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Searched refs:wmask (Results 1 – 25 of 34) sorted by relevance

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/qemu/hw/cxl/
H A Dcxl-component-utils.c383 uint8_t *wmask = pdev->wmask; in cxl_component_create_dvsec() local
403 wmask[offset + offsetof(CXLDVSECDevice, ctrl)] = 0xFD; in cxl_component_create_dvsec()
404 wmask[offset + offsetof(CXLDVSECDevice, ctrl) + 1] = 0x4F; in cxl_component_create_dvsec()
406 wmask[offset + offsetof(CXLDVSECDevice, ctrl2)] = 0x0F; in cxl_component_create_dvsec()
408 wmask[offset + offsetof(CXLDVSECDevice, lock)] = 0x01; in cxl_component_create_dvsec()
410 wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi)] = 0xFF; in cxl_component_create_dvsec()
411 wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 1] = 0xFF; in cxl_component_create_dvsec()
412 wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 2] = 0xFF; in cxl_component_create_dvsec()
413 wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 3] = 0xFF; in cxl_component_create_dvsec()
414 wmask[offset + offsetof(CXLDVSECDevice, range1_base_lo) + 3] = 0xF0; in cxl_component_create_dvsec()
[all …]
/qemu/hw/pci/
H A Dpcie_sriov.c50 pci_set_word(dev->wmask + sriov_cap + PCI_SRIOV_NUM_VF, 0); in register_vfs()
64 pci_set_word(dev->wmask + dev->exp.sriov_cap + PCI_SRIOV_NUM_VF, 0xffff); in unregister_vfs()
74 uint8_t *wmask; in pcie_sriov_pf_init_common() local
120 wmask = dev->wmask + offset; in pcie_sriov_pf_init_common()
121 pci_set_word(wmask + PCI_SRIOV_CTRL, in pcie_sriov_pf_init_common()
123 pci_set_word(wmask + PCI_SRIOV_NUM_VF, 0xffff); in pcie_sriov_pf_init_common()
124 pci_set_word(wmask + PCI_SRIOV_SYS_PGSIZE, 0x553); in pcie_sriov_pf_init_common()
201 uint64_t wmask; in pcie_sriov_pf_init_vf_bar() local
209 wmask = ~(size - 1); in pcie_sriov_pf_init_vf_bar()
215 pci_set_quad(dev->wmask + addr, wmask); in pcie_sriov_pf_init_vf_bar()
[all …]
H A Dshpc.c454 uint8_t wmask = shpc->wmask[a]; in shpc_write() local
456 assert(!(wmask & w1cmask)); in shpc_write()
457 shpc->config[a] = (shpc->config[a] & ~wmask) | (val & wmask); in shpc_write()
516 pci_set_byte(d->wmask + config_offset + SHPC_CAP_DWORD_SELECT, 0xff); in shpc_cap_add_config()
517 pci_set_long(d->wmask + config_offset + SHPC_CAP_DWORD_DATA, 0xffffffff); in shpc_cap_add_config()
670 shpc->wmask = g_malloc0(SHPC_SIZEOF(d)); in shpc_init()
677 pci_set_byte(shpc->wmask + SHPC_CMD_CODE, 0xff); in shpc_init()
678 pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX); in shpc_init()
679 pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX); in shpc_init()
680 pci_set_long(shpc->wmask + SHPC_SERR_INT, in shpc_init()
[all …]
H A Dpcie.c246 pci_set_word(dev->wmask + pos + PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_EETLPPB); in pcie_cap_init()
250 pci_set_long(dev->wmask + PCI_CONFIG_SPACE_SIZE, 0); in pcie_cap_init()
366 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL, in pcie_cap_deverr_init()
385 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_LNKCTL, in pcie_cap_lnkctl_init()
700 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, in pcie_cap_slot_init()
710 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, in pcie_cap_slot_init()
722 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, in pcie_cap_slot_init()
931 pci_set_word(dev->wmask + dev->exp.exp_cap + PCI_EXP_RTCTL, in pcie_cap_root_init()
952 pci_word_test_and_set_mask(dev->wmask + dev->exp.exp_cap + PCI_EXP_DEVCTL, in pcie_cap_flr_init()
976 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL2, in pcie_cap_arifwd_init()
[all …]
H A Dpci.c545 pci_get_word(dev->wmask + PCI_COMMAND) | in pci_do_device_reset()
548 pci_get_word(dev->wmask + PCI_STATUS) | in pci_do_device_reset()
552 pci_get_word(dev->wmask + PCI_INTERRUPT_LINE) | in pci_do_device_reset()
797 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) { in get_pci_config_device()
801 s->cmask[i], s->wmask[i], s->w1cmask[i]); in get_pci_config_device()
1025 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; in pci_init_wmask()
1026 dev->wmask[PCI_INTERRUPT_LINE] = 0xff; in pci_init_wmask()
1027 pci_set_word(dev->wmask + PCI_COMMAND, in pci_init_wmask()
1030 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR); in pci_init_wmask()
1032 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, in pci_init_wmask()
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H A Dmsi.c237 pci_set_word(dev->wmask + msi_flags_off(dev), in msi_init()
239 pci_set_long(dev->wmask + msi_address_lo_off(dev), in msi_init()
242 pci_set_long(dev->wmask + msi_address_hi_off(dev), 0xffffffff); in msi_init()
244 pci_set_word(dev->wmask + msi_data_off(dev, msi64bit), 0xffff); in msi_init()
248 pci_set_long(dev->wmask + msi_mask_off(dev, msi64bit), in msi_init()
H A Dpcie_aer.c119 pci_set_long(dev->wmask + offset + PCI_ERR_UNCOR_MASK, in pcie_aer_init()
125 pci_set_long(dev->wmask + offset + PCI_ERR_UNCOR_SEVER, in pcie_aer_init()
133 pci_set_long(dev->wmask + offset + PCI_ERR_COR_MASK, in pcie_aer_init()
141 pci_set_long(dev->wmask + offset + PCI_ERR_CAP, in pcie_aer_init()
147 pci_set_long(dev->wmask + offset + PCI_ERR_CAP, in pcie_aer_init()
157 pci_word_test_and_set_mask(dev->wmask + PCI_BRIDGE_CONTROL, in pcie_aer_init()
748 pci_set_long(dev->wmask + pos + PCI_ERR_ROOT_COMMAND, in pcie_aer_root_init()
H A Dslotid_cap.c40 d->wmask[cap + PCI_SID_CHASSIS_NR] = 0xff; in slotid_cap_init()
H A Dpcie_port.c38 pci_word_test_and_clear_mask(d->wmask + PCI_BRIDGE_CONTROL, in pcie_port_init_reg()
H A Dmsix.c374 dev->wmask[cap + MSIX_CONTROL_OFFSET] |= MSIX_ENABLE_MASK | in msix_init()
561 ~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET]; in msix_reset()
/qemu/hw/audio/
H A Dintel-hda.c211 uint32_t wmask; /* write mask */ member
637 .wmask = 0x0103,
644 .wmask = 0x7fff,
651 .wmask = 0x7fff,
661 .wmask = 0xc00000ff,
668 .wmask = 0xc00000ff,
685 .wmask = 0xffffff80,
691 .wmask = 0xffffffff,
697 .wmask = 0xff,
704 .wmask = 0x80ff,
[all …]
/qemu/hw/pci-bridge/
H A Dgen_pcie_root_port.c107 pci_word_test_and_clear_mask(d->wmask + PCI_COMMAND, in gen_rp_realize()
109 d->wmask[PCI_IO_BASE] = 0; in gen_rp_realize()
110 d->wmask[PCI_IO_LIMIT] = 0; in gen_rp_realize()
H A Dsimba.c63 pci_set_word(dev->wmask + PCI_IO_BASE_UPPER16, 0xffff); in simba_pci_bridge_realize()
64 pci_set_word(dev->wmask + PCI_IO_LIMIT_UPPER16, 0xffff); in simba_pci_bridge_realize()
H A Dcxl_root_port.c171 pci_word_test_and_clear_mask(pci_dev->wmask + PCI_COMMAND, in cxl_rp_realize()
173 pci_dev->wmask[PCI_IO_BASE] = 0; in cxl_rp_realize()
174 pci_dev->wmask[PCI_IO_LIMIT] = 0; in cxl_rp_realize()
/qemu/hw/pci-host/
H A Dq35.c351 pd->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK_LCK; in mch_update_smram()
352 pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK; in mch_update_smram()
435 pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] = in mch_update_smbase_smram()
445 if (pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] == 0xff) { in mch_update_smbase_smram()
452 pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] &= in mch_update_smbase_smram()
553 d->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK; in mch_reset()
554 d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK; in mch_reset()
562 d->wmask[MCH_HOST_BRIDGE_F_SMBASE] = 0xff; in mch_reset()
H A Dgt64120.c1232 pci_set_long(d->wmask + PCI_BASE_ADDRESS_0, 0xfffff008); /* SCS[1:0] */ in gt64120_pci_realize()
1233 pci_set_long(d->wmask + PCI_BASE_ADDRESS_1, 0xfffff008); /* SCS[3:2] */ in gt64120_pci_realize()
1234 pci_set_long(d->wmask + PCI_BASE_ADDRESS_2, 0xfffff008); /* CS[2:0] */ in gt64120_pci_realize()
1235 pci_set_long(d->wmask + PCI_BASE_ADDRESS_3, 0xfffff008); /* CS[3], BootCS */ in gt64120_pci_realize()
1236 pci_set_long(d->wmask + PCI_BASE_ADDRESS_4, 0xfffff000); /* ISD MMIO */ in gt64120_pci_realize()
1237 pci_set_long(d->wmask + PCI_BASE_ADDRESS_5, 0xfffff001); /* ISD I/O */ in gt64120_pci_realize()
/qemu/hw/isa/
H A Dlpc_ich9.c532 uint16_t wmask; in ich9_lpc_pmcon_update() local
544 wmask = pci_get_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1); in ich9_lpc_pmcon_update()
545 wmask &= ~ICH9_LPC_GEN_PMCON_1_SMI_LOCK; in ich9_lpc_pmcon_update()
546 pci_set_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1, wmask); in ich9_lpc_pmcon_update()
727 pci_set_long(d->wmask + ICH9_LPC_PMBASE, in ich9_lpc_realize()
729 pci_set_byte(d->wmask + ICH9_LPC_PMBASE, in ich9_lpc_realize()
/qemu/hw/vfio/
H A Digd.c609 pci_set_long(vdev->pdev.wmask + IGD_ASLS, ~0); in vfio_pci_igd_config_quirk()
624 pci_set_long(vdev->pdev.wmask + IGD_GMCH, 0); in vfio_pci_igd_config_quirk()
634 pci_set_long(vdev->pdev.wmask + IGD_BDSM, ~0); in vfio_pci_igd_config_quirk()
638 pci_set_quad(vdev->pdev.wmask + IGD_BDSM_GEN11, ~0); in vfio_pci_igd_config_quirk()
/qemu/hw/ide/
H A Dcmd646.c266 dev->wmask[CFR] = 0x0; in pci_cmd646_ide_realize()
268 dev->wmask[ARTTIM23] = 0x0; in pci_cmd646_ide_realize()
270 dev->wmask[MRDMODE] = 0x0; in pci_cmd646_ide_realize()
H A Dvia.c205 dev->wmask[PCI_INTERRUPT_LINE] = 0; in via_ide_realize()
206 dev->wmask[PCI_CLASS_PROG] = 5; in via_ide_realize()
/qemu/linux-user/xtensa/
H A Dtarget_syscall.h22 xtensa_reg_t wmask; /* 28 */ member
/qemu/include/hw/pci/
H A Dshpc.h24 uint8_t *wmask; member
H A Dpci_device.h74 uint8_t *wmask; member
/qemu/hw/i386/
H A Dintel_iommu.c96 uint64_t wmask, uint64_t w1cmask) in vtd_define_quad() argument
99 stq_le_p(&s->wmask[addr], wmask); in vtd_define_quad()
109 uint32_t wmask, uint32_t w1cmask) in vtd_define_long() argument
112 stl_le_p(&s->wmask[addr], wmask); in vtd_define_long()
125 uint64_t wmask = ldq_le_p(&s->wmask[addr]); in vtd_set_quad() local
128 ((oldval & ~wmask) | (val & wmask)) & ~(w1cmask & val)); in vtd_set_quad()
134 uint32_t wmask = ldl_le_p(&s->wmask[addr]); in vtd_set_long() local
137 ((oldval & ~wmask) | (val & wmask)) & ~(w1cmask & val)); in vtd_set_long()
4603 memset(s->wmask, 0, DMAR_REG_SIZE); in vtd_init()
/qemu/include/hw/i386/
H A Dintel_iommu.h260 uint8_t wmask[DMAR_REG_SIZE]; /* R/W bytes */ member

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