| /kvm-unit-tests/x86/ |
| H A D | hyperv_stimer.c | 40 struct stimer timer[HV_SYNIC_STIMER_COUNT]; member
62 static void stimer_init(struct stimer *timer, int index) in stimer_init() argument
64 memset(timer, 0, sizeof(*timer)); in stimer_init()
65 timer->index = index; in stimer_init()
76 for (i = 0; i < ARRAY_SIZE(svcpu->timer); i++) { in synic_enable()
77 stimer_init(&svcpu->timer[i], i); in synic_enable()
84 static void stimer_shutdown(struct stimer *timer) in stimer_shutdown() argument
86 wrmsr(HV_X64_MSR_STIMER0_CONFIG + 2*timer->index, 0); in stimer_shutdown()
89 static void process_stimer_expired(struct stimer *timer) in process_stimer_expired() argument
91 atomic_inc(&timer->fire_count); in process_stimer_expired()
[all …]
|
| H A D | hyperv.h | 45 * Synthetic Timer MSRs. Four timers per vcpu.
66 * Synthetic timer configuration.
98 /* Timer notification messages. */
154 /* Define timer message payload structure. */
158 uint64_t expiration_time; /* When the timer expired */
|
| H A D | tscdeadline_latency.c | 96 printf("tsc deadline timer enabled\n"); in test_tsc_deadline_timer()
98 printf("tsc deadline timer not detected, aborting\n"); in test_tsc_deadline_timer()
|
| H A D | apic.c | 59 report(tdt_count == 1, "tsc deadline timer"); in __test_tsc_deadline_timer()
60 report(rdmsr(MSR_IA32_TSCDEADLINE) == 0, "tsc deadline timer clearing"); in __test_tsc_deadline_timer()
81 report_skip("tsc deadline timer not detected"); in test_tsc_deadline_timer()
494 /* Set "Initial Counter Register", which starts the timer */ in test_apic_timer_one_shot()
500 * For LVT Timer clock, SDM vol 3 10.5.4 says it should be in test_apic_timer_one_shot()
507 "APIC LVT timer one shot"); in test_apic_timer_one_shot()
630 * Specifically wait for timer wrap around and skip 0. in test_apic_change_mode()
640 * Keep the same TMICT and change timer mode to one-shot in test_apic_change_mode()
|
| H A D | unittests.cfg | 31 # Hide x2APIC and don't create a Programmable Interval Timer (PIT, a.k.a 8254)
85 # enabled, do not create a Programmable Interval Timer (PIT, a.k.a 8254), since
|
| H A D | vmx_tests.c | 131 printf("\tPreemption timer is not supported\n"); in preemption_timer_init()
184 "busy-wait for preemption timer"); in preemption_timer_exit_handler()
193 "preemption timer during hlt"); in preemption_timer_exit_handler()
203 "preemption timer with 0 value"); in preemption_timer_exit_handler()
228 report_fail("busy-wait for preemption timer"); in preemption_timer_exit_handler()
233 report_fail("preemption timer during hlt"); in preemption_timer_exit_handler()
243 report_fail("preemption timer with 0 value (vmcall stage 5)"); in preemption_timer_exit_handler()
4928 * If the "activate VMX-preemption timer" VM-execution control is 0, the
4929 * the "save VMX-preemption timer value" VM-exit control must also be 0.
4942 …report_skip("%s : \"Save-VMX-preemption-timer\" and/or \"Enable-VMX-preemption-timer\" control not… in test_vmx_preemption_timer()
[all …]
|
| /kvm-unit-tests/lib/arm/ |
| H A D | timer.c | 14 #include <asm/timer.h>
25 node = fdt_node_offset_by_compatible(fdt, -1, "arm,armv8-timer"); in timer_save_state_fdt()
35 * From Linux devicetree timer binding documentation in timer_save_state_fdt()
38 * secure timer irq in timer_save_state_fdt()
39 * non-secure timer irq (ptimer) in timer_save_state_fdt()
40 * virtual timer irq (vtimer) in timer_save_state_fdt()
41 * hypervisor timer irq in timer_save_state_fdt()
|
| /kvm-unit-tests/lib/riscv/ |
| H A D | timer.c | 14 #include <asm/timer.h>
49 assert_msg(false, "No timer to start!"); in timer_start()
58 * exact number to decide *not* to update the timer. IOW, if in timer_stop()
59 * we used ULONG_MAX, then we wouldn't stop the timer at all, in timer_stop()
70 assert_msg(false, "No timer to stop!"); in timer_stop()
|
| H A D | delay.c | 8 #include <asm/timer.h>
|
| /kvm-unit-tests/arm/ |
| H A D | timer.c | 2 * Timer tests for the ARM virt machine.
11 #include <asm/timer.h>
170 /* Check that the timer condition is met. */
202 /* Program timer to fire in 10 ms */ in test_cval_10msec()
207 /* Wait for the timer to fire */ in test_cval_10msec()
215 report_info("After timer: 0x%016lx", after_timer); in test_cval_10msec()
240 * timer state and we want to test the timer output signal. We can in test_timer_pending()
245 /* Enable the timer, but schedule it for much later */ in test_timer_pending()
258 report(!info->irq_received, "no interrupt when timer is disabled"); in test_timer_pending()
317 report(left <= 0, "timer has expired"); in test_timer_tval()
|
| H A D | unittests.cfg | 252 # Timer tests
253 [timer]
254 file = timer.flat
255 groups = timer
|
| H A D | micro-bench.c | 25 #include <asm/timer.h>
93 printf("Timer Frequency %d Hz (Output in microseconds)\n", cntfrq); in test_init()
253 * We use a 10msec timer to test the latency of PPI, in timer_post()
|
| H A D | Makefile.arm64 | 61 tests = $(TEST_DIR)/timer.$(exe)
|
| H A D | Makefile.common | 63 cflatobjs += lib/arm/timer.o
|
| /kvm-unit-tests/s390x/ |
| H A D | panic-loop-extint.c | 24 * Because the CPU timer subclass mask is still enabled, the CPU timer in ext_int_cleanup()
27 * this, clear the CPU timer subclass mask here. in ext_int_cleanup()
|
| H A D | diag288.c | 3 * Timer Event DIAG288 test
60 report_prefix_push("min timer"); in test_specs()
83 /* If watchdog doesn't bite, the cpu timer does */ in test_bite()
|
| H A D | pv-icptcode.c | 26 * The hypervisor should not be able to decrease the cpu timer by an
30 * Warning: A lot of things influence time so decreasing the timer by
55 /* Cpu timer counts down so adding a ms should lead to a validity */ in test_validity_timing()
63 * We are not allowed to decrement the timer more than the in test_validity_timing()
|
| /kvm-unit-tests/lib/arm64/asm/ |
| H A D | timer.h | 1 #include "../../arm/asm/timer.h"
|
| /kvm-unit-tests/lib/x86/ |
| H A D | apic.c | 273 * APIC timer runs at the 'core crystal clock', divided by the value in in apic_start_timer()
288 /* Stop the timer/counter. */ in apic_cleanup_timer()
291 /* Mask the timer interrupt in the local vector table. */ in apic_cleanup_timer()
294 /* Enable interrupts to ensure any pending timer IRQs are serviced. */ in apic_cleanup_timer()
|
| /kvm-unit-tests/riscv/ |
| H A D | sbi.c | 29 #include <asm/timer.h>
291 report(!ret.error, "set timer%s", mask_test_str); in timer_check_set_timer()
293 report_info("set timer%s failed with %ld\n", mask_test_str, ret.error); in timer_check_set_timer()
298 report(timer_info.timer_works, "timer interrupt received%s", mask_test_str); in timer_check_set_timer()
299 …report(timer_info.timer_irq_set, "pending timer interrupt bit set in irq handler%s", mask_test_str… in timer_check_set_timer()
303 "pending timer interrupt bit cleared by setting timer to -1"); in timer_check_set_timer()
308 report(duration >= d && duration <= (d + margin), "timer delay honored%s", mask_test_str); in timer_check_set_timer()
311 report(timer_info.timer_irq_count == 1, "timer interrupt received exactly once%s", mask_test_str); in timer_check_set_timer()
339 report_skip("timer irq enable bit is not writable, skipping mask irq test"); in check_time()
344 report(pending, "timer immediately pending by setting timer to 0"); in check_time()
[all …]
|
| /kvm-unit-tests/s390x/snippets/asm/ |
| H A D | pv-icpt-vir-timing.S | 3 * Sets a cpu timer which the host can manipulate to check if it will
|
| /kvm-unit-tests/powerpc/ |
| H A D | timebase.c | 133 mdelay(100); /* Give the timer a chance to run */ in test_dec()
149 mdelay(100); /* Give the timer a chance to run */ in test_dec()
224 mdelay(100); /* Give the timer a chance to run */ in test_hdec()
250 mdelay(100); /* Give the timer a chance to run */ in test_hdec()
|
| /kvm-unit-tests/ |
| H A D | errata.txt | 6 7b6b46311a85 : 4.11 : KVM: arm/arm64: Emulate the EL1 phys timer regist…
|
| H A D | .gitlab-ci.yml | 51 timer
111 timer
|
| /kvm-unit-tests/lib/ |
| H A D | acpi.h | 93 u32 pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
127 …struct acpi_generic_address xpm_timer_block; /* 64-bit Extended Power Mgt Timer Ctrl Reg Blk addre…
|