Searched full:syscon (Results 1 – 8 of 8) sorted by relevance
/qemu/target/tricore/ |
H A D | gdbstub.c | 60 return env->SYSCON; in tricore_cpu_gdb_read_csfr() 102 env->SYSCON = val; in tricore_cpu_gdb_write_csfr()
|
H A D | csfr.h.inc | 11 A(0xfe14, SYSCON, TRICORE_FEATURE_13)
|
H A D | op_helper.c | 46 env->SYSCON |= MASK_SYSCON_FCD_SF; in raise_exception_sync_internal()
|
/qemu/hw/openrisc/ |
H A D | virt.c | 269 qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon"); in openrisc_virt_test_init() 278 qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-reboot"); in openrisc_virt_test_init() 286 qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-poweroff"); in openrisc_virt_test_init()
|
/qemu/hw/loongarch/ |
H A D | virt-fdt-build.c | 456 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon"); in fdt_add_ged_reset() 467 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot"); in fdt_add_ged_reset() 475 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-poweroff"); in fdt_add_ged_reset()
|
/qemu/hw/arm/ |
H A D | mps3r.c | 605 * initial setting for the SCC SYSCON 0x000 register is 0x21, meaning in mps3r_an536_class_init() 614 * the user to set the initial value of the SYSCON 0x000 register. in mps3r_an536_class_init()
|
/qemu/hw/mips/ |
H A D | boston.c | 521 "img,boston-platform-regs", "syscon" in create_fdt() 632 qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-reboot"); in create_fdt()
|
/qemu/hw/riscv/ |
H A D | virt.c | 933 "sifive,test1", "sifive,test0", "syscon" in create_fdt_reset() 946 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot"); in create_fdt_reset() 954 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-poweroff"); in create_fdt_reset()
|