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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Daltr,msi-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/altr,msi-controller.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Matthew Gerlach <matthew.gerlach@linux.intel.com>
16 - altr,msi-1.0
20 - description: CSR registers
21 - description: Vectors slave port region
23 reg-names:
25 - const: csr
[all …]
H A Dloongson,pch-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
19 const: loongson,pch-msi-1.0
24 loongson,msi-base-vec:
32 loongson,msi-num-vecs:
34 u32 value of the number of parent HyperTransport vectors allocated
40 msi-controller: true
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/linux/drivers/vdpa/alibaba/
H A Deni_vdpa.c1 // SPDX-License-Identifier: GPL-2.0-only
25 dev_err(&pdev->dev, "%s"fmt, "eni_vdpa: ", ##__VA_ARGS__)
27 dev_dbg(&pdev->dev, "%s"fmt, "eni_vdpa: ", ##__VA_ARGS__)
29 dev_info(&pdev->dev, "%s"fmt, "eni_vdpa: ", ##__VA_ARGS__)
46 int vectors; member
58 return &eni_vdpa->ldev; in vdpa_to_ldev()
77 ENI_ERR(ldev->pci_dev, in eni_vdpa_set_driver_features()
79 return -EINVAL; in eni_vdpa_set_driver_features()
104 int irq = eni_vdpa->vring[idx].irq; in eni_vdpa_get_vq_irq()
107 return -EINVAL; in eni_vdpa_get_vq_irq()
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/linux/drivers/net/ethernet/hisilicon/hibmcge/
H A Dhbg_debugfs.c1 // SPDX-License-Identifier: GPL-2.0+
22 #define state_str_true_false(p, s) str_true_false(test_bit(s, &(p)->state))
27 u32 irq_mask = ring->dir == HBG_DIR_TX ? HBG_INT_MSK_TX_B : in hbg_dbg_ring()
30 seq_printf(s, "ring used num: %u\n", in hbg_dbg_ring()
32 seq_printf(s, "ring max num: %u\n", ring->len); in hbg_dbg_ring()
33 seq_printf(s, "ring head: %u, tail: %u\n", ring->head, ring->tail); in hbg_dbg_ring()
34 seq_printf(s, "fifo used num: %u\n", in hbg_dbg_ring()
35 hbg_hw_get_fifo_used_num(priv, ring->dir)); in hbg_dbg_ring()
36 seq_printf(s, "fifo max num: %u\n", in hbg_dbg_ring()
37 hbg_get_spec_fifo_max_num(priv, ring->dir)); in hbg_dbg_ring()
[all …]
/linux/drivers/net/ethernet/hisilicon/hns3/hns3vf/
H A Dhclgevf_main.h1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* Copyright (c) 2016-2017 Hisilicon Limited. */
28 * possible vector-per-VF is {VFn(1-32), VECTn(32 + 1)}.
103 (pci_resource_len((hdev)->pdev, HCLGEVF_MEM_BAR) >> 1)
112 hclge_comm_read_reg((a)->hw.io_base, reg)
114 hclge_comm_write_reg((a)->hw.io_base, reg, value)
233 u16 num_tqps; /* num task queue pairs of this VF */
238 u16 num_alloc_vport; /* num vports this driver supports */
241 u16 num_tx_desc; /* desc num of per tx queue */
242 u16 num_rx_desc; /* desc num of per rx queue */
[all …]
H A Dhclgevf_main.c1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
38 /* hclgevf_cmd_send - send command to command queue
41 * @num : the number of descriptors to be sent
46 int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclge_desc *desc, int num) in hclgevf_cmd_send() argument
48 return hclge_comm_cmd_send(&hw->hw, desc, num); in hclgevf_cmd_send()
52 int num, bool is_special) in hclgevf_trace_cmd_send() argument
56 trace_hclge_vf_cmd_send(hw, desc, 0, num); in hclgevf_trace_cmd_send()
61 for (i = 1; i < num; i++) in hclgevf_trace_cmd_send()
62 trace_hclge_vf_cmd_send(hw, &desc[i], i, num); in hclgevf_trace_cmd_send()
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/linux/arch/arm/mm/
H A Ddump.c1 // SPDX-License-Identifier: GPL-2.0-only
31 { VECTORS_BASE, "Vectors" },
32 { VECTORS_BASE + PAGE_SIZE * 2, "Vectors End" },
33 { -1, NULL },
205 size_t num; member
219 .num = ARRAY_SIZE(section_bits),
223 .num = ARRAY_SIZE(pte_bits),
227 static void dump_prot(struct pg_state *st, const struct prot_bits *bits, size_t num) in dump_prot() argument
231 for (i = 0; i < num; i++, bits++) { in dump_prot()
234 if ((st->current_prot & bits->mask) == bits->val) in dump_prot()
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H A Dpmsa-v7.c52 /* Data-side / unified region attributes */
76 /* Optional instruction-side region attributes */
78 /* I-side Region access control register */
84 /* I-side Region size register */
90 /* I-side Region base address register */
108 /* Data-side / unified region attributes */
137 /* ARMv7-M only supports a unified MPU, so I-side operations are nop */
149 phys_addr_t abase = base & ~(size - 1); in try_split_region()
150 phys_addr_t asize = base + size - abase; in try_split_region()
157 bdiff = base - abase; in try_split_region()
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/linux/drivers/virtio/
H A Dvirtio_pci_common.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Virtio PCI driver - APIs for common functionality for all device versions
41 /* MSI-X vector (or none) */
86 /* MSI-X support */
93 /* Number of available vectors */
95 /* Vectors allocated, excluding per-vq vectors if any */
111 int (*avq_index)(struct virtio_device *vdev, u16 *index, u16 *num);
114 /* Constants for MSI-X */
116 * virtqueues Thus, we need at least 2 vectors for MSI. */
132 /* the config->del_vqs() implementation */
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/linux/security/selinux/ss/
H A Dpolicydb.h1 /* SPDX-License-Identifier: GPL-2.0-only */
12 * Copyright (C) 2004-2005 Trusted Computer Solutions, Inc.
17 * Copyright (C) 2003-2004 Tresys Technology, LLC
34 * common prefixes for access vectors, classes,
43 /* Attributes of a common prefix for access vectors */
54 struct symtab permissions; /* class-specific permission symbol table */
123 struct mls_range range; /* MLS range (min - max) for user */
250 /* symbol names indexed by (value - 1) */
253 /* class, role, and user attributes indexed by (value - 1) */
259 /* type enforcement access vectors and transitions */
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/linux/drivers/net/ethernet/intel/i40e/
H A Di40e.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2013 - 2021 Intel Corporation. */
29 #define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024)
38 (test_bit(I40E_HW_CAP_RSS_AQ, (pf)->hw.caps) ? 4 : 1)
42 (test_bit(I40E_HW_CAP_128_QP_RSS, (pf)->hw.caps) ? 128 : 64)
69 (&(((union i40e_rx_desc *)((R)->desc))[i]))
71 (&(((struct i40e_tx_desc *)((R)->desc))[i]))
73 (&(((struct i40e_tx_context_desc *)((R)->desc))[i]))
75 (&(((struct i40e_filter_program_desc *)((R)->desc))[i]))
182 * - LINK_DOWN_ON_CLOSE_ENA is configurable at host OS run-time and
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/linux/drivers/irqchip/
H A Dirq-riscv-imsic-state.c1 // SPDX-License-Identifier: GPL-2.0
7 #define pr_fmt(fmt) "riscv-imsic: " fmt
22 #include "irq-riscv-imsic-state.h"
63 return imsic ? &imsic->global : NULL; in imsic_get_global_config()
74 imask = BIT(id & (__riscv_xlen - 1)); in __imsic_eix_read_clear()
102 * are XLEN-wide and we must not touch IDs which in __imsic_eix_update()
106 for (i = id & (__riscv_xlen - 1); id < last_id && i < __riscv_xlen; i++) { in __imsic_eix_update()
134 lockdep_assert_held(&lpriv->lock); in __imsic_local_sync()
136 for_each_set_bit(i, lpriv->dirty_bitmap, imsic->global.nr_ids + 1) { in __imsic_local_sync()
139 vec = &lpriv->vectors[i]; in __imsic_local_sync()
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H A Dirq-mbigen.c1 // SPDX-License-Identifier: GPL-2.0-only
22 /* 64 irqs (Pin0-pin63) are reserved for each mbigen chip */
57 * struct mbigen_device - holds the information of mbigen device.
85 hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP; in get_mbigen_vec_reg()
97 hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP; in get_mbigen_type_reg()
118 void __iomem *base = data->chip_data; in mbigen_eoi_irq()
121 get_mbigen_clear_reg(data->hwirq, &mask, &addr); in mbigen_eoi_irq()
130 void __iomem *base = data->chip_data; in mbigen_set_type()
134 return -EINVAL; in mbigen_set_type()
136 get_mbigen_type_reg(data->hwirq, &mask, &addr); in mbigen_set_type()
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/linux/arch/xtensa/variants/test_mmuhifi_c3/include/variant/
H A Dcore.h7 * Copyright (c) 1999-2009 Tensilica Inc.
24 /*----------------------------------------------------------------------
26 ----------------------------------------------------------------------*/
28 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
30 #define XCHAL_NUM_AREGS 32 /* num of physical addr regs */
34 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
35 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
45 #define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
59 #define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */
70 #define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
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/linux/arch/xtensa/variants/dc232b/include/variant/
H A Dcore.h8 * Copyright (c) 1999-2007 Tensilica Inc.
25 /*----------------------------------------------------------------------
27 ----------------------------------------------------------------------*/
29 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
31 #define XCHAL_NUM_AREGS 32 /* num of physical addr regs */
35 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
36 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
46 #define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
60 #define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */
68 #define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
[all …]
/linux/arch/xtensa/variants/dc233c/include/variant/
H A Dcore.h2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
10 Copyright (c) 1999-2010 Tensilica Inc.
45 /*----------------------------------------------------------------------
47 ----------------------------------------------------------------------*/
49 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
51 #define XCHAL_NUM_AREGS 32 /* num of physical addr regs */
55 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
56 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
66 #define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
80 #define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */
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/linux/drivers/net/ethernet/brocade/bna/
H A Dbnad.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Linux network driver for QLogic BR-series Converged Network Adapter.
6 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
7 * Copyright (c) 2014-2015 QLogic Corporation
58 (((_bnad)->cfg_flags & BNAD_CF_MSIX) ? \
59 ((_bnad)->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector) : \
60 ((_bnad)->pcidev->irq))
64 (_res_info)->res_type = BNA_RES_T_MEM; \
65 (_res_info)->res_u.mem_info.mem_type = BNA_MEM_T_KVA; \
66 (_res_info)->res_u.mem_info.num = (_num); \
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/linux/arch/x86/kernel/apic/
H A Dvector.c1 // SPDX-License-Identifier: GPL-2.0-only
78 info->mask = mask; in init_irq_alloc_info()
94 while (irqd->parent_data) in apic_chip_data()
95 irqd = irqd->parent_data; in apic_chip_data()
97 return irqd->chip_data; in apic_chip_data()
104 return apicd ? &apicd->hw_irq_cfg : NULL; in irqd_cfg()
119 INIT_HLIST_NODE(&apicd->clist); in alloc_apic_chip_data()
135 apicd->hw_irq_cfg.vector = vector; in apic_update_irq_cfg()
136 apicd->hw_irq_cfg.dest_apicid = apic->calc_dest_apicid(cpu); in apic_update_irq_cfg()
138 trace_vector_config(irqd->irq, vector, cpu, in apic_update_irq_cfg()
[all …]
/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drvu.c1 // SPDX-License-Identifier: GPL-2.0
36 int type, int num,
63 struct rvu_hwinfo *hw = rvu->hw; in rvu_setup_hw_capabilities()
65 hw->cap.nix_tx_aggr_lvl = NIX_TXSCH_LVL_TL1; in rvu_setup_hw_capabilities()
66 hw->cap.nix_fixed_txschq_mapping = false; in rvu_setup_hw_capabilities()
67 hw->cap.nix_shaping = true; in rvu_setup_hw_capabilities()
68 hw->cap.nix_tx_link_bp = true; in rvu_setup_hw_capabilities()
69 hw->cap.nix_rx_multicast = true; in rvu_setup_hw_capabilities()
70 hw->cap.nix_shaper_toggle_wait = false; in rvu_setup_hw_capabilities()
71 hw->cap.npc_hash_extract = false; in rvu_setup_hw_capabilities()
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/linux/drivers/vdpa/ifcvf/
H A Difcvf_main.c1 // SPDX-License-Identifier: GPL-2.0-only
24 if (vf->config_cb.callback) in ifcvf_config_changed()
25 return vf->config_cb.callback(vf->config_cb.private); in ifcvf_config_changed()
34 if (vring->cb.callback) in ifcvf_vq_intr_handler()
35 return vring->cb.callback(vring->cb.private); in ifcvf_vq_intr_handler()
46 for (i = 0; i < vf->nr_vring; i++) { in ifcvf_vqs_reused_intr_handler()
47 vring = &vf->vring[i]; in ifcvf_vqs_reused_intr_handler()
48 if (vring->cb.callback) in ifcvf_vqs_reused_intr_handler()
49 vring->cb.callback(vring->cb.private); in ifcvf_vqs_reused_intr_handler()
60 isr = vp_ioread8(vf->isr); in ifcvf_dev_intr_handler()
[all …]
/linux/drivers/net/ethernet/marvell/octeontx2/af/cn20k/
H A Dmbox_init.c1 // SPDX-License-Identifier: GPL-2.0
19 struct rvu *rvu = rvu_irq_data->rvu; in cn20k_afvf_mbox_intr_handler()
26 intr = rvupf_read64(rvu, rvu_irq_data->intr_status); in cn20k_afvf_mbox_intr_handler()
27 rvupf_write64(rvu, rvu_irq_data->intr_status, intr); in cn20k_afvf_mbox_intr_handler()
30 trace_otx2_msg_interrupt(rvu->pdev, "VF(s) to AF", intr); in cn20k_afvf_mbox_intr_handler()
32 rvu_irq_data->afvf_queue_work_hdlr(&rvu->afvf_wq_info, rvu_irq_data->start, in cn20k_afvf_mbox_intr_handler()
33 rvu_irq_data->mdevs, intr); in cn20k_afvf_mbox_intr_handler()
44 /* irq data for 4 VFPF intr vectors */ in cn20k_register_afvf_mbox_intr()
45 irq_data = devm_kcalloc(rvu->dev, 4, in cn20k_register_afvf_mbox_intr()
48 return -ENOMEM; in cn20k_register_afvf_mbox_intr()
[all …]
/linux/drivers/vdpa/solidrun/
H A Dsnet_main.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2022-2023 SolidRun
7 * Author: Alvaro Karsz <alvaro.karsz@solid-run.com>
42 if (likely(snet->cb.callback)) in snet_cfg_irq_hndlr()
43 return snet->cb.callback(snet->cb.private); in snet_cfg_irq_hndlr()
52 if (likely(vq->cb.callback)) in snet_vq_irq_hndlr()
53 return vq->cb.callback(vq->cb.private); in snet_vq_irq_hndlr()
60 struct psnet *psnet = snet->psnet; in snet_free_irqs()
66 pdev = snet->pdev->physfn; in snet_free_irqs()
68 pdev = snet->pdev; in snet_free_irqs()
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/linux/kernel/irq/
H A Dmatrix.c1 // SPDX-License-Identifier: GPL-2.0
41 * irq_alloc_matrix - Allocate a irq_matrix structure and initialize it
58 m->system_map = &m->scratch_map[matrix_size]; in irq_alloc_matrix()
60 m->matrix_bits = matrix_bits; in irq_alloc_matrix()
61 m->alloc_start = alloc_start; in irq_alloc_matrix()
62 m->alloc_end = alloc_end; in irq_alloc_matrix()
63 m->alloc_size = alloc_end - alloc_start; in irq_alloc_matrix()
64 m->maps = __alloc_percpu(struct_size(m->maps, alloc_map, matrix_size * 2), in irq_alloc_matrix()
65 __alignof__(*m->maps)); in irq_alloc_matrix()
66 if (!m->maps) { in irq_alloc_matrix()
[all …]
/linux/tools/testing/selftests/kvm/lib/arm64/
H A Dprocessor.c1 // SPDX-License-Identifier: GPL-2.0
25 return (v + vm->page_size) & ~(vm->page_size - 1); in page_align()
30 unsigned int shift = (vm->pgtable_levels - 1) * (vm->page_shift - 3) + vm->page_shift; in pgd_index()
31 uint64_t mask = (1UL << (vm->va_bits - shift)) - 1; in pgd_index()
38 unsigned int shift = 2 * (vm->page_shift - 3) + vm->page_shift; in pud_index()
39 uint64_t mask = (1UL << (vm->page_shift - 3)) - 1; in pud_index()
41 TEST_ASSERT(vm->pgtable_levels == 4, in pud_index()
42 "Mode %d does not have 4 page table levels", vm->mode); in pud_index()
49 unsigned int shift = (vm->page_shift - 3) + vm->page_shift; in pmd_index()
50 uint64_t mask = (1UL << (vm->page_shift - 3)) - 1; in pmd_index()
[all …]
/linux/drivers/net/ethernet/mellanox/mlx5/core/
H A Dpci_irq.c1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
21 /* min num of vectors for SFs to be enabled */
52 return mlx5_core_ec_vf_vport_base(dev) + func - 1; in mlx5_core_func_to_vport()
56 * mlx5_get_default_msix_vec_count - Get the default number of MSI-X vectors
72 /* Limit maximum number of MSI-X vectors so the default configuration in mlx5_get_default_msix_vec_count()
74 * the number of vectors in a VF without having to first size-down other in mlx5_get_default_msix_vec_count()
81 * mlx5_set_msix_vec_count - Set dynamically allocated MSI-X on the VF
84 * @msix_vec_count: Number of MSI-X vectors to set
102 return -EOPNOTSUPP; in mlx5_set_msix_vec_count()
108 return -EINVAL; in mlx5_set_msix_vec_count()
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