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Searched refs:int_level (Results 1 – 8 of 8) sorted by relevance

/qemu/hw/net/
H A Dsmc91c111.c63 uint8_t int_level; member
92 VMSTATE_UINT8(int_level, smc91c111_state),
148 s->int_level |= INT_TX_EMPTY; in smc91c111_update()
150 s->int_level |= INT_TX; in smc91c111_update()
151 level = (s->int_level & s->int_mask) != 0; in smc91c111_update()
197 s->int_level |= INT_ALLOC; in smc91c111_tx_alloc()
219 s->int_level |= INT_RCV; in smc91c111_pop_rx_fifo()
221 s->int_level &= ~INT_RCV; in smc91c111_pop_rx_fifo()
375 s->int_level = INT_TX_EMPTY; in smc91c111_reset()
509 s->int_level &= ~INT_ALLOC; in smc91c111_writeb()
[all …]
/qemu/hw/char/
H A Dpl011.c137 flags = s->int_level & s->int_enabled; in pl011_update()
194 s->int_level |= INT_RX; in pl011_fifo_rx_put()
244 s->int_level |= INT_TX; in pl011_write_txdata()
263 s->int_level &= ~INT_RX; in pl011_read_rxdata()
310 r = s->int_level; in pl011_read()
313 r = s->int_level & s->int_enabled; in pl011_read()
395 il = s->int_level & ~(INT_DSR | INT_DCD | INT_CTS | INT_RI); in pl011_loopback_mdmctrl()
402 s->int_level = il; in pl011_loopback_mdmctrl()
472 s->int_level &= ~value; in pl011_write()
604 VMSTATE_UINT32(int_level, PL011State),
[all …]
/qemu/rust/hw/char/pl011/src/
H A Ddevice.rs89 pub int_level: Interrupt, field
203 RIS => u32::from(self.int_level), in read()
204 MIS => u32::from(self.int_level & self.int_enabled), in read()
272 self.int_level &= !Interrupt::from(value); in write()
298 self.int_level &= !Interrupt::RX; in read_data_register()
308 self.int_level |= Interrupt::TX; in write_data_register()
362 let mut il = self.int_level; in loopback_mdmctrl()
378 self.int_level = il; in loopback_mdmctrl()
395 self.int_level = 0.into(); in reset()
454 self.int_level | in fifo_rx_put()
[all...]
H A Ddevice_class.rs58 vmstate_of!(PL011Registers, int_level),
/qemu/hw/timer/
H A Darm_timer.c37 int int_level; member
46 if (s->int_level && (s->control & TIMER_CTRL_IE)) { in arm_timer_update()
66 return s->int_level; in arm_timer_read()
70 return s->int_level; in arm_timer_read()
140 s->int_level = 0; in arm_timer_write()
158 s->int_level = 1; in arm_timer_tick()
169 VMSTATE_INT32(int_level, arm_timer_state),
H A Dsh_timer.c43 int int_level; member
54 int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE); in sh_timer_update()
59 s->old_level = s->int_level; in sh_timer_update()
60 s->int_level = new_level; in sh_timer_update()
73 return s->tcr | (s->int_level ? TIMER_TCR_UNF : 0); in sh_timer_read()
167 s->int_level = 0; in sh_timer_write()
224 s->int_level = s->enabled; in sh_timer_tick()
/qemu/hw/arm/
H A Dintegratorcp.c52 uint32_t int_level; member
75 VMSTATE_UINT32(int_level, IntegratorCMState),
130 return s->int_level & s->irq_enabled; in integratorcm_read()
132 return s->int_level; in integratorcm_read()
136 return s->int_level & 1; in integratorcm_read()
138 return s->int_level & s->fiq_enabled; in integratorcm_read()
140 return s->int_level; in integratorcm_read()
186 if (s->int_level & (s->irq_enabled | s->fiq_enabled)) in integratorcm_update()
237 s->int_level |= (value & 1); in integratorcm_write()
241 s->int_level &= ~(value & 1); in integratorcm_write()
/qemu/include/hw/char/
H A Dpl011.h41 uint32_t int_level; member