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Searched refs:IRQ_S_EXT (Results 1 – 10 of 10) sorted by relevance

/qemu/target/riscv/
H A Dcpu_bits.h745 #define IRQ_S_EXT 9 macro
767 #define MIP_SEIP (1 << IRQ_S_EXT)
780 #define MIE_SEIE (1 << IRQ_S_EXT)
H A Dcpu_helper.c450 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, in riscv_cpu_sirq_pending()
465 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, in riscv_cpu_vsirq_pending()
517 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, in riscv_cpu_local_irq_pending()
534 virq = riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, in riscv_cpu_local_irq_pending()
H A Dcsr.c2675 (priv == PRV_M) ? IRQ_M_EXT : IRQ_S_EXT); in rmw_xireg_aia()
4396 siid[scount] = IRQ_S_EXT; in read_vstopi()
4415 if (hviid == IRQ_S_EXT && hviprio) { in read_vstopi()
4416 siid[scount] = IRQ_S_EXT; in read_vstopi()
4423 if (hviid != IRQ_S_EXT) { in read_vstopi()
4430 if (irq != IRQ_S_EXT && 0 < irq && irq <= 63) { in read_vstopi()
H A Dcpu.c734 env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio; in riscv_cpu_reset_hold()
1037 case IRQ_S_EXT: in riscv_cpu_set_irq()
/qemu/hw/intc/
H A Driscv_imsic.c475 (mmode) ? IRQ_M_EXT : IRQ_S_EXT)); in type_init()
H A Dsifive_plic.c516 qdev_get_gpio_in(DEVICE(cpu), IRQ_S_EXT)); in type_init()
H A Driscv_aplic.c1082 (mmode) ? IRQ_M_EXT : IRQ_S_EXT)); in riscv_aplic_create()
/qemu/hw/riscv/
H A Dvirt.c476 plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); in create_fdt_socket_plic()
489 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); in create_fdt_socket_plic()
544 imsic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT); in create_fdt_one_imsic()
639 aplic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT); in create_fdt_one_aplic()
H A Dsifive_u.c262 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT); in create_fdt()
/qemu/target/riscv/kvm/
H A Dkvm-cpu.c1736 if (irq != IRQ_S_EXT) { in kvm_riscv_set_irq()