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Searched refs:apb_base (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/pci/controller/dwc/
H A Dpcie-keembay.c60 void __iomem *apb_base; member
96 val = readl(pcie->apb_base + PCIE_REGS_PCIE_APP_CNTRL); in keembay_pcie_ltssm_set()
101 writel(val, pcie->apb_base + PCIE_REGS_PCIE_APP_CNTRL); in keembay_pcie_ltssm_set()
109 val = readl(pcie->apb_base + PCIE_REGS_PCIE_SII_PM_STATE); in keembay_pcie_link_up()
125 ret = readl_poll_timeout(pcie->apb_base + PCIE_REGS_PCIE_PHY_STAT, in keembay_pcie_start_link()
216 writel(val, pcie->apb_base + PCIE_REGS_LJPLL_CNTRL_2); in keembay_pcie_pll_init()
220 writel(val, pcie->apb_base + PCIE_REGS_LJPLL_CNTRL_3); in keembay_pcie_pll_init()
223 writel(val, pcie->apb_base + PCIE_REGS_LJPLL_CNTRL_0); in keembay_pcie_pll_init()
225 ret = readl_poll_timeout(pcie->apb_base + PCIE_REGS_LJPLL_STA, in keembay_pcie_pll_init()
253 val = readl(pcie->apb_base in keembay_pcie_msi_irq_handler()
[all...]
H A Dpcie-dw-rockchip.c73 void __iomem *apb_base; member
91 return readl_relaxed(rockchip->apb_base + reg); in rockchip_pcie_readl_apb()
97 writel_relaxed(val, rockchip->apb_base + reg); in rockchip_pcie_writel_apb()
395 rockchip->apb_base = devm_platform_ioremap_resource_byname(pdev, "apb"); in rockchip_pcie_resource_get()
396 if (IS_ERR(rockchip->apb_base)) in rockchip_pcie_resource_get()
397 return dev_err_probe(&pdev->dev, PTR_ERR(rockchip->apb_base), in rockchip_pcie_resource_get()
H A Dpcie-kirin.c453 void __iomem *apb_base; in kirin_pcie_get_resource() local
456 apb_base = devm_platform_ioremap_resource_byname(pdev, "apb"); in kirin_pcie_get_resource()
457 if (IS_ERR(apb_base)) in kirin_pcie_get_resource()
458 return PTR_ERR(apb_base); in kirin_pcie_get_resource()
460 kirin_pcie->apb = devm_regmap_init_mmio(dev, apb_base, in kirin_pcie_get_resource()
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-thead.c50 void __iomem *apb_base; member
75 writel(phyif, dwmac->apb_base + GMAC_INTF_CTRL); in thead_dwmac_set_phy_if()
100 writel(txclk_dir, dwmac->apb_base + GMAC_TXCLK_OEN); in thead_dwmac_set_txclk_dir()
126 writel(0, dwmac->apb_base + GMAC_PLLCLK_DIV); in thead_set_clk_tx_rate()
142 writel(reg, dwmac->apb_base + GMAC_PLLCLK_DIV); in thead_set_clk_tx_rate()
167 writel(GMAC_GTXCLK_SEL_PLL, dwmac->apb_base + GMAC_GTXCLK_SEL); in thead_dwmac_enable_clk()
178 writel(reg, dwmac->apb_base + GMAC_CLK_EN); in thead_dwmac_enable_clk()
196 reg = readl(dwmac->apb_base + GMAC_RXCLK_DELAY_CTRL); in thead_dwmac_init()
199 writel(reg, dwmac->apb_base + GMAC_RXCLK_DELAY_CTRL); in thead_dwmac_init()
201 reg = readl(dwmac->apb_base + GMAC_TXCLK_DELAY_CTRL); in thead_dwmac_init()
[all …]
/linux/drivers/pci/controller/
H A Dpcie-rockchip.c50 rockchip->apb_base = in rockchip_pcie_parse_dt()
52 if (IS_ERR(rockchip->apb_base)) in rockchip_pcie_parse_dt()
53 return PTR_ERR(rockchip->apb_base); in rockchip_pcie_parse_dt()
H A Dpcie-rockchip.h308 void __iomem *apb_base; /* DT apb-base */ member
334 return readl(rockchip->apb_base + reg); in rockchip_pcie_read()
340 writel(val, rockchip->apb_base + reg); in rockchip_pcie_write()
H A Dpcie-rockchip-host.c97 addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + where; in rockchip_pcie_rd_own_conf()
124 addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + offset; in rockchip_pcie_wr_own_conf()
323 err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1, in rockchip_pcie_host_init_port()
344 err = readl_poll_timeout(rockchip->apb_base + PCIE_CORE_CTRL, in rockchip_pcie_host_init_port()
852 err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_DEBUG_OUT_0, in rockchip_pcie_wait_l2()
H A Dpcie-rockchip-ep.c543 ret = readl_poll_timeout(rockchip->apb_base + PCIE_CORE_CTRL, in rockchip_pcie_ep_link_training()
550 ret = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1, in rockchip_pcie_ep_link_training()
564 readl_poll_timeout(rockchip->apb_base + PCIE_CORE_CTRL, in rockchip_pcie_ep_link_training()