50 	void __iomem *apb_base;  member
75 	writel(phyif, dwmac->apb_base + GMAC_INTF_CTRL);  in thead_dwmac_set_phy_if()
100 	writel(txclk_dir, dwmac->apb_base + GMAC_TXCLK_OEN);  in thead_dwmac_set_txclk_dir()
126 		writel(0, dwmac->apb_base + GMAC_PLLCLK_DIV);  in thead_set_clk_tx_rate()
142 		writel(reg, dwmac->apb_base + GMAC_PLLCLK_DIV);  in thead_set_clk_tx_rate()
167 		writel(GMAC_GTXCLK_SEL_PLL, dwmac->apb_base + GMAC_GTXCLK_SEL);  in thead_dwmac_enable_clk()
178 	writel(reg, dwmac->apb_base + GMAC_CLK_EN);  in thead_dwmac_enable_clk()
196 	reg = readl(dwmac->apb_base + GMAC_RXCLK_DELAY_CTRL);  in thead_dwmac_init()
199 	writel(reg, dwmac->apb_base + GMAC_RXCLK_DELAY_CTRL);  in thead_dwmac_init()
201 	reg = readl(dwmac->apb_base + GMAC_TXCLK_DELAY_CTRL);  in thead_dwmac_init()
204 	writel(reg, dwmac->apb_base + GMAC_TXCLK_DELAY_CTRL);  in thead_dwmac_init()
252 	dwmac->apb_base = apb;  in thead_dwmac_probe()