1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Rockchip AXI PCIe host controller driver 4 * 5 * Copyright (c) 2016 Rockchip, Inc. 6 * 7 * Author: Shawn Lin <shawn.lin@rock-chips.com> 8 * Wenrui Li <wenrui.li@rock-chips.com> 9 * 10 * Bits taken from Synopsys DesignWare Host controller driver and 11 * ARM PCI Host generic driver. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/delay.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/iopoll.h> 18 #include <linux/of.h> 19 #include <linux/of_pci.h> 20 #include <linux/phy/phy.h> 21 #include <linux/platform_device.h> 22 #include <linux/reset.h> 23 24 #include "../pci.h" 25 #include "pcie-rockchip.h" 26 27 int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) 28 { 29 struct device *dev = rockchip->dev; 30 struct platform_device *pdev = to_platform_device(dev); 31 struct device_node *node = dev->of_node; 32 struct resource *regs; 33 int err, i; 34 35 if (rockchip->is_rc) { 36 regs = platform_get_resource_byname(pdev, 37 IORESOURCE_MEM, 38 "axi-base"); 39 rockchip->reg_base = devm_pci_remap_cfg_resource(dev, regs); 40 if (IS_ERR(rockchip->reg_base)) 41 return PTR_ERR(rockchip->reg_base); 42 } else { 43 rockchip->mem_res = 44 platform_get_resource_byname(pdev, IORESOURCE_MEM, 45 "mem-base"); 46 if (!rockchip->mem_res) 47 return -EINVAL; 48 } 49 50 rockchip->apb_base = 51 devm_platform_ioremap_resource_byname(pdev, "apb-base"); 52 if (IS_ERR(rockchip->apb_base)) 53 return PTR_ERR(rockchip->apb_base); 54 55 err = rockchip_pcie_get_phys(rockchip); 56 if (err) 57 return err; 58 59 rockchip->lanes = 1; 60 err = of_property_read_u32(node, "num-lanes", &rockchip->lanes); 61 if (!err && (rockchip->lanes == 0 || 62 rockchip->lanes == 3 || 63 rockchip->lanes > 4)) { 64 dev_warn(dev, "invalid num-lanes, default to use one lane\n"); 65 rockchip->lanes = 1; 66 } 67 68 rockchip->link_gen = of_pci_get_max_link_speed(node); 69 if (rockchip->link_gen < 0 || rockchip->link_gen > 2) 70 rockchip->link_gen = 2; 71 72 for (i = 0; i < ROCKCHIP_NUM_PM_RSTS; i++) 73 rockchip->pm_rsts[i].id = rockchip_pci_pm_rsts[i]; 74 75 err = devm_reset_control_bulk_get_exclusive(dev, 76 ROCKCHIP_NUM_PM_RSTS, 77 rockchip->pm_rsts); 78 if (err) 79 return dev_err_probe(dev, err, "Cannot get the PM reset\n"); 80 81 for (i = 0; i < ROCKCHIP_NUM_CORE_RSTS; i++) 82 rockchip->core_rsts[i].id = rockchip_pci_core_rsts[i]; 83 84 err = devm_reset_control_bulk_get_exclusive(dev, 85 ROCKCHIP_NUM_CORE_RSTS, 86 rockchip->core_rsts); 87 if (err) 88 return dev_err_probe(dev, err, "Cannot get the Core resets\n"); 89 90 if (rockchip->is_rc) 91 rockchip->perst_gpio = devm_gpiod_get_optional(dev, "ep", 92 GPIOD_OUT_LOW); 93 else 94 rockchip->perst_gpio = devm_gpiod_get_optional(dev, "reset", 95 GPIOD_IN); 96 if (IS_ERR(rockchip->perst_gpio)) 97 return dev_err_probe(dev, PTR_ERR(rockchip->perst_gpio), 98 "failed to get PERST# GPIO\n"); 99 100 rockchip->num_clks = devm_clk_bulk_get_all(dev, &rockchip->clks); 101 if (rockchip->num_clks < 0) 102 return dev_err_probe(dev, rockchip->num_clks, 103 "failed to get clocks\n"); 104 105 return 0; 106 } 107 EXPORT_SYMBOL_GPL(rockchip_pcie_parse_dt); 108 109 #define rockchip_pcie_read_addr(addr) rockchip_pcie_read(rockchip, addr) 110 /* 100 ms max wait time for PHY PLLs to lock */ 111 #define RK_PHY_PLL_LOCK_TIMEOUT_US 100000 112 /* Sleep should be less than 20ms */ 113 #define RK_PHY_PLL_LOCK_SLEEP_US 1000 114 115 int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) 116 { 117 struct device *dev = rockchip->dev; 118 int err, i; 119 u32 regs; 120 121 err = reset_control_bulk_assert(ROCKCHIP_NUM_PM_RSTS, 122 rockchip->pm_rsts); 123 if (err) 124 return dev_err_probe(dev, err, "Couldn't assert PM resets\n"); 125 126 for (i = 0; i < MAX_LANE_NUM; i++) { 127 err = phy_init(rockchip->phys[i]); 128 if (err) { 129 dev_err(dev, "init phy%d err %d\n", i, err); 130 goto err_exit_phy; 131 } 132 } 133 134 err = reset_control_bulk_assert(ROCKCHIP_NUM_CORE_RSTS, 135 rockchip->core_rsts); 136 if (err) { 137 dev_err_probe(dev, err, "Couldn't assert Core resets\n"); 138 goto err_exit_phy; 139 } 140 141 udelay(10); 142 143 err = reset_control_bulk_deassert(ROCKCHIP_NUM_PM_RSTS, 144 rockchip->pm_rsts); 145 if (err) { 146 dev_err(dev, "Couldn't deassert PM resets %d\n", err); 147 goto err_exit_phy; 148 } 149 150 if (rockchip->link_gen == 2) 151 rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_2, 152 PCIE_CLIENT_CONFIG); 153 else 154 rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_1, 155 PCIE_CLIENT_CONFIG); 156 157 regs = PCIE_CLIENT_ARI_ENABLE | 158 PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes); 159 160 if (rockchip->is_rc) 161 regs |= PCIE_CLIENT_LINK_TRAIN_ENABLE | 162 PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC; 163 else 164 regs |= PCIE_CLIENT_CONF_DISABLE | PCIE_CLIENT_MODE_EP; 165 166 rockchip_pcie_write(rockchip, regs, PCIE_CLIENT_CONFIG); 167 168 for (i = 0; i < MAX_LANE_NUM; i++) { 169 err = phy_power_on(rockchip->phys[i]); 170 if (err) { 171 dev_err(dev, "power on phy%d err %d\n", i, err); 172 goto err_power_off_phy; 173 } 174 } 175 176 err = readx_poll_timeout(rockchip_pcie_read_addr, 177 PCIE_CLIENT_SIDE_BAND_STATUS, 178 regs, !(regs & PCIE_CLIENT_PHY_ST), 179 RK_PHY_PLL_LOCK_SLEEP_US, 180 RK_PHY_PLL_LOCK_TIMEOUT_US); 181 if (err) { 182 dev_err(dev, "PHY PLLs could not lock, %d\n", err); 183 goto err_power_off_phy; 184 } 185 186 err = reset_control_bulk_deassert(ROCKCHIP_NUM_CORE_RSTS, 187 rockchip->core_rsts); 188 if (err) { 189 dev_err(dev, "Couldn't deassert Core reset %d\n", err); 190 goto err_power_off_phy; 191 } 192 193 return 0; 194 err_power_off_phy: 195 while (i--) 196 phy_power_off(rockchip->phys[i]); 197 i = MAX_LANE_NUM; 198 err_exit_phy: 199 while (i--) 200 phy_exit(rockchip->phys[i]); 201 return err; 202 } 203 EXPORT_SYMBOL_GPL(rockchip_pcie_init_port); 204 205 int rockchip_pcie_get_phys(struct rockchip_pcie *rockchip) 206 { 207 struct device *dev = rockchip->dev; 208 struct phy *phy; 209 char *name; 210 u32 i; 211 212 phy = devm_phy_get(dev, "pcie-phy"); 213 if (!IS_ERR(phy)) { 214 rockchip->legacy_phy = true; 215 rockchip->phys[0] = phy; 216 dev_warn(dev, "legacy phy model is deprecated!\n"); 217 return 0; 218 } 219 220 if (PTR_ERR(phy) == -EPROBE_DEFER) 221 return PTR_ERR(phy); 222 223 dev_dbg(dev, "missing legacy phy; search for per-lane PHY\n"); 224 225 for (i = 0; i < MAX_LANE_NUM; i++) { 226 name = kasprintf(GFP_KERNEL, "pcie-phy-%u", i); 227 if (!name) 228 return -ENOMEM; 229 230 phy = devm_of_phy_get(dev, dev->of_node, name); 231 kfree(name); 232 233 if (IS_ERR(phy)) { 234 if (PTR_ERR(phy) != -EPROBE_DEFER) 235 dev_err(dev, "missing phy for lane %d: %ld\n", 236 i, PTR_ERR(phy)); 237 return PTR_ERR(phy); 238 } 239 240 rockchip->phys[i] = phy; 241 } 242 243 return 0; 244 } 245 EXPORT_SYMBOL_GPL(rockchip_pcie_get_phys); 246 247 void rockchip_pcie_deinit_phys(struct rockchip_pcie *rockchip) 248 { 249 int i; 250 251 for (i = 0; i < MAX_LANE_NUM; i++) { 252 /* inactive lanes are already powered off */ 253 if (rockchip->lanes_map & BIT(i)) 254 phy_power_off(rockchip->phys[i]); 255 phy_exit(rockchip->phys[i]); 256 } 257 } 258 EXPORT_SYMBOL_GPL(rockchip_pcie_deinit_phys); 259 260 int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip) 261 { 262 struct device *dev = rockchip->dev; 263 int err; 264 265 err = clk_bulk_prepare_enable(rockchip->num_clks, rockchip->clks); 266 if (err) 267 return dev_err_probe(dev, err, "failed to enable clocks\n"); 268 269 return 0; 270 } 271 EXPORT_SYMBOL_GPL(rockchip_pcie_enable_clocks); 272 273 void rockchip_pcie_disable_clocks(struct rockchip_pcie *rockchip) 274 { 275 276 clk_bulk_disable_unprepare(rockchip->num_clks, rockchip->clks); 277 } 278 EXPORT_SYMBOL_GPL(rockchip_pcie_disable_clocks); 279 280 void rockchip_pcie_cfg_configuration_accesses( 281 struct rockchip_pcie *rockchip, u32 type) 282 { 283 u32 ob_desc_0; 284 285 /* Configuration Accesses for region 0 */ 286 rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF); 287 288 rockchip_pcie_write(rockchip, 289 (RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS), 290 PCIE_CORE_OB_REGION_ADDR0); 291 rockchip_pcie_write(rockchip, RC_REGION_0_ADDR_TRANS_H, 292 PCIE_CORE_OB_REGION_ADDR1); 293 ob_desc_0 = rockchip_pcie_read(rockchip, PCIE_CORE_OB_REGION_DESC0); 294 ob_desc_0 &= ~(RC_REGION_0_TYPE_MASK); 295 ob_desc_0 |= (type | (0x1 << 23)); 296 rockchip_pcie_write(rockchip, ob_desc_0, PCIE_CORE_OB_REGION_DESC0); 297 rockchip_pcie_write(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1); 298 } 299 EXPORT_SYMBOL_GPL(rockchip_pcie_cfg_configuration_accesses); 300