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Searched refs:wptr (Results 1 – 25 of 123) sorted by relevance

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/linux/drivers/media/usb/pvrusb2/
H A Dpvrusb2-debugifc.c51 const char *wptr; in debugifc_isolate_word() local
56 wptr = NULL; in debugifc_isolate_word()
64 wptr = buf; in debugifc_isolate_word()
69 *wstrPtr = wptr; in debugifc_isolate_word()
178 const char *wptr; in pvr2_debugifc_do1cmd() local
182 scnt = debugifc_isolate_word(buf,count,&wptr,&wlen); in pvr2_debugifc_do1cmd()
185 if (!wptr) return 0; in pvr2_debugifc_do1cmd()
187 pvr2_trace(PVR2_TRACE_DEBUGIFC,"debugifc cmd: \"%.*s\"",wlen,wptr); in pvr2_debugifc_do1cmd()
188 if (debugifc_match_keyword(wptr,wlen,"reset")) { in pvr2_debugifc_do1cmd()
189 scnt = debugifc_isolate_word(buf,count,&wptr,&wlen); in pvr2_debugifc_do1cmd()
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/linux/drivers/media/platform/amphion/
H A Dvpu_rpc.c39 ptr1 = desc->wptr; in vpu_rpc_check_buffer_space()
43 ptr2 = desc->wptr; in vpu_rpc_check_buffer_space()
61 u32 wptr; in vpu_rpc_send_cmd_buf() local
70 wptr = desc->wptr; in vpu_rpc_send_cmd_buf()
71 data = (u32 *)(shared->cmd_mem_vir + desc->wptr - desc->start); in vpu_rpc_send_cmd_buf()
76 wptr += 4; in vpu_rpc_send_cmd_buf()
78 if (wptr >= desc->end) { in vpu_rpc_send_cmd_buf()
79 wptr = desc->start; in vpu_rpc_send_cmd_buf()
85 wptr += 4; in vpu_rpc_send_cmd_buf()
87 if (wptr >= desc->end) { in vpu_rpc_send_cmd_buf()
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H A Dvpu_malone.c198 u32 wptr; member
324 u32 wptr; member
383 iface->cmd_buffer_desc.buffer.wptr = phy_addr; in vpu_malone_init_rpc()
391 iface->msg_buffer_desc.buffer.wptr = in vpu_malone_init_rpc()
435 iface->eng_access_buff_desc[i].buffer.wptr = in vpu_malone_init_rpc()
458 iface->debug_buffer_desc.buffer.wptr = in vpu_malone_set_log_buf()
510 writel(buf->phys, &str_buf->wptr); in vpu_malone_config_stream_buffer()
527 desc->wptr = readl(&str_buf->wptr); in vpu_malone_get_stream_buffer_desc()
536 static void vpu_malone_update_wptr(struct vpu_malone_str_buffer __iomem *str_buf, u32 wptr) in vpu_malone_update_wptr() argument
540 writel(wptr, &str_buf->wptr); in vpu_malone_update_wptr()
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H A Dvpu_helpers.c271 u32 *wptr, u32 size, void *src) in vpu_helper_copy_to_stream_buffer() argument
278 if (!stream_buffer || !wptr || !src) in vpu_helper_copy_to_stream_buffer()
284 offset = *wptr; in vpu_helper_copy_to_stream_buffer()
298 *wptr = vpu_helper_step_walk(stream_buffer, offset, size); in vpu_helper_copy_to_stream_buffer()
304 u32 *wptr, u8 val, u32 size) in vpu_helper_memset_stream_buffer() argument
311 if (!stream_buffer || !wptr) in vpu_helper_memset_stream_buffer()
317 offset = *wptr; in vpu_helper_memset_stream_buffer()
335 *wptr = offset; in vpu_helper_memset_stream_buffer()
347 if (desc.rptr > desc.wptr) in vpu_helper_get_free_space()
348 return desc.rptr - desc.wptr; in vpu_helper_get_free_space()
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_ih.c153 uint32_t wptr = le32_to_cpu(*ih->wptr_cpu) >> 2; in amdgpu_ih_ring_write() local
157 ih->ring[wptr++] = cpu_to_le32(iv[i]); in amdgpu_ih_ring_write()
159 wptr <<= 2; in amdgpu_ih_ring_write()
160 wptr &= ih->ptr_mask; in amdgpu_ih_ring_write()
163 if (wptr != READ_ONCE(ih->rptr)) { in amdgpu_ih_ring_write()
165 WRITE_ONCE(*ih->wptr_cpu, cpu_to_le32(wptr)); in amdgpu_ih_ring_write()
168 wptr, ih->rptr); in amdgpu_ih_ring_write()
212 u32 wptr; in amdgpu_ih_process() local
217 wptr = amdgpu_ih_get_wptr(adev, ih); in amdgpu_ih_process()
221 dev_dbg(adev->dev, "%s: rptr %d, wptr %d\n", __func__, ih->rptr, wptr); in amdgpu_ih_process()
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H A Dcz_ih.c196 u32 wptr, tmp; in cz_ih_get_wptr() local
198 wptr = le32_to_cpu(*ih->wptr_cpu); in cz_ih_get_wptr()
203 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in cz_ih_get_wptr()
207 wptr = RREG32(mmIH_RB_WPTR); in cz_ih_get_wptr()
209 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in cz_ih_get_wptr()
212 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in cz_ih_get_wptr()
219 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in cz_ih_get_wptr()
220 ih->rptr = (wptr + 16) & ih->ptr_mask; in cz_ih_get_wptr()
232 return (wptr & ih->ptr_mask); in cz_ih_get_wptr()
H A Diceland_ih.c196 u32 wptr, tmp; in iceland_ih_get_wptr() local
198 wptr = le32_to_cpu(*ih->wptr_cpu); in iceland_ih_get_wptr()
203 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in iceland_ih_get_wptr()
207 wptr = RREG32(mmIH_RB_WPTR); in iceland_ih_get_wptr()
209 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in iceland_ih_get_wptr()
212 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in iceland_ih_get_wptr()
218 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in iceland_ih_get_wptr()
219 ih->rptr = (wptr + 16) & ih->ptr_mask; in iceland_ih_get_wptr()
231 return (wptr & ih->ptr_mask); in iceland_ih_get_wptr()
H A Dtonga_ih.c198 u32 wptr, tmp; in tonga_ih_get_wptr() local
200 wptr = le32_to_cpu(*ih->wptr_cpu); in tonga_ih_get_wptr()
205 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in tonga_ih_get_wptr()
209 wptr = RREG32(mmIH_RB_WPTR); in tonga_ih_get_wptr()
211 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in tonga_ih_get_wptr()
214 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in tonga_ih_get_wptr()
222 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in tonga_ih_get_wptr()
223 ih->rptr = (wptr + 16) & ih->ptr_mask; in tonga_ih_get_wptr()
235 return (wptr & ih->ptr_mask); in tonga_ih_get_wptr()
H A Dsi_ih.c114 u32 wptr, tmp; in si_ih_get_wptr() local
116 wptr = le32_to_cpu(*ih->wptr_cpu); in si_ih_get_wptr()
121 if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) { in si_ih_get_wptr()
122 wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK; in si_ih_get_wptr()
124 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in si_ih_get_wptr()
125 ih->rptr = (wptr + 16) & ih->ptr_mask; in si_ih_get_wptr()
138 return (wptr & ih->ptr_mask); in si_ih_get_wptr()
H A Dcik_ih.c194 u32 wptr, tmp; in cik_ih_get_wptr() local
196 wptr = le32_to_cpu(*ih->wptr_cpu); in cik_ih_get_wptr()
201 if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) { in cik_ih_get_wptr()
202 wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK; in cik_ih_get_wptr()
208 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in cik_ih_get_wptr()
209 ih->rptr = (wptr + 16) & ih->ptr_mask; in cik_ih_get_wptr()
222 return (wptr & ih->ptr_mask); in cik_ih_get_wptr()
H A Damdgpu_ring_mux.c213 void amdgpu_ring_mux_set_wptr(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring, u64 wptr) in amdgpu_ring_mux_set_wptr() argument
239 e->sw_wptr = wptr; in amdgpu_ring_mux_set_wptr()
240 e->start_ptr_in_hw_ring = mux->real_ring->wptr; in amdgpu_ring_mux_set_wptr()
243 if (ring->hw_prio > AMDGPU_RING_PRIO_DEFAULT || mux->wptr_resubmit < wptr) { in amdgpu_ring_mux_set_wptr()
244 amdgpu_ring_mux_copy_pkt_from_sw_ring(mux, ring, e->sw_cptr, wptr); in amdgpu_ring_mux_set_wptr()
245 e->end_ptr_in_hw_ring = mux->real_ring->wptr; in amdgpu_ring_mux_set_wptr()
248 e->end_ptr_in_hw_ring = mux->real_ring->wptr; in amdgpu_ring_mux_set_wptr()
340 amdgpu_ring_mux_set_wptr(mux, ring, ring->wptr); in amdgpu_sw_ring_set_wptr_gfx()
428 offset = ring->wptr & ring->buf_mask; in amdgpu_sw_ring_ib_mark_offset()
454 chunk->start = ring->wptr; in amdgpu_ring_mux_start_ib()
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H A Dih_v6_0.c438 u32 wptr, tmp; in ih_v6_0_get_wptr() local
441 wptr = le32_to_cpu(*ih->wptr_cpu); in ih_v6_0_get_wptr()
444 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in ih_v6_0_get_wptr()
447 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in ih_v6_0_get_wptr()
448 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in ih_v6_0_get_wptr()
451 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in ih_v6_0_get_wptr()
459 tmp = (wptr + 32) & ih->ptr_mask; in ih_v6_0_get_wptr()
462 wptr, ih->rptr, tmp); in ih_v6_0_get_wptr()
475 return (wptr & ih->ptr_mask); in ih_v6_0_get_wptr()
543 uint32_t wptr = cpu_to_le32(entry->src_data[0]); in ih_v6_0_self_irq() local
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H A Dih_v6_1.c409 u32 wptr, tmp; in ih_v6_1_get_wptr() local
412 wptr = le32_to_cpu(*ih->wptr_cpu); in ih_v6_1_get_wptr()
415 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in ih_v6_1_get_wptr()
418 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in ih_v6_1_get_wptr()
419 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in ih_v6_1_get_wptr()
421 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in ih_v6_1_get_wptr()
427 tmp = (wptr + 32) & ih->ptr_mask; in ih_v6_1_get_wptr()
430 wptr, ih->rptr, tmp); in ih_v6_1_get_wptr()
444 return (wptr & ih->ptr_mask); in ih_v6_1_get_wptr()
512 uint32_t wptr = cpu_to_le32(entry->src_data[0]); in ih_v6_1_self_irq() local
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H A Dsdma_v4_4_2.c241 u64 wptr; in sdma_v4_4_2_ring_get_wptr() local
245 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); in sdma_v4_4_2_ring_get_wptr()
246 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); in sdma_v4_4_2_ring_get_wptr()
248 wptr = RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI); in sdma_v4_4_2_ring_get_wptr()
249 wptr = wptr << 32; in sdma_v4_4_2_ring_get_wptr()
250 wptr |= RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR); in sdma_v4_4_2_ring_get_wptr()
252 ring->me, wptr); in sdma_v4_4_2_ring_get_wptr()
255 return wptr >> 2; in sdma_v4_4_2_ring_get_wptr()
278 lower_32_bits(ring->wptr << 2), in sdma_v4_4_2_ring_set_wptr()
279 upper_32_bits(ring->wptr << 2)); in sdma_v4_4_2_ring_set_wptr()
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H A Dsdma_v5_2.c153 ret = ring->wptr & ring->buf_mask; in sdma_v5_2_ring_init_cond_exec()
188 u64 wptr; in sdma_v5_2_ring_get_wptr() local
192 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); in sdma_v5_2_ring_get_wptr()
193 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); in sdma_v5_2_ring_get_wptr()
195 wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); in sdma_v5_2_ring_get_wptr()
196 wptr = wptr << 32; in sdma_v5_2_ring_get_wptr()
197 wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)); in sdma_v5_2_ring_get_wptr()
198 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr); in sdma_v5_2_ring_get_wptr()
201 return wptr >> 2; in sdma_v5_2_ring_get_wptr()
222 lower_32_bits(ring->wptr << 2), in sdma_v5_2_ring_set_wptr()
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H A Dvega10_ih.c338 u32 wptr, tmp; in vega10_ih_get_wptr() local
347 wptr = le32_to_cpu(*ih->wptr_cpu); in vega10_ih_get_wptr()
349 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in vega10_ih_get_wptr()
356 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in vega10_ih_get_wptr()
357 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in vega10_ih_get_wptr()
360 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in vega10_ih_get_wptr()
366 tmp = (wptr + 32) & ih->ptr_mask; in vega10_ih_get_wptr()
368 amdgpu_ih_ring_name(adev, ih), wptr, ih->rptr, tmp); in vega10_ih_get_wptr()
382 return (wptr & ih->ptr_mask); in vega10_ih_get_wptr()
H A Dsdma_v4_0.c674 u64 wptr; in sdma_v4_0_ring_get_wptr() local
678 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); in sdma_v4_0_ring_get_wptr()
679 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); in sdma_v4_0_ring_get_wptr()
681 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI); in sdma_v4_0_ring_get_wptr()
682 wptr = wptr << 32; in sdma_v4_0_ring_get_wptr()
683 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR); in sdma_v4_0_ring_get_wptr()
685 ring->me, wptr); in sdma_v4_0_ring_get_wptr()
688 return wptr >> 2; in sdma_v4_0_ring_get_wptr()
711 lower_32_bits(ring->wptr << 2), in sdma_v4_0_ring_set_wptr()
712 upper_32_bits(ring->wptr << 2)); in sdma_v4_0_ring_set_wptr()
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/linux/drivers/net/ppp/
H A Dbsd_comp.c579 unsigned char *wptr; in bsd_compress() local
585 if (wptr) \ in bsd_compress()
587 *wptr++ = (unsigned char) (v); \ in bsd_compress()
590 wptr = NULL; \ in bsd_compress()
629 wptr = obuf; in bsd_compress()
638 if (wptr) in bsd_compress()
640 *wptr++ = PPP_ADDRESS(rptr); in bsd_compress()
641 *wptr++ = PPP_CONTROL(rptr); in bsd_compress()
642 *wptr++ = 0; in bsd_compress()
643 *wptr++ = PPP_COMP; in bsd_compress()
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H A Dppp_deflate.c189 unsigned char *wptr; in z_compress() local
203 wptr = obuf; in z_compress()
208 wptr[0] = PPP_ADDRESS(rptr); in z_compress()
209 wptr[1] = PPP_CONTROL(rptr); in z_compress()
210 put_unaligned_be16(PPP_COMP, wptr + 2); in z_compress()
211 wptr += PPP_HDRLEN; in z_compress()
212 put_unaligned_be16(state->seqno, wptr); in z_compress()
213 wptr += DEFLATE_OVHD; in z_compress()
215 state->strm.next_out = wptr; in z_compress()
/linux/drivers/net/ethernet/tehuti/
H A Dtehuti.c171 f->wptr = 0; in bdx_fifo_init()
1101 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr); in bdx_rx_alloc_skbs()
1109 f->m.wptr += sizeof(struct rxf_desc); in bdx_rx_alloc_skbs()
1110 delta = f->m.wptr - f->m.memsz; in bdx_rx_alloc_skbs()
1112 f->m.wptr = delta; in bdx_rx_alloc_skbs()
1121 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR); in bdx_rx_alloc_skbs()
1156 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr); in bdx_recycle_skb()
1164 f->m.wptr += sizeof(struct rxf_desc); in bdx_recycle_skb()
1165 delta = f->m.wptr - f->m.memsz; in bdx_recycle_skb()
1167 f->m.wptr = delta; in bdx_recycle_skb()
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H A Dtn40.c54 f->wptr = 0; in tn40_fifo_alloc()
212 rxfd = (struct tn40_rxf_desc *)(f->m.va + f->m.wptr); in tn40_set_rx_desc()
218 f->m.wptr += sizeof(struct tn40_rxf_desc); in tn40_set_rx_desc()
219 delta = f->m.wptr - f->m.memsz; in tn40_set_rx_desc()
221 f->m.wptr = delta; in tn40_set_rx_desc()
261 f->m.wptr & TN40_TXF_WPTR_WR_PTR); in tn40_rx_alloc_buffers()
263 f->m.reg_wptr, f->m.wptr & TN40_TXF_WPTR_WR_PTR); in tn40_rx_alloc_buffers()
281 tn40_write_reg(priv, f->m.reg_wptr, f->m.wptr & TN40_TXF_WPTR_WR_PTR); in tn40_recycle_rx_buffer()
296 f->m.wptr = tn40_read_reg(priv, f->m.reg_wptr) & TN40_TXF_WPTR_WR_PTR; in tn40_rx_receive()
297 size = f->m.wptr - f->m.rptr; in tn40_rx_receive()
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/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_kernel_queue.c206 uint32_t wptr, rptr; in kq_acquire_packet_buffer() local
216 wptr = kq->pending_wptr; in kq_acquire_packet_buffer()
222 pr_debug("wptr: %d\n", wptr); in kq_acquire_packet_buffer()
225 available_size = (rptr + queue_size_dwords - 1 - wptr) % in kq_acquire_packet_buffer()
236 if (wptr + packet_size_in_dwords >= queue_size_dwords) { in kq_acquire_packet_buffer()
244 while (wptr > 0) { in kq_acquire_packet_buffer()
245 queue_address[wptr] = kq->nop_packet; in kq_acquire_packet_buffer()
246 wptr = (wptr + 1) % queue_size_dwords; in kq_acquire_packet_buffer()
251 *buffer_ptr = &queue_address[wptr]; in kq_acquire_packet_buffer()
252 kq->pending_wptr = wptr + packet_size_in_dwords; in kq_acquire_packet_buffer()
/linux/drivers/crypto/ccp/
H A Dtee-dev.c128 tee->rb_mgr.wptr = 0; in tee_init_ring()
257 (tee->rb_mgr.ring_start + tee->rb_mgr.wptr); in tee_submit_cmd()
264 if (!(tee->rb_mgr.wptr + sizeof(struct tee_ring_cmd) == rptr || in tee_submit_cmd()
269 rptr, tee->rb_mgr.wptr); in tee_submit_cmd()
279 (tee->rb_mgr.wptr + sizeof(struct tee_ring_cmd) == rptr || in tee_submit_cmd()
282 rptr, tee->rb_mgr.wptr, cmd->flag); in tee_submit_cmd()
305 tee->rb_mgr.wptr += sizeof(struct tee_ring_cmd); in tee_submit_cmd()
306 if (tee->rb_mgr.wptr >= tee->rb_mgr.ring_size) in tee_submit_cmd()
307 tee->rb_mgr.wptr = 0; in tee_submit_cmd()
310 iowrite32(tee->rb_mgr.wptr, tee->io_regs + tee->vdata->ring_wptr_reg); in tee_submit_cmd()
/linux/drivers/gpu/drm/radeon/
H A Dradeon_ring.c89 ring->ring_free_dw -= ring->wptr; in radeon_ring_free_size()
130 ring->wptr_old = ring->wptr; in radeon_ring_alloc()
178 while (ring->wptr & ring->align_mask) { in radeon_ring_commit()
216 ring->wptr = ring->wptr_old; in radeon_ring_undo()
316 size = ring->wptr + (ring->ring_size / 4); in radeon_ring_backup()
472 uint32_t rptr, wptr, rptr_next; in radeon_debugfs_ring_info_show() local
478 wptr = radeon_ring_get_wptr(rdev, ring); in radeon_debugfs_ring_info_show()
480 wptr, wptr); in radeon_debugfs_ring_info_show()
494 ring->wptr, ring->wptr); in radeon_debugfs_ring_info_show()
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/
H A Drpc.c153 u32 wptr = *gsp->msgq.wptr; in r535_gsp_msgq_wait() local
155 used = wptr + gsp->msgq.cnt - rptr; in r535_gsp_msgq_wait()
361 u32 wptr, size, step, len; in r535_gsp_cmdq_push() local
377 wptr = *gsp->cmdq.wptr; in r535_gsp_cmdq_push()
380 free = *gsp->cmdq.rptr + gsp->cmdq.cnt - wptr - 1; in r535_gsp_cmdq_push()
394 cqe = (void *)((u8 *)gsp->shm.cmdq.ptr + 0x1000 + wptr * 0x1000); in r535_gsp_cmdq_push()
395 step = min_t(u32, free, (gsp->cmdq.cnt - wptr)); in r535_gsp_cmdq_push()
400 wptr += DIV_ROUND_UP(size, 0x1000); in r535_gsp_cmdq_push()
401 if (wptr == gsp->cmdq.cnt) in r535_gsp_cmdq_push()
402 wptr = 0; in r535_gsp_cmdq_push()
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