Lines Matching refs:wptr

153 	ret = ring->wptr & ring->buf_mask;  in sdma_v5_2_ring_init_cond_exec()
188 u64 wptr; in sdma_v5_2_ring_get_wptr() local
192 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); in sdma_v5_2_ring_get_wptr()
193 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); in sdma_v5_2_ring_get_wptr()
195 wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); in sdma_v5_2_ring_get_wptr()
196 wptr = wptr << 32; in sdma_v5_2_ring_get_wptr()
197 wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)); in sdma_v5_2_ring_get_wptr()
198 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr); in sdma_v5_2_ring_get_wptr()
201 return wptr >> 2; in sdma_v5_2_ring_get_wptr()
222 lower_32_bits(ring->wptr << 2), in sdma_v5_2_ring_set_wptr()
223 upper_32_bits(ring->wptr << 2)); in sdma_v5_2_ring_set_wptr()
226 ring->wptr << 2); in sdma_v5_2_ring_set_wptr()
228 ring->doorbell_index, ring->wptr << 2); in sdma_v5_2_ring_set_wptr()
229 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); in sdma_v5_2_ring_set_wptr()
236 lower_32_bits(ring->wptr << 2)); in sdma_v5_2_ring_set_wptr()
238 upper_32_bits(ring->wptr << 2)); in sdma_v5_2_ring_set_wptr()
245 lower_32_bits(ring->wptr << 2), in sdma_v5_2_ring_set_wptr()
247 upper_32_bits(ring->wptr << 2)); in sdma_v5_2_ring_set_wptr()
249 lower_32_bits(ring->wptr << 2)); in sdma_v5_2_ring_set_wptr()
251 upper_32_bits(ring->wptr << 2)); in sdma_v5_2_ring_set_wptr()
294 sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); in sdma_v5_2_ring_emit_ib()
566 …C15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), lower_32_bits(ring->wptr << 2)); in sdma_v5_2_gfx_resume_instance()
567 …_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), upper_32_bits(ring->wptr << 2)); in sdma_v5_2_gfx_resume_instance()
568 …C15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2)); in sdma_v5_2_gfx_resume_instance()
569 …_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); in sdma_v5_2_gfx_resume_instance()
603 ring->wptr = 0; in sdma_v5_2_gfx_resume_instance()
609 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2)); in sdma_v5_2_gfx_resume_instance()
610 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); in sdma_v5_2_gfx_resume_instance()