Lines Matching refs:wptr
668 * Get the current wptr from the hardware (VEGA10+).
673 u64 wptr;
677 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
678 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
680 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI);
681 wptr = wptr << 32;
682 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR);
683 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n",
684 ring->me, wptr);
687 return wptr >> 2;
695 * Write the wptr back to the hardware (VEGA10+).
707 "lower_32_bits(ring->wptr << 2) == 0x%08x "
708 "upper_32_bits(ring->wptr << 2) == 0x%08x\n",
710 lower_32_bits(ring->wptr << 2),
711 upper_32_bits(ring->wptr << 2));
713 WRITE_ONCE(*wb, (ring->wptr << 2));
715 ring->doorbell_index, ring->wptr << 2);
716 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
722 lower_32_bits(ring->wptr << 2),
724 upper_32_bits(ring->wptr << 2));
726 lower_32_bits(ring->wptr << 2));
728 upper_32_bits(ring->wptr << 2));
737 * Get the current wptr from the hardware (VEGA10+).
742 u64 wptr;
746 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
748 wptr = RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI);
749 wptr = wptr << 32;
750 wptr |= RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR);
753 return wptr >> 2;
761 * Write the wptr back to the hardware (VEGA10+).
771 WRITE_ONCE(*wb, (ring->wptr << 2));
772 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
774 uint64_t wptr = ring->wptr << 2;
777 lower_32_bits(wptr));
779 upper_32_bits(wptr));
814 sdma_v4_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
1118 ring->wptr = 0;
1120 /* before programing wptr to a less value, need set minor_ptr_update first */
1136 /* set minor_ptr_update to 0 after wptr programed */
1139 /* setup the wptr shadow polling */
1203 ring->wptr = 0;
1205 /* before programing wptr to a less value, need set minor_ptr_update first */
1222 /* set minor_ptr_update to 0 after wptr programed */
1225 /* setup the wptr shadow polling */