Searched refs:clr (Results 1 – 5 of 5) sorted by relevance
130 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { in preemption_timer_init()139 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) in preemption_timer_init()148 if (ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) { in preemption_timer_main()220 EXI_SAVE_PREEMPT) & ctrl_exit_rev.clr; in preemption_timer_exit_handler()310 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT) && in test_ctrl_pat_init()311 !(ctrl_exit_rev.clr & EXI_LOAD_PAT) && in test_ctrl_pat_init()312 !(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { in test_ctrl_pat_init()319 ctrl_ent |= ctrl_enter_rev.clr & ENT_LOAD_PAT; in test_ctrl_pat_init()320 ctrl_exi |= ctrl_exit_rev.clr & (EXI_SAVE_PAT | EXI_LOAD_PAT); in test_ctrl_pat_init()334 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) in test_ctrl_pat_main()[all …]
1106 ctrl_cpu_rev[1].clr; in init_vmcs_ctrl()1129 if (ctrl_exit_rev.clr & EXI_LOAD_PAT) in init_vmcs_host()1258 ctrl_pin = (ctrl_pin | ctrl_pin_rev.set) & ctrl_pin_rev.clr; in init_vmcs()1259 ctrl_enter = (ctrl_enter | ctrl_enter_rev.set) & ctrl_enter_rev.clr; in init_vmcs()1260 ctrl_exit = (ctrl_exit | ctrl_exit_rev.set) & ctrl_exit_rev.clr; in init_vmcs()1261 ctrl_cpu[0] = (ctrl_cpu[0] | ctrl_cpu_rev[0].set) & ctrl_cpu_rev[0].clr; in init_vmcs()1293 if ((ctrl_cpu_rev[0].clr & CPU_SECONDARY) != 0) in init_vmx_caps()1297 if ((ctrl_cpu_rev[1].clr & (CPU_EPT | CPU_VPID)) != 0) in init_vmx_caps()1604 report((!(ctrl_cpu_rev[1].clr & CPU_URG) || val & (1ul << 5)) && in test_vmx_caps()1613 ok = ok && (ctrl.set & ~ctrl.clr) == 0; in test_vmx_caps()[all …]
152 u32 set, clr; member824 return (ctrl_cpu_rev[0].clr & CPU_SECONDARY) && in is_vpid_supported()825 (ctrl_cpu_rev[1].clr & CPU_VPID); in is_vpid_supported()
75 void pci_cmd_set_clr(struct pci_dev *dev, uint16_t set, uint16_t clr) in pci_cmd_set_clr() argument80 assert((set & clr) == 0); in pci_cmd_set_clr()82 val &= ~clr; in pci_cmd_set_clr()
34 extern void pci_cmd_set_clr(struct pci_dev *dev, uint16_t set, uint16_t clr);