1 /*
2 * Copyright (C) 2013, Red Hat Inc, Michael S. Tsirkin <mst@redhat.com>
3 *
4 * This work is licensed under the terms of the GNU LGPL, version 2.
5 */
6 #include <linux/pci_regs.h>
7 #include "pci.h"
8 #include "asm/pci.h"
9
pci_cap_walk(struct pci_dev * dev,pci_cap_handler_t handler)10 void pci_cap_walk(struct pci_dev *dev, pci_cap_handler_t handler)
11 {
12 uint8_t cap_offset;
13 uint8_t cap_id;
14 int count = 0;
15
16 cap_offset = pci_config_readb(dev->bdf, PCI_CAPABILITY_LIST);
17 while (cap_offset) {
18 cap_id = pci_config_readb(dev->bdf, cap_offset);
19 assert(cap_id < PCI_CAP_ID_MAX + 1);
20 handler(dev, cap_offset, cap_id);
21 cap_offset = pci_config_readb(dev->bdf, cap_offset + 1);
22 /* Avoid dead loop during cap walk */
23 assert(++count <= 255);
24 }
25 }
26
pci_msi_set_enable(struct pci_dev * dev,bool enabled)27 void pci_msi_set_enable(struct pci_dev *dev, bool enabled)
28 {
29 uint16_t msi_control;
30 uint16_t offset;
31
32 offset = dev->msi_offset;
33 msi_control = pci_config_readw(dev->bdf, offset + PCI_MSI_FLAGS);
34
35 if (enabled)
36 msi_control |= PCI_MSI_FLAGS_ENABLE;
37 else
38 msi_control &= ~PCI_MSI_FLAGS_ENABLE;
39
40 pci_config_writew(dev->bdf, offset + PCI_MSI_FLAGS, msi_control);
41 }
42
pci_setup_msi(struct pci_dev * dev,uint64_t msi_addr,uint32_t msi_data)43 bool pci_setup_msi(struct pci_dev *dev, uint64_t msi_addr, uint32_t msi_data)
44 {
45 uint16_t msi_control;
46 uint16_t offset;
47 pcidevaddr_t addr;
48
49 assert(dev);
50
51 if (!dev->msi_offset) {
52 printf("MSI: dev %#x does not support MSI.\n", dev->bdf);
53 return false;
54 }
55
56 addr = dev->bdf;
57 offset = dev->msi_offset;
58 msi_control = pci_config_readw(addr, offset + PCI_MSI_FLAGS);
59 pci_config_writel(addr, offset + PCI_MSI_ADDRESS_LO,
60 msi_addr & 0xffffffff);
61
62 if (msi_control & PCI_MSI_FLAGS_64BIT) {
63 pci_config_writel(addr, offset + PCI_MSI_ADDRESS_HI,
64 (uint32_t)(msi_addr >> 32));
65 pci_config_writel(addr, offset + PCI_MSI_DATA_64, msi_data);
66 } else {
67 pci_config_writel(addr, offset + PCI_MSI_DATA_32, msi_data);
68 }
69
70 pci_msi_set_enable(dev, true);
71
72 return true;
73 }
74
pci_cmd_set_clr(struct pci_dev * dev,uint16_t set,uint16_t clr)75 void pci_cmd_set_clr(struct pci_dev *dev, uint16_t set, uint16_t clr)
76 {
77 uint16_t val = pci_config_readw(dev->bdf, PCI_COMMAND);
78
79 /* No overlap is allowed */
80 assert((set & clr) == 0);
81 val |= set;
82 val &= ~clr;
83
84 pci_config_writew(dev->bdf, PCI_COMMAND, val);
85 }
86
pci_dev_exists(pcidevaddr_t dev)87 bool pci_dev_exists(pcidevaddr_t dev)
88 {
89 return (pci_config_readw(dev, PCI_VENDOR_ID) != 0xffff &&
90 pci_config_readw(dev, PCI_DEVICE_ID) != 0xffff);
91 }
92
93 /* Scan bus look for a specific device. Only bus 0 scanned for now. */
pci_find_dev(uint16_t vendor_id,uint16_t device_id)94 pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id)
95 {
96 pcidevaddr_t dev;
97
98 for (dev = 0; dev < PCI_DEVFN_MAX; ++dev) {
99 if (pci_config_readw(dev, PCI_VENDOR_ID) == vendor_id &&
100 pci_config_readw(dev, PCI_DEVICE_ID) == device_id)
101 return dev;
102 }
103
104 return PCIDEVADDR_INVALID;
105 }
106
pci_bar_mask(uint32_t bar)107 uint32_t pci_bar_mask(uint32_t bar)
108 {
109 return (bar & PCI_BASE_ADDRESS_SPACE_IO) ?
110 PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK;
111 }
112
pci_bar_get(struct pci_dev * dev,int bar_num)113 uint32_t pci_bar_get(struct pci_dev *dev, int bar_num)
114 {
115 ASSERT_BAR_NUM(bar_num);
116
117 return pci_config_readl(dev->bdf, PCI_BASE_ADDRESS_0 +
118 bar_num * 4);
119 }
120
__pci_bar_get_addr(struct pci_dev * dev,int bar_num)121 static phys_addr_t __pci_bar_get_addr(struct pci_dev *dev, int bar_num)
122 {
123 uint32_t bar = pci_bar_get(dev, bar_num);
124 uint32_t mask = pci_bar_mask(bar);
125 uint64_t addr = bar & mask;
126 phys_addr_t phys_addr;
127
128 if (pci_bar_is64(dev, bar_num))
129 addr |= (uint64_t)pci_bar_get(dev, bar_num + 1) << 32;
130
131 phys_addr = pci_translate_addr(dev->bdf, addr);
132 assert(phys_addr != INVALID_PHYS_ADDR);
133
134 return phys_addr;
135 }
136
pci_bar_get_addr(struct pci_dev * dev,int bar_num)137 phys_addr_t pci_bar_get_addr(struct pci_dev *dev, int bar_num)
138 {
139 ASSERT_BAR_NUM(bar_num);
140
141 return dev->resource[bar_num];
142 }
143
pci_bar_set_addr(struct pci_dev * dev,int bar_num,phys_addr_t addr)144 void pci_bar_set_addr(struct pci_dev *dev, int bar_num, phys_addr_t addr)
145 {
146 int off = PCI_BASE_ADDRESS_0 + bar_num * 4;
147
148 assert(addr != INVALID_PHYS_ADDR);
149 assert(dev->resource[bar_num] != INVALID_PHYS_ADDR);
150
151 ASSERT_BAR_NUM(bar_num);
152 if (pci_bar_is64(dev, bar_num))
153 ASSERT_BAR_NUM(bar_num + 1);
154 else
155 assert((addr >> 32) == 0);
156
157 pci_config_writel(dev->bdf, off, (uint32_t)addr);
158 dev->resource[bar_num] = addr;
159
160 if (pci_bar_is64(dev, bar_num)) {
161 pci_config_writel(dev->bdf, off + 4, (uint32_t)(addr >> 32));
162 dev->resource[bar_num + 1] = dev->resource[bar_num];
163 }
164 }
165
166 /*
167 * To determine the amount of address space needed by a PCI device,
168 * one must save the original value of the BAR, write a value of
169 * all 1's to the register, and then read it back. The amount of
170 * memory can be then determined by masking the information bits,
171 * performing a bitwise NOT, and incrementing the value by 1.
172 *
173 * The following pci_bar_size_helper() and pci_bar_size() functions
174 * implement the algorithm.
175 */
pci_bar_size_helper(struct pci_dev * dev,int bar_num)176 static uint32_t pci_bar_size_helper(struct pci_dev *dev, int bar_num)
177 {
178 int off = PCI_BASE_ADDRESS_0 + bar_num * 4;
179 uint16_t bdf = dev->bdf;
180 uint32_t bar, val;
181
182 bar = pci_config_readl(bdf, off);
183 pci_config_writel(bdf, off, ~0u);
184 val = pci_config_readl(bdf, off);
185 pci_config_writel(bdf, off, bar);
186
187 return val;
188 }
189
pci_bar_size(struct pci_dev * dev,int bar_num)190 phys_addr_t pci_bar_size(struct pci_dev *dev, int bar_num)
191 {
192 uint32_t bar, size;
193
194 size = pci_bar_size_helper(dev, bar_num);
195 if (!size)
196 return 0;
197
198 bar = pci_bar_get(dev, bar_num);
199 size &= pci_bar_mask(bar);
200
201 if (pci_bar_is64(dev, bar_num)) {
202 phys_addr_t size64 = pci_bar_size_helper(dev, bar_num + 1);
203 size64 = (size64 << 32) | size;
204
205 return ~size64 + 1;
206 } else {
207 return ~size + 1;
208 }
209 }
210
pci_bar_is_memory(struct pci_dev * dev,int bar_num)211 bool pci_bar_is_memory(struct pci_dev *dev, int bar_num)
212 {
213 uint32_t bar = pci_bar_get(dev, bar_num);
214
215 return !(bar & PCI_BASE_ADDRESS_SPACE_IO);
216 }
217
pci_bar_is_valid(struct pci_dev * dev,int bar_num)218 bool pci_bar_is_valid(struct pci_dev *dev, int bar_num)
219 {
220 return dev->resource[bar_num] != INVALID_PHYS_ADDR;
221 }
222
pci_bar_is64(struct pci_dev * dev,int bar_num)223 bool pci_bar_is64(struct pci_dev *dev, int bar_num)
224 {
225 uint32_t bar = pci_bar_get(dev, bar_num);
226
227 if (bar & PCI_BASE_ADDRESS_SPACE_IO)
228 return false;
229
230 return (bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
231 PCI_BASE_ADDRESS_MEM_TYPE_64;
232 }
233
pci_bar_print(struct pci_dev * dev,int bar_num)234 void pci_bar_print(struct pci_dev *dev, int bar_num)
235 {
236 phys_addr_t size, start, end;
237 uint32_t bar;
238
239 if (!pci_bar_is_valid(dev, bar_num))
240 return;
241
242 bar = pci_bar_get(dev, bar_num);
243 size = pci_bar_size(dev, bar_num);
244 start = pci_bar_get_addr(dev, bar_num);
245 end = start + size - 1;
246
247 if (pci_bar_is64(dev, bar_num)) {
248 printf("BAR#%d,%d [%" PRIx64 "-%" PRIx64 " ",
249 bar_num, bar_num + 1, start, end);
250 } else {
251 printf("BAR#%d [%02" PRIx32 "-%02" PRIx32 " ",
252 bar_num, (uint32_t)start, (uint32_t)end);
253 }
254
255 if (bar & PCI_BASE_ADDRESS_SPACE_IO) {
256 printf("PIO");
257 } else {
258 printf("MEM");
259 switch (bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK) {
260 case PCI_BASE_ADDRESS_MEM_TYPE_32:
261 printf("32");
262 break;
263 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
264 printf("1M");
265 break;
266 case PCI_BASE_ADDRESS_MEM_TYPE_64:
267 printf("64");
268 break;
269 default:
270 assert(0);
271 }
272 }
273
274 if (bar & PCI_BASE_ADDRESS_MEM_PREFETCH)
275 printf("/p");
276
277 printf("]");
278 }
279
pci_dev_print_id(struct pci_dev * dev)280 void pci_dev_print_id(struct pci_dev *dev)
281 {
282 pcidevaddr_t bdf = dev->bdf;
283
284 printf("00.%02x.%1x %04x:%04x", bdf / 8, bdf % 8,
285 pci_config_readw(bdf, PCI_VENDOR_ID),
286 pci_config_readw(bdf, PCI_DEVICE_ID));
287 }
288
pci_cap_print(struct pci_dev * dev,int cap_offset,int cap_id)289 static void pci_cap_print(struct pci_dev *dev, int cap_offset, int cap_id)
290 {
291 switch (cap_id) {
292 case PCI_CAP_ID_MSI: {
293 uint16_t control = pci_config_readw(dev->bdf, cap_offset + PCI_MSI_FLAGS);
294 printf("\tMSI,%s-bit capability ", control & PCI_MSI_FLAGS_64BIT ? "64" : "32");
295 break;
296 }
297 default:
298 printf("\tcapability %#04x ", cap_id);
299 break;
300 }
301 printf("at offset %#04x\n", cap_offset);
302 }
303
pci_dev_print(struct pci_dev * dev)304 void pci_dev_print(struct pci_dev *dev)
305 {
306 pcidevaddr_t bdf = dev->bdf;
307 uint8_t header = pci_config_readb(bdf, PCI_HEADER_TYPE);
308 uint8_t progif = pci_config_readb(bdf, PCI_CLASS_PROG);
309 uint8_t subclass = pci_config_readb(bdf, PCI_CLASS_DEVICE);
310 uint8_t class = pci_config_readb(bdf, PCI_CLASS_DEVICE + 1);
311 int i;
312
313 pci_dev_print_id(dev);
314 printf(" type %02x progif %02x class %02x subclass %02x\n",
315 header, progif, class, subclass);
316
317 pci_cap_walk(dev, pci_cap_print);
318
319 if ((header & PCI_HEADER_TYPE_MASK) != PCI_HEADER_TYPE_NORMAL)
320 return;
321
322 for (i = 0; i < PCI_BAR_NUM; i++) {
323 if (pci_bar_is_valid(dev, i)) {
324 printf("\t");
325 pci_bar_print(dev, i);
326 printf("\n");
327 }
328 if (pci_bar_is64(dev, i))
329 i++;
330 }
331 }
332
pci_print(void)333 void pci_print(void)
334 {
335 pcidevaddr_t devfn;
336 struct pci_dev pci_dev;
337
338 for (devfn = 0; devfn < PCI_DEVFN_MAX; ++devfn) {
339 if (pci_dev_exists(devfn)) {
340 pci_dev_init(&pci_dev, devfn);
341 pci_dev_print(&pci_dev);
342 }
343 }
344 }
345
pci_dev_init(struct pci_dev * dev,pcidevaddr_t bdf)346 void pci_dev_init(struct pci_dev *dev, pcidevaddr_t bdf)
347 {
348 int i;
349
350 memset(dev, 0, sizeof(*dev));
351 dev->bdf = bdf;
352
353 for (i = 0; i < PCI_BAR_NUM; i++) {
354 if (pci_bar_size(dev, i)) {
355 dev->resource[i] = __pci_bar_get_addr(dev, i);
356 if (pci_bar_is64(dev, i)) {
357 assert(i + 1 < PCI_BAR_NUM);
358 dev->resource[i + 1] = dev->resource[i];
359 i++;
360 }
361 } else {
362 dev->resource[i] = INVALID_PHYS_ADDR;
363 }
364 }
365 }
366
pci_intx_line(struct pci_dev * dev)367 uint8_t pci_intx_line(struct pci_dev *dev)
368 {
369 return pci_config_readb(dev->bdf, PCI_INTERRUPT_LINE);
370 }
371
pci_cap_setup(struct pci_dev * dev,int cap_offset,int cap_id)372 static void pci_cap_setup(struct pci_dev *dev, int cap_offset, int cap_id)
373 {
374 switch (cap_id) {
375 case PCI_CAP_ID_MSI:
376 dev->msi_offset = cap_offset;
377 break;
378 }
379 }
380
pci_enable_defaults(struct pci_dev * dev)381 void pci_enable_defaults(struct pci_dev *dev)
382 {
383 /* Enable device DMA operations */
384 pci_cmd_set_clr(dev, PCI_COMMAND_MASTER, 0);
385 pci_cap_walk(dev, pci_cap_setup);
386 }
387