Searched refs:PMCR (Results 1 – 9 of 9) sorted by relevance
17 #define PMCR(n) (PM_CR_BASE + ((n) * 0x04)) macro 33 * corresponds to the PMCR PMM setting. Each counter can be configured212 tmp = __raw_readw(PMCR(idx)); in sh7750_pmu_disable() 214 __raw_writew(tmp, PMCR(idx)); in sh7750_pmu_disable() 219 __raw_writew(__raw_readw(PMCR(idx)) | PMCR_PMCLR, PMCR(idx)); in sh7750_pmu_enable() 220 __raw_writew(hwc->config | PMCR_PMEN | PMCR_PMST, PMCR(idx)); in sh7750_pmu_enable() 228 __raw_writew(__raw_readw(PMCR(i)) & ~PMCR_PMEN, PMCR(i)); in sh7750_pmu_disable_all() 236 __raw_writew(__raw_readw(PMCR( in sh7750_pmu_enable_all() [all...]
77 * r12 = &PMCR78 * r13 = PMCR value (1)110 ldr r12, =PMCR139 @ Step 6 set force sleep bit in PMCR
91 PMCR = PMCR_SF; in sa1100_power_off()
26 #define PMCR __REG(0x40F50000) /* Power Manager Control Register */ macro
20 #define PMCR __REG(0x40F00000) /* Power Manager Control Register */ macro
1101 PMCR = 0x00; in spitz_init()
87 #define PMCR 0xE04 macro 105 /* PMCR register field */
478 writel(PMCR_C | PMCR_P, cspmu->base0 + PMCR); in arm_cspmu_reset_counters() 483 writel(PMCR_E, cspmu->base0 + PMCR); in arm_cspmu_start_counters() 488 writel(0, cspmu->base0 + PMCR); in arm_cspmu_stop_counters()
865 * PMCR Power Manager (PM) Control Register (read/write).884 #define PMCR __REG(0x90020000) /* PM Control Reg. */ macro