1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * ARM CoreSight Architecture PMU driver. 4 * Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. 5 * 6 */ 7 8 #ifndef __ARM_CSPMU_H__ 9 #define __ARM_CSPMU_H__ 10 11 #include <linux/bitfield.h> 12 #include <linux/cpumask.h> 13 #include <linux/device.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/perf_event.h> 17 #include <linux/platform_device.h> 18 #include <linux/types.h> 19 20 #define to_arm_cspmu(p) (container_of(p, struct arm_cspmu, pmu)) 21 22 #define ARM_CSPMU_EXT_ATTR(_name, _func, _config) \ 23 (&((struct dev_ext_attribute[]){ \ 24 { \ 25 .attr = __ATTR(_name, 0444, _func, NULL), \ 26 .var = (void *)_config \ 27 } \ 28 })[0].attr.attr) 29 30 #define ARM_CSPMU_FORMAT_ATTR(_name, _config) \ 31 ARM_CSPMU_EXT_ATTR(_name, device_show_string, _config) 32 33 #define ARM_CSPMU_EVENT_ATTR(_name, _config) \ 34 PMU_EVENT_ATTR_ID(_name, arm_cspmu_sysfs_event_show, _config) 35 36 37 /* Default event id mask */ 38 #define ARM_CSPMU_EVENT_MASK GENMASK_ULL(63, 0) 39 40 /* Default filter value mask */ 41 #define ARM_CSPMU_FILTER_MASK GENMASK_ULL(63, 0) 42 43 /* Default event format */ 44 #define ARM_CSPMU_FORMAT_EVENT_ATTR \ 45 ARM_CSPMU_FORMAT_ATTR(event, "config:0-32") 46 47 /* Default filter format */ 48 #define ARM_CSPMU_FORMAT_FILTER_ATTR \ 49 ARM_CSPMU_FORMAT_ATTR(filter, "config1:0-31") 50 #define ARM_CSPMU_FORMAT_FILTER2_ATTR \ 51 ARM_CSPMU_FORMAT_ATTR(filter2, "config2:0-31") 52 53 /* 54 * This is the default event number for cycle count, if supported, since the 55 * ARM Coresight PMU specification does not define a standard event code 56 * for cycle count. 57 */ 58 #define ARM_CSPMU_EVT_CYCLES_DEFAULT (0x1ULL << 32) 59 60 /* 61 * The ARM Coresight PMU supports up to 256 event counters. 62 * If the counters are larger-than 32-bits, then the PMU includes at 63 * most 128 counters. 64 */ 65 #define ARM_CSPMU_MAX_HW_CNTRS 256 66 67 /* The cycle counter, if implemented, is located at counter[31]. */ 68 #define ARM_CSPMU_CYCLE_CNTR_IDX 31 69 70 /* 71 * CoreSight PMU Arch register offsets. 72 */ 73 #define PMEVCNTR_LO 0x0 74 #define PMEVCNTR_HI 0x4 75 #define PMEVTYPER 0x400 76 #define PMCCFILTR 0x47C 77 #define PMEVFILT2R 0x800 78 #define PMEVFILTR 0xA00 79 #define PMCNTENSET 0xC00 80 #define PMCNTENCLR 0xC20 81 #define PMINTENSET 0xC40 82 #define PMINTENCLR 0xC60 83 #define PMOVSCLR 0xC80 84 #define PMOVSSET 0xCC0 85 #define PMIMPDEF 0xD80 86 #define PMCFGR 0xE00 87 #define PMCR 0xE04 88 #define PMIIDR 0xE08 89 90 /* PMCFGR register field */ 91 #define PMCFGR_NCG GENMASK(31, 28) 92 #define PMCFGR_HDBG BIT(24) 93 #define PMCFGR_TRO BIT(23) 94 #define PMCFGR_SS BIT(22) 95 #define PMCFGR_FZO BIT(21) 96 #define PMCFGR_MSI BIT(20) 97 #define PMCFGR_UEN BIT(19) 98 #define PMCFGR_NA BIT(17) 99 #define PMCFGR_EX BIT(16) 100 #define PMCFGR_CCD BIT(15) 101 #define PMCFGR_CC BIT(14) 102 #define PMCFGR_SIZE GENMASK(13, 8) 103 #define PMCFGR_N GENMASK(7, 0) 104 105 /* PMCR register field */ 106 #define PMCR_TRO BIT(11) 107 #define PMCR_HDBG BIT(10) 108 #define PMCR_FZO BIT(9) 109 #define PMCR_NA BIT(8) 110 #define PMCR_DP BIT(5) 111 #define PMCR_X BIT(4) 112 #define PMCR_D BIT(3) 113 #define PMCR_C BIT(2) 114 #define PMCR_P BIT(1) 115 #define PMCR_E BIT(0) 116 117 /* PMIIDR register field */ 118 #define ARM_CSPMU_PMIIDR_IMPLEMENTER GENMASK(11, 0) 119 #define ARM_CSPMU_PMIIDR_PRODUCTID GENMASK(31, 20) 120 121 /* JEDEC-assigned JEP106 identification code */ 122 #define ARM_CSPMU_IMPL_ID_NVIDIA 0x36B 123 #define ARM_CSPMU_IMPL_ID_AMPERE 0xA16 124 125 struct arm_cspmu; 126 127 /* This tracks the events assigned to each counter in the PMU. */ 128 struct arm_cspmu_hw_events { 129 /* The events that are active on the PMU for a given logical index. */ 130 struct perf_event **events; 131 132 /* 133 * Each bit indicates a logical counter is being used (or not) for an 134 * event. If cycle counter is supported and there is a gap between 135 * regular and cycle counter, the last logical counter is mapped to 136 * cycle counter. Otherwise, logical and physical have 1-to-1 mapping. 137 */ 138 DECLARE_BITMAP(used_ctrs, ARM_CSPMU_MAX_HW_CNTRS); 139 }; 140 141 /* Contains ops to query vendor/implementer specific attribute. */ 142 struct arm_cspmu_impl_ops { 143 /* Get event attributes */ 144 struct attribute **(*get_event_attrs)(const struct arm_cspmu *cspmu); 145 /* Get format attributes */ 146 struct attribute **(*get_format_attrs)(const struct arm_cspmu *cspmu); 147 /* Get string identifier */ 148 const char *(*get_identifier)(const struct arm_cspmu *cspmu); 149 /* Get PMU name to register to core perf */ 150 const char *(*get_name)(const struct arm_cspmu *cspmu); 151 /* Check if the event corresponds to cycle count event */ 152 bool (*is_cycle_counter_event)(const struct perf_event *event); 153 /* Decode event type/id from configs */ 154 u32 (*event_type)(const struct perf_event *event); 155 /* Set event filters */ 156 void (*set_cc_filter)(struct arm_cspmu *cspmu, 157 const struct perf_event *event); 158 void (*set_ev_filter)(struct arm_cspmu *cspmu, 159 const struct perf_event *event); 160 /* Implementation specific event validation */ 161 int (*validate_event)(struct arm_cspmu *cspmu, 162 struct perf_event *event); 163 /* Hide/show unsupported events */ 164 umode_t (*event_attr_is_visible)(struct kobject *kobj, 165 struct attribute *attr, int unused); 166 }; 167 168 /* Vendor/implementer registration parameter. */ 169 struct arm_cspmu_impl_match { 170 /* Backend module. */ 171 struct module *module; 172 const char *module_name; 173 /* PMIIDR value/mask. */ 174 u32 pmiidr_val; 175 u32 pmiidr_mask; 176 /* Callback to vendor backend to init arm_cspmu_impl::ops. */ 177 int (*impl_init_ops)(struct arm_cspmu *cspmu); 178 }; 179 180 /* Vendor/implementer descriptor. */ 181 struct arm_cspmu_impl { 182 u32 pmiidr; 183 struct module *module; 184 struct arm_cspmu_impl_match *match; 185 struct arm_cspmu_impl_ops ops; 186 void *ctx; 187 }; 188 189 /* Coresight PMU descriptor. */ 190 struct arm_cspmu { 191 struct pmu pmu; 192 struct device *dev; 193 const char *name; 194 const char *identifier; 195 void __iomem *base0; 196 void __iomem *base1; 197 cpumask_t associated_cpus; 198 cpumask_t active_cpu; 199 struct hlist_node cpuhp_node; 200 int irq; 201 202 bool has_atomic_dword; 203 u32 pmcfgr; 204 u32 num_logical_ctrs; 205 u32 num_set_clr_reg; 206 int cycle_counter_logical_idx; 207 208 struct arm_cspmu_hw_events hw_events; 209 const struct attribute_group *attr_groups[5]; 210 211 struct arm_cspmu_impl impl; 212 }; 213 214 /* Default function to show event attribute in sysfs. */ 215 ssize_t arm_cspmu_sysfs_event_show(struct device *dev, 216 struct device_attribute *attr, 217 char *buf); 218 219 /* Register vendor backend. */ 220 int arm_cspmu_impl_register(const struct arm_cspmu_impl_match *impl_match); 221 222 /* Unregister vendor backend. */ 223 void arm_cspmu_impl_unregister(const struct arm_cspmu_impl_match *impl_match); 224 225 #endif /* __ARM_CSPMU_H__ */ 226