Searched +full:zynqmp +full:- +full:reset (Results 1 – 11 of 11) sorted by relevance
2 * QEMU model of the ZynqMP APU Control.4 * Copyright (c) 2013-2022 Xilinx Inc5 * SPDX-License-Identifier: GPL-2.0-or-later15 #include "hw/qdev-properties.h"22 #include "hw/misc/xlnx-zynqmp-apu-ctrl.h"33 wfi_pending = s->cpu_pwrdwn_req & s->cpu_in_wfi; in update_wfi_out()35 qemu_set_irq(s->wfi_out[i], !!(wfi_pending & (1 << i))); in update_wfi_out()41 XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque); in zynqmp_apu_rvbar_post_write()45 uint64_t rvbar = s->regs[R_RVBARADDR0L + 2 * i] + in zynqmp_apu_rvbar_post_write()46 ((uint64_t)s->regs[R_RVBARADDR0H + 2 * i] << 32); in zynqmp_apu_rvbar_post_write()[all …]
2 * QEMU model of the CRF - Clock Reset FPD.5 * SPDX-License-Identifier: GPL-2.0-or-later16 #include "hw/misc/xlnx-zynqmp-crf.h"17 #include "target/arm/arm-powerctl.h"27 bool pending = s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK]; in ir_update_irq()28 qemu_set_irq(s->irq_ir, pending); in ir_update_irq()33 XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(reg->opaque); in ir_status_postw()39 XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(reg->opaque); in ir_enable_prew()42 s->regs[R_IR_MASK] &= ~val; in ir_enable_prew()49 XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(reg->opaque); in ir_disable_prew()[all …]
2 * QEMU model of the Xilinx ZynqMP Real Time Clock (RTC).6 * Written-by: Alistair Francis <alistair.francis@xilinx.com>38 #include "hw/rtc/xlnx-zynqmp-rtc.h"47 bool pending = s->regs[R_RTC_INT_STATUS] & ~s->regs[R_RTC_INT_MASK]; in rtc_int_update_irq()48 qemu_set_irq(s->irq_rtc_int, pending); in rtc_int_update_irq()53 bool pending = s->regs[R_ADDR_ERROR] & ~s->regs[R_ADDR_ERROR_INT_MASK]; in addr_error_int_update_irq()54 qemu_set_irq(s->irq_addr_error_int, pending); in addr_error_int_update_irq()60 return s->tick_offset + now / NANOSECONDS_PER_SECOND; in rtc_get_count()65 XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); in current_time_postr()72 XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque); in rtc_int_status_postw()[all …]
2 * QEMU model of the ZynqMP eFuse29 #include "hw/nvram/xlnx-zynqmp-efuse.h"34 #include "hw/qdev-properties.h"203 * ZynqMP: UG1085 (v2.1) August 21, 2019, p.277, Table 12-13260 ARRAY_FIELD_DP32((s)->regs, reg, field, \261 (xlnx_efuse_get_row((s->efuse), EFUSE_ ## field) \265 ARRAY_FIELD_DP32((s)->regs, reg, field, xlnx_efuse_get_bit((s->efuse), \270 QEMU_BUILD_BUG_ON(R_MAX != ARRAY_SIZE(((XlnxZynqMPEFuse *)0)->regs));274 unsigned int check = xlnx_efuse_tbits_check(s->efuse); in update_tbit_status()275 uint32_t val = s->regs[R_STATUS]; in update_tbit_status()[all …]
21 #include "hw/arm/xlnx-zynqmp.h"26 #include "target/arm/cpu-qom.h"216 int num_rpus = MIN((int)(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS), in xlnx_zynqmp_create_rpu()220 /* Don't create rpu-cluster object if there's nothing to put in it */ in xlnx_zynqmp_create_rpu()224 object_initialize_child(OBJECT(s), "rpu-cluster", &s->rpu_cluster, in xlnx_zynqmp_create_rpu()226 qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1); in xlnx_zynqmp_create_rpu()231 object_initialize_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]", in xlnx_zynqmp_create_rpu()232 &s->rpu_cpu[i], in xlnx_zynqmp_create_rpu()233 ARM_CPU_TYPE_NAME("cortex-r5f")); in xlnx_zynqmp_create_rpu()235 name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i])); in xlnx_zynqmp_create_rpu()[all …]
25 #include "hw/qdev-properties.h"36 * https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers50 FIELD(CTRL, FIFOTHRESH, 25, 7) /* rw, only exists in DST, reset 0x40 */54 FIELD(CTRL, TIMEOUT_VAL, 10, 12) /* rw, reset: 0xFFE */55 FIELD(CTRL, FIFO_THRESH, 2, 8) /* rw, reset: 0x80 */87 FIELD(INT_MASK, FIFO_OVERFLOW, 7, 1) /* ro, reset: 0x1 */88 FIELD(INT_MASK, INVALID_APB, 6, 1) /* ro, reset: 0x1 */89 FIELD(INT_MASK, THRESH_HIT, 5, 1) /* ro, reset: 0x1 */90 FIELD(INT_MASK, TIMEOUT_MEM, 4, 1) /* ro, reset: 0x1 */91 FIELD(INT_MASK, TIMEOUT_STRM, 3, 1) /* ro, reset: 0x1 */[all …]
2 * QEMU model of the ZynqMP generic DMA30 #include "hw/dma/xlnx-zdma.h"32 #include "hw/qdev-properties.h"213 pending = s->regs[R_ZDMA_CH_ISR] & ~s->regs[R_ZDMA_CH_IMR]; in zdma_ch_imr_update_irq()215 qemu_set_irq(s->irq_zdma_ch_imr, pending); in zdma_ch_imr_update_irq()220 XlnxZDMA *s = XLNX_ZDMA(reg->opaque); in zdma_ch_isr_postw()226 XlnxZDMA *s = XLNX_ZDMA(reg->opaque); in zdma_ch_ien_prew()229 s->regs[R_ZDMA_CH_IMR] &= ~val; in zdma_ch_ien_prew()236 XlnxZDMA *s = XLNX_ZDMA(reg->opaque); in zdma_ch_ids_prew()239 s->regs[R_ZDMA_CH_IMR] |= val; in zdma_ch_ids_prew()[all …]
2 * QEMU model of the Xilinx ZynqMP CAN controller.4 * https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf8 * Written-by: Vikram Garhwal<fnu.vikram@xilinx.com>41 #include "hw/qdev-properties.h"46 #include "hw/net/xlnx-zynqmp-can.h"258 if ((fifo32_num_free(&s->tx_fifo) / CAN_FRAME_SIZE) > in can_update_irq()259 ARRAY_FIELD_EX32(s->regs, WIR, EW)) { in can_update_irq()260 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXFWMEMP, 1); in can_update_irq()263 if ((fifo32_num_used(&s->rx_fifo) / CAN_FRAME_SIZE) > in can_update_irq()264 ARRAY_FIELD_EX32(s->regs, WIR, FW)) { in can_update_irq()[all …]
35 #include "hw/intc/xlnx-zynqmp-ipi.h"150 qemu_set_irq(s->irq_trig_out[i], !!(val & ipi_mask)); in xlnx_zynqmp_ipi_set_trig()163 qemu_set_irq(s->irq_obs_out[i], !!(val & ipi_mask)); in xlnx_zynqmp_ipi_set_obs()169 bool pending = s->regs[R_IPI_ISR] & ~s->regs[R_IPI_IMR]; in xlnx_zynqmp_ipi_update_irq()172 pending, s->regs[R_IPI_ISR], s->regs[R_IPI_IMR]); in xlnx_zynqmp_ipi_update_irq()173 qemu_set_irq(s->irq, pending); in xlnx_zynqmp_ipi_update_irq()178 XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque); in xlnx_zynqmp_ipi_trig_prew()187 XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque); in xlnx_zynqmp_ipi_trig_postw()190 * post-write callback to bring the signal back-down. in xlnx_zynqmp_ipi_trig_postw()192 s->regs[R_IPI_TRIG] = 0; in xlnx_zynqmp_ipi_trig_postw()[all …]
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10 consult qemu-devel and not any specific individual privately.23 W: Web-page with status/info59 ------------------------------63 L: qemu-devel@nongnu.org72 R: Philippe Mathieu-Daudé <philmd@linaro.org>75 F: docs/devel/build-environment.rst76 F: docs/devel/code-of-conduct.rst78 F: docs/devel/conflict-resolution.rst80 F: docs/devel/submitting-a-patch.rst81 F: docs/devel/submitting-a-pull-request.rst[all …]