2  * QEMU model of the ZynqMP APU Control.
4  * Copyright (c) 2013-2022 Xilinx Inc
5  * SPDX-License-Identifier: GPL-2.0-or-later
15 #include "hw/qdev-properties.h"
22 #include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
33     wfi_pending = s->cpu_pwrdwn_req & s->cpu_in_wfi;  in update_wfi_out()
35         qemu_set_irq(s->wfi_out[i], !!(wfi_pending & (1 << i)));  in update_wfi_out()
41     XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque);  in zynqmp_apu_rvbar_post_write()
45         uint64_t rvbar = s->regs[R_RVBARADDR0L + 2 * i] +  in zynqmp_apu_rvbar_post_write()
46                          ((uint64_t)s->regs[R_RVBARADDR0H + 2 * i] << 32);  in zynqmp_apu_rvbar_post_write()
47         if (s->cpus[i]) {  in zynqmp_apu_rvbar_post_write()
48             object_property_set_int(OBJECT(s->cpus[i]), "rvbar", rvbar,  in zynqmp_apu_rvbar_post_write()
56     XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque);  in zynqmp_apu_pwrctl_post_write()
62         if (new != (s->cpu_pwrdwn_req & (1 << i))) {  in zynqmp_apu_pwrctl_post_write()
63             qemu_set_irq(s->cpu_power_status[i], !!new);  in zynqmp_apu_pwrctl_post_write()
65         s->cpu_pwrdwn_req &= ~(1 << i);  in zynqmp_apu_pwrctl_post_write()
66         s->cpu_pwrdwn_req |= new;  in zynqmp_apu_pwrctl_post_write()
73     bool pending = s->regs[R_ISR] & ~s->regs[R_IMR];  in imr_update_irq()
74     qemu_set_irq(s->irq_imr, pending);  in imr_update_irq()
79     XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque);  in isr_postw()
85     XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque);  in ien_prew()
88     s->regs[R_IMR] &= ~val;  in ien_prew()
95     XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque);  in ids_prew()
98     s->regs[R_IMR] |= val;  in ids_prew()
106             .reset = 0xffff0000ul,                                         \
116         .reset = 0x1,
123         .reset = 0xf0f,
131         .reset = 0xf000f,
146         register_reset(&s->regs_info[i]);  in zynqmp_apu_reset_enter()
149     s->cpu_pwrdwn_req = 0;  in zynqmp_apu_reset_enter()
150     s->cpu_in_wfi = 0;  in zynqmp_apu_reset_enter()
175     s->cpu_in_wfi = deposit32(s->cpu_in_wfi, irq, 1, level);  in zynqmp_apu_handle_wfi()
184     s->reg_array =  in zynqmp_apu_init()
187                               s->regs_info, s->regs,  in zynqmp_apu_init()
191     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->reg_array->mem);  in zynqmp_apu_init()
192     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq_imr);  in zynqmp_apu_init()
197                                  (Object **)&s->cpus[i],  in zynqmp_apu_init()
203     qdev_init_gpio_out_named(DEVICE(obj), s->wfi_out, "wfi_out", 4);  in zynqmp_apu_init()
205     qdev_init_gpio_out_named(DEVICE(obj), s->cpu_power_status,  in zynqmp_apu_init()
214     register_finalize_block(s->reg_array);  in zynqmp_apu_finalize()
232     dc->vmsd = &vmstate_zynqmp_apu;  in zynqmp_apu_class_init()
234     rc->phases.enter = zynqmp_apu_reset_enter;  in zynqmp_apu_class_init()
235     rc->phases.hold = zynqmp_apu_reset_hold;  in zynqmp_apu_class_init()