| /qemu/hw/arm/ |
| H A D | netduinoplus2.c | 34 /* Main SYSCLK frequency in Hz (168MHz) */
40 Clock *sysclk; in netduinoplus2_init() local
43 sysclk = clock_new(OBJECT(machine), "SYSCLK"); in netduinoplus2_init()
44 clock_set_hz(sysclk, SYSCLK_FRQ); in netduinoplus2_init()
48 qdev_connect_clock_in(dev, "sysclk", sysclk); in netduinoplus2_init()
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| H A D | netduino2.c | 34 /* Main SYSCLK frequency in Hz (120MHz) */
40 Clock *sysclk; in netduino2_init() local
43 sysclk = clock_new(OBJECT(machine), "SYSCLK"); in netduino2_init()
44 clock_set_hz(sysclk, SYSCLK_FRQ); in netduino2_init()
48 qdev_connect_clock_in(dev, "sysclk", sysclk); in netduino2_init()
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| H A D | stm32vldiscovery.c | 37 /* Main SYSCLK frequency in Hz (24MHz) */
43 Clock *sysclk; in stm32vldiscovery_init() local
46 sysclk = clock_new(OBJECT(machine), "SYSCLK"); in stm32vldiscovery_init()
47 clock_set_hz(sysclk, SYSCLK_FRQ); in stm32vldiscovery_init()
51 qdev_connect_clock_in(dev, "sysclk", sysclk); in stm32vldiscovery_init()
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| H A D | olimex-stm32-h405.c | 37 /* Main SYSCLK frequency in Hz (168MHz) */
43 Clock *sysclk; in olimex_stm32_h405_init() local
46 sysclk = clock_new(OBJECT(machine), "SYSCLK"); in olimex_stm32_h405_init()
47 clock_set_hz(sysclk, SYSCLK_FRQ); in olimex_stm32_h405_init()
51 qdev_connect_clock_in(dev, "sysclk", sysclk); in olimex_stm32_h405_init()
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| H A D | stm32f100_soc.c | 62 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); in stm32f100_soc_initfn()
85 if (!clock_has_source(s->sysclk)) { in stm32f100_soc_realize()
86 error_setg(errp, "sysclk clock must be wired up by the board code"); in stm32f100_soc_realize()
92 * change the sysclk frequency and define different sysclk sources. in stm32f100_soc_realize()
97 clock_set_source(s->refclk, s->sysclk); in stm32f100_soc_realize()
121 qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); in stm32f100_soc_realize()
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| H A D | stm32f205_soc.c | 79 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); in stm32f205_soc_initfn()
102 if (!clock_has_source(s->sysclk)) { in stm32f205_soc_realize()
103 error_setg(errp, "sysclk clock must be wired up by the board code"); in stm32f205_soc_realize()
109 * change the sysclk frequency and define different sysclk sources. in stm32f205_soc_realize()
114 clock_set_source(s->refclk, s->sysclk); in stm32f205_soc_realize()
133 qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); in stm32f205_soc_realize()
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| H A D | nrf51_soc.c | 70 * HCLK on this SoC is fixed, so we set up sysclk ourselves and in nrf51_soc_realize()
73 if (clock_has_source(s->sysclk)) { in nrf51_soc_realize()
74 error_setg(errp, "sysclk clock must not be wired up by the board code"); in nrf51_soc_realize()
78 clock_set_hz(s->sysclk, HCLK_FRQ); in nrf51_soc_realize()
79 qdev_connect_clock_in(DEVICE(&s->armv7m), "cpuclk", s->sysclk); in nrf51_soc_realize()
208 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); in nrf51_soc_init()
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| H A D | stm32f405_soc.c | 87 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); in stm32f405_soc_initfn()
110 if (!clock_has_source(s->sysclk)) { in stm32f405_soc_realize()
111 error_setg(errp, "sysclk clock must be wired up by the board code"); in stm32f405_soc_realize()
117 * change the sysclk frequency and define different sysclk sources. in stm32f405_soc_realize()
122 clock_set_source(s->refclk, s->sysclk); in stm32f405_soc_realize()
158 qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); in stm32f405_soc_realize()
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| H A D | mps2.c | 90 Clock *sysclk; member
102 /* Main SYSCLK frequency in Hz */ in OBJECT_DECLARE_TYPE()
153 mms->sysclk = clock_new(OBJECT(machine), "SYSCLK"); in mps2_common_init()
154 clock_set_hz(mms->sysclk, SYSCLK_FRQ); in mps2_common_init()
240 qdev_connect_clock_in(armv7m, "cpuclk", mms->sysclk); in mps2_common_init()
377 qdev_connect_clock_in(DEVICE(&mms->timer[i]), "pclk", mms->sysclk); in mps2_common_init()
385 qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->sysclk); in mps2_common_init()
392 qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->sysclk); in mps2_common_init()
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| H A D | aspeed_ast27x0-ssp.c | 138 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); in aspeed_soc_ast27x0ssp_init()
169 if (!clock_has_source(s->sysclk)) { in aspeed_soc_ast27x0ssp_realize()
170 error_setg(errp, "sysclk clock must be wired up by the board code"); in aspeed_soc_ast27x0ssp_realize()
178 qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); in aspeed_soc_ast27x0ssp_realize()
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| H A D | aspeed_ast27x0-tsp.c | 138 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); in aspeed_soc_ast27x0tsp_init()
169 if (!clock_has_source(s->sysclk)) { in aspeed_soc_ast27x0tsp_realize()
170 error_setg(errp, "sysclk clock must be wired up by the board code"); in aspeed_soc_ast27x0tsp_realize()
178 qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); in aspeed_soc_ast27x0tsp_realize()
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| H A D | aspeed_ast10x0.c | 125 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); in aspeed_soc_ast1030_init()
198 if (!clock_has_source(s->sysclk)) { in aspeed_soc_ast1030_realize()
199 error_setg(errp, "sysclk clock must be wired up by the board code"); in aspeed_soc_ast1030_realize()
215 qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); in aspeed_soc_ast1030_realize()
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| H A D | musca.c | 86 Clock *sysclk; member
97 * Main SYSCLK frequency in Hz in OBJECT_DECLARE_TYPE()
368 mms->sysclk = clock_new(OBJECT(machine), "SYSCLK"); in musca_init()
369 clock_set_hz(mms->sysclk, SYSCLK_FRQ); in musca_init()
381 qdev_connect_clock_in(ssedev, "MAINCLK", mms->sysclk); in musca_init()
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| H A D | stellaris.c | 112 Clock *sysclk; member
308 clock_set_ns(s->sysclk, period_ns); in ssys_calculate_system_clock()
310 clock_propagate(s->sysclk); in ssys_calculate_system_clock()
462 /* No field for sysclk -- handled in post-load instead */
487 s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK"); in stellaris_sys_instance_init()
1096 * need its sysclk output. in stellaris_init()
1132 qdev_get_clock_out(ssys_dev, "SYSCLK")); in stellaris_init()
1163 qdev_get_clock_out(ssys_dev, "SYSCLK")); in stellaris_init()
1177 qdev_get_clock_out(ssys_dev, "SYSCLK")); in stellaris_init()
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| H A D | fby35.c | 122 s->bic_sysclk = clock_new(OBJECT(s), "SYSCLK"); in fby35_bic_init()
131 qdev_connect_clock_in(DEVICE(&s->bic), "sysclk", s->bic_sysclk); in fby35_bic_init()
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| H A D | aspeed_ast27x0-fc.c | 135 qdev_connect_clock_in(DEVICE(&s->ssp), "sysclk", s->ssp_sysclk); in ast2700fc_ssp_init()
159 qdev_connect_clock_in(DEVICE(&s->tsp), "sysclk", s->tsp_sysclk); in ast2700fc_tsp_init()
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| H A D | mps2-tz.c | 117 uint32_t sysclk_frq; /* Main SYSCLK frequency in Hz */
163 Clock *sysclk; member
820 mms->sysclk = clock_new(OBJECT(machine), "SYSCLK"); in mps2tz_common_init()
821 clock_set_hz(mms->sysclk, mmc->sysclk_frq); in mps2tz_common_init()
847 qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk); in mps2tz_common_init()
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| H A D | aspeed.c | 1632 /* Main SYSCLK frequency in Hz (200MHz) */
1639 Clock *sysclk; in aspeed_minibmc_machine_init() local
1641 sysclk = clock_new(OBJECT(machine), "SYSCLK"); in aspeed_minibmc_machine_init()
1642 clock_set_hz(sysclk, SYSCLK_FRQ); in aspeed_minibmc_machine_init()
1647 qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk); in aspeed_minibmc_machine_init()
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| /qemu/tests/qtest/ |
| H A D | stm32l4x5_rcc-test.c | 94 /* Wait until SYSCLK is stable. */ in test_init_pll()
170 * These test separately that we can enable the plls, change the sysclk, in main()
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| /qemu/include/hw/arm/ |
| H A D | nrf51_soc.h | 54 Clock *sysclk; member
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| H A D | stm32f100_soc.h | 57 Clock *sysclk; member
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| H A D | stm32f205_soc.h | 68 Clock *sysclk; member
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| H A D | stm32f405_soc.h | 73 Clock *sysclk; member
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| H A D | aspeed_soc.h | 92 Clock *sysclk; member
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| /qemu/hw/ppc/ |
| H A D | virtex_ml507.c | 70 static PowerPCCPU *ppc440_init_xilinx(const char *cpu_type, uint32_t sysclk) in ppc440_init_xilinx() argument
80 ppc_booke_timers_init(cpu, sysclk, 0/* no flags */); in ppc440_init_xilinx()
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