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/linux-6.8/Documentation/devicetree/bindings/bus/
Dqcom,ssc-block-bus.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/qcom,ssc-block-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: The AHB Bus Providing a Global View of the SSC Block on (some) qcom SoCs
10 - Michael Srba <Michael.Srba@seznam.cz>
20 The SSC (Snapdragon Sensor Core) block contains a gpio controller, i2c/spi/uart
27 - const: qcom,msm8998-ssc-block-bus
28 - const: qcom,ssc-block-bus
32 - description: SSCAON_CONFIG0 registers
[all …]
/linux-6.8/Documentation/devicetree/bindings/phy/
Dphy-rockchip-naneng-combphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,rk3568-naneng-combphy
16 - rockchip,rk3588-naneng-combphy
23 - description: reference clock
24 - description: apb clock
25 - description: pipe clock
[all …]
/linux-6.8/drivers/bus/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
37 Driver for the Broadcom Set Top Box System-on-a-chip internal bus
39 and internal bus master decoding.
42 bool "Baikal-T1 APB-bus driver"
46 Baikal-T1 AXI-APB bridge is used to access the SoC subsystem CSRs.
53 errors counter. The counter and the APB-bus operations timeout can be
57 bool "Baikal-T1 AXI-bus driver"
61 AXI3-bus is the main communication bus connecting all high-speed
62 peripheral IP-cores with RAM controller and with MIPS P5600 cores on
63 Baikal-T1 SoC. Traffic arbitration is done by means of DW AMBA 3 AXI
[all …]
/linux-6.8/drivers/phy/cadence/
Dphy-cadence-torrent.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-cadence.h>
12 #include <linux/clk-provider.h>
239 [CDNS_TORRENT_REFCLK_DRIVER] = "refclk-driver",
240 [CDNS_TORRENT_DERIVED_REFCLK] = "refclk-der",
241 [CDNS_TORRENT_RECEIVED_REFCLK] = "refclk-rec",
329 #define CDNS_TORRENT_KEY(refclk0, refclk1, link0, link1, ssc) \ argument
334 (((ssc) << SSC_SHIFT) & SSC_MASK))
459 enum cdns_torrent_ssc_mode ssc) in cdns_torrent_get_tbl_vals() argument
[all …]
/linux-6.8/drivers/iio/pressure/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
20 tristate "ROHM BM1390GLV-Z pressure sensor driver"
23 Support for the ROHM BM1390 pressure sensor. The BM1390GLV-Z
25 configurable measurement averaging and internal FIFO. The
40 will be called bmp280 and you will also get bmp280-i2c for I2C
41 and/or bmp280-spi for SPI support.
99 will be called hid-sensor-press.
113 tristate "Honeywell HSC/SSC TruStability pressure sensor series"
119 HSC and SSC pressure and temperature sensor series.
135 tristate "InvenSense ICP-101xx pressure and temperature sensor"
[all …]
/linux-6.8/drivers/gpu/drm/i915/display/
Dintel_display_core.h1 /* SPDX-License-Identifier: MIT */
61 * fills out the pipe-config with the hw state.
130 int ssc; member
134 * Bitmask of PLLs using the PCH SSC, indexed using enum intel_dpll_id.
183 * if we get a HPD irq from DP and a HPD irq from non-DP
184 * the non-DP HPD could block the workqueue on a mode config
187 * blocked behind the non-DP one.
265 * protects * intel_crtc->wm.active and
266 * crtc_state->wm.need_postvbl_update.
276 /* Top level crtc-ish functions */
[all …]
Dintel_dpll_mgr.c2 * Copyright © 2006-2016 Intel Corporation
44 * per-pipe or per-encoder dedicated PLLs, others allow the use of any PLL
123 shared_dpll[pll->index] = pll->state; in intel_atomic_duplicate_dpll_state()
131 drm_WARN_ON(s->dev, !drm_modeset_is_locked(&s->dev->mode_config.connection_mutex)); in intel_atomic_get_shared_dpll_state()
133 if (!state->dpll_set) { in intel_atomic_get_shared_dpll_state()
134 state->dpll_set = true; in intel_atomic_get_shared_dpll_state()
136 intel_atomic_duplicate_dpll_state(to_i915(s->dev), in intel_atomic_get_shared_dpll_state()
137 state->shared_dpll); in intel_atomic_get_shared_dpll_state()
140 return state->shared_dpll; in intel_atomic_get_shared_dpll_state()
144 * intel_get_shared_dpll_by_id - get a DPLL given its id
[all …]
Dintel_cx0_phy.c1 // SPDX-License-Identifier: MIT
58 * In DP-alt with pin assignment D, only PHY lane 0 is owned in intel_cx0_get_owned_lane_mask()
71 drm_WARN_ON(&i915->drm, !enabled); in assert_dc_off()
77 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_program_msgbus_timer()
81 XELPDP_PORT_MSGBUS_TIMER(encoder->port, lane), in intel_cx0_program_msgbus_timer()
98 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_phy_transaction_begin()
110 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_phy_transaction_end()
134 drm_err_once(&i915->drm, "Failed to bring PHY %c to idle.\n", phy_name(phy)); in intel_cx0_bus_reset()
152 drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for message ACK. Status: 0x%x\n", in intel_cx0_wait_for_ack()
157 drm_dbg_kms(&i915->drm, in intel_cx0_wait_for_ack()
[all …]
/linux-6.8/drivers/pci/controller/
Dpcie-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
26 #include <linux/pci-ecam.h>
37 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
158 #define BRCM_INT_PCI_MSI_MASK GENMASK(BRCM_INT_PCI_MSI_NR - 1, 0)
160 32 - BRCM_INT_PCI_MSI_LEGACY_NR)
187 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX])
188 #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA])
189 #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1])
254 /* Internal PCIe Host Controller Information.*/
[all …]
/linux-6.8/drivers/misc/cardreader/
Drtsx_usb.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
36 dev_dbg(&ucr->pusb_intf->dev, "%s: sg transfer timed out", __func__); in rtsx_usb_sg_timed_out()
37 usb_sg_cancel(&ucr->current_sg); in rtsx_usb_sg_timed_out()
46 dev_dbg(&ucr->pusb_intf->dev, "%s: xfer %u bytes, %d entries\n", in rtsx_usb_bulk_transfer_sglist()
48 ret = usb_sg_init(&ucr->current_sg, ucr->pusb_dev, pipe, 0, in rtsx_usb_bulk_transfer_sglist()
53 ucr->sg_timer.expires = jiffies + msecs_to_jiffies(timeout); in rtsx_usb_bulk_transfer_sglist()
54 add_timer(&ucr->sg_timer); in rtsx_usb_bulk_transfer_sglist()
55 usb_sg_wait(&ucr->current_sg); in rtsx_usb_bulk_transfer_sglist()
56 if (!del_timer_sync(&ucr->sg_timer)) in rtsx_usb_bulk_transfer_sglist()
[all …]
Drts5228.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Driver for Realtek PCI-Express card reader
4 * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved.
45 drive_sel = pcr->sd30_drive_sel_3v3; in rts5228_fill_driving()
48 drive_sel = pcr->sd30_drive_sel_1v8; in rts5228_fill_driving()
63 struct pci_dev *pdev = pcr->pci; in rtsx5228_fetch_vendor_settings()
74 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg); in rtsx5228_fetch_vendor_settings()
75 pcr->aspm_en = rtsx_reg_to_aspm(reg); in rtsx5228_fetch_vendor_settings()
81 pcr->rtd3_en = rtsx_reg_to_rtd3(reg); in rtsx5228_fetch_vendor_settings()
83 pcr->extra_caps |= EXTRA_CAPS_NO_MMC; in rtsx5228_fetch_vendor_settings()
[all …]
Drtsx_pcr.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Driver for Realtek PCI-Express card reader
4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
13 #include <linux/dma-mapping.h>
87 if (pcr->aspm_enabled == enable) in rtsx_comm_set_aspm()
90 if (pcr->aspm_mode == ASPM_MODE_CFG) { in rtsx_comm_set_aspm()
91 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL, in rtsx_comm_set_aspm()
93 enable ? pcr->aspm_en : 0); in rtsx_comm_set_aspm()
94 } else if (pcr->aspm_mode == ASPM_MODE_REG) { in rtsx_comm_set_aspm()
95 if (pcr->aspm_en & 0x02) in rtsx_comm_set_aspm()
[all …]
Drts5261.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Driver for Realtek PCI-Express card reader
4 * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved.
44 drive_sel = pcr->sd30_drive_sel_3v3; in rts5261_fill_driving()
47 drive_sel = pcr->sd30_drive_sel_1v8; in rts5261_fill_driving()
69 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, in rts5261_force_power_down()
75 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00); in rts5261_force_power_down()
158 struct rtsx_cr_option *option = &pcr->option; in rts5261_card_power_on()
160 if (option->ocp_en) in rts5261_card_power_on()
194 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 || in rts5261_card_power_on()
[all …]
Drts5264.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Driver for Realtek PCI-Express card reader
4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
43 drive_sel = pcr->sd30_drive_sel_3v3; in rts5264_fill_driving()
46 drive_sel = pcr->sd30_drive_sel_1v8; in rts5264_fill_driving()
66 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, in rts5264_force_power_down()
72 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00); in rts5264_force_power_down()
78 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x01); in rts5264_force_power_down()
79 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, in rts5264_force_power_down()
155 struct rtsx_cr_option *option = &pcr->option; in rts5264_card_power_on()
[all …]
/linux-6.8/drivers/gpu/drm/bridge/
Dparade-ps8622.c1 // SPDX-License-Identifier: GPL-2.0-only
68 struct i2c_adapter *adap = client->adapter; in ps8622_set()
72 msg.addr = client->addr + page; in ps8622_set()
80 client->addr + page, reg, val, ret); in ps8622_set()
86 struct i2c_client *cl = ps8622->client; in ps8622_send_config()
137 /* [7:5] DCO_FTRNG=+-40% */ in ps8622_send_config()
147 /* Gitune=-37% */ in ps8622_send_config()
167 /* [7:6] Right-bar GPIO output strength is 8mA */ in ps8622_send_config()
179 err = ps8622_set(cl, 0x01, 0x02, 0x80 | ps8622->max_lane_count); in ps8622_send_config()
184 err = ps8622_set(cl, 0x01, 0x21, 0x80 | ps8622->lane_count); in ps8622_send_config()
[all …]
/linux-6.8/drivers/gpu/drm/msm/dsi/phy/
Ddsi_phy_14nm.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
17 * DSI PLL 14nm - clock diagram (eg: DSI0):
22 * +----+ | +----+
23 * dsi0vco_clk ---| n1 |--o--| /8 |-- dsi0pllbyte
24 * +----+ | +----+
26 * | +----+ |
27 * o---| /2 |--o--|\
28 * | +----+ | \ +----+
29 * | | |--| n2 |-- dsi0pll
[all …]
Ddsi_phy_7nm.c2 * SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
15 * DSI PLL 7nm - clock diagram (eg: DSI0): TODO: updated CPHY diagram
20 * +---------+ | +----------+ | +----+
21 * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk
22 * +---------+ | +----------+ | +----+
26 * | | +----+ | |\ dsi0_pclk_mux
27 * | |--| /2 |--o--| \ |
28 * | | +----+ | \ | +---------+
29 …* | --------------| |--o--| div_7_4 |-- dsi0_phy_pll_…
[all …]
Ddsi_phy_10nm.c2 * SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
15 * DSI PLL 10nm - clock diagram (eg: DSI0):
20 * +---------+ | +----------+ | +----+
21 * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk
22 * +---------+ | +----------+ | +----+
26 * | | +----+ | |\ dsi0_pclk_mux
27 * | |--| /2 |--o--| \ |
28 * | | +----+ | \ | +---------+
29 …* | --------------| |--o--| div_7_4 |-- dsi0_phy_pll_…
[all …]
/linux-6.8/drivers/spi/
Dspi-lantiq-ssc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011-2015 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
4 * Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de>
142 #define LTQ_SPI_RXCNT_TODO_M 0xFFFF /* Recevie to-do value */
191 return __raw_readl(spi->regbase + reg); in lantiq_ssc_readl()
197 __raw_writel(val, spi->regbase + reg); in lantiq_ssc_writel()
203 u32 val = __raw_readl(spi->regbase + reg); in lantiq_ssc_maskl()
207 __raw_writel(val, spi->regbase + reg); in lantiq_ssc_maskl()
212 const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg; in tx_fifo_level()
215 return (fstat >> LTQ_SPI_FSTAT_TXFFL_S) & hwcfg->fifo_size_mask; in tx_fifo_level()
[all …]
/linux-6.8/drivers/phy/
Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
11 * The first PLL clock macro is used for internal reference clock. The second
15 * required if internal clock is enabled.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
[all …]
/linux-6.8/drivers/i2c/busses/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
16 for Cypress CCGx Type-C controller. Individual bus drivers
25 controller is part of the 7101 device, which is an ACPI-compliant
29 will be called i2c-ali1535.
37 controller is part of the 7101 device, which is an ACPI-compliant
41 will be called i2c-ali1563.
51 will be called i2c-ali15x3.
63 will be called i2c-amd756.
70 S4882 motherboard. On this 4-CPU board, the SMBus is multiplexed
76 will be called i2c-amd756-s4882.
[all …]
/linux-6.8/arch/x86/include/asm/
Dperf_event_p4.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 * perf-MSRs are not shared and every thread has its
17 * own perf-MSRs set)
21 #define ARCH_P4_MAX_ESCR (ARCH_P4_TOTAL_ESCR - ARCH_P4_RESERVED_ESCR)
25 #define ARCH_P4_CNTRVAL_MASK ((1ULL << ARCH_P4_CNTRVAL_BITS) - 1)
26 #define ARCH_P4_UNFLAGGED_BIT ((1ULL) << (ARCH_P4_CNTRVAL_BITS - 1))
207 * non-HT machines (on HT machines we count TS events in p4_default_cccr_conf()
304 * processor builds (family 0FH, models 01H-02H). These MSRs
613 P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_COMPLETE, SSC, 1),
822 * Notes on internal configuration of ESCR+CCCR tuples
[all …]
/linux-6.8/drivers/staging/rts5208/
Drtsx_chip.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for Realtek PCI-Express card reader
5 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
40 for (i = 0; i <= chip->max_lun; i++) { in rtsx_enable_card_int()
41 if (chip->lun2card[i] & XD_CARD) in rtsx_enable_card_int()
43 if (chip->lun2card[i] & SD_CARD) in rtsx_enable_card_int()
45 if (chip->lun2card[i] & MS_CARD) in rtsx_enable_card_int()
48 if (chip->hw_bypass_sd) in rtsx_enable_card_int()
64 for (i = 0; i <= chip->max_lun; i++) { in rtsx_enable_bus_int()
66 i, chip->lun2card[i]); in rtsx_enable_bus_int()
[all …]
/linux-6.8/drivers/scsi/isci/
Dhost.c7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
100 * NORMALIZE_PUT_POINTER() -
110 * NORMALIZE_EVENT_POINTER() -
122 * NORMALIZE_GET_POINTER() -
131 * NORMALIZE_GET_POINTER_CYCLE_BIT() -
137 ((SMU_CQGR_CYCLE_BIT & (x)) << (31 - SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT))
140 * COMPLETION_QUEUE_CYCLE_BIT() -
152 sm->initial_state_id = initial_state; in sci_init_sm()
[all …]
/linux-6.8/drivers/gpu/drm/amd/include/
Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,…
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
427 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
433 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
440 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
460 …icable to memory clock change, when set, the table will skip predefined internal memory parameter …
[all …]

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