Lines Matching +full:ssc +full:- +full:internal
1 // SPDX-License-Identifier: MIT
58 * In DP-alt with pin assignment D, only PHY lane 0 is owned in intel_cx0_get_owned_lane_mask()
71 drm_WARN_ON(&i915->drm, !enabled); in assert_dc_off()
77 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_program_msgbus_timer()
81 XELPDP_PORT_MSGBUS_TIMER(encoder->port, lane), in intel_cx0_program_msgbus_timer()
98 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_phy_transaction_begin()
110 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_phy_transaction_end()
134 drm_err_once(&i915->drm, "Failed to bring PHY %c to idle.\n", phy_name(phy)); in intel_cx0_bus_reset()
152 drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for message ACK. Status: 0x%x\n", in intel_cx0_wait_for_ack()
157 drm_dbg_kms(&i915->drm, in intel_cx0_wait_for_ack()
162 return -ETIMEDOUT; in intel_cx0_wait_for_ack()
166 drm_dbg_kms(&i915->drm, "PHY %c Error occurred during %s command. Status: 0x%x\n", phy_name(phy), in intel_cx0_wait_for_ack()
169 return -EINVAL; in intel_cx0_wait_for_ack()
173 drm_dbg_kms(&i915->drm, "PHY %c Not a %s response. MSGBUS Status: 0x%x.\n", phy_name(phy), in intel_cx0_wait_for_ack()
176 return -EINVAL; in intel_cx0_wait_for_ack()
192 drm_dbg_kms(&i915->drm, in __intel_cx0_read_once()
195 return -ETIMEDOUT; in __intel_cx0_read_once()
235 drm_err_once(&i915->drm, "PHY %c Read %04x failed after %d retries.\n", in __intel_cx0_read()
259 drm_dbg_kms(&i915->drm, in __intel_cx0_write_once()
262 return -ETIMEDOUT; in __intel_cx0_write_once()
275 drm_dbg_kms(&i915->drm, in __intel_cx0_write_once()
278 return -ETIMEDOUT; in __intel_cx0_write_once()
287 drm_dbg_kms(&i915->drm, in __intel_cx0_write_once()
290 return -EINVAL; in __intel_cx0_write_once()
321 drm_err_once(&i915->drm, in __intel_cx0_write()
388 (crtc_state->port_clock == 540000 || in intel_c10_get_tx_vboost_lvl()
389 crtc_state->port_clock == 810000)) in intel_c10_get_tx_vboost_lvl()
402 (crtc_state->port_clock == 540000 || in intel_c10_get_tx_term_ctl()
403 crtc_state->port_clock == 810000)) in intel_c10_get_tx_term_ctl()
415 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_phy_set_signal_levels()
417 enum phy phy = intel_port_to_phy(i915, encoder->port); in intel_cx0_phy_set_signal_levels()
430 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in intel_cx0_phy_set_signal_levels()
431 if (drm_WARN_ON_ONCE(&i915->drm, !trans)) { in intel_cx0_phy_set_signal_levels()
437 intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_CONTROL(1), in intel_cx0_phy_set_signal_levels()
439 intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_CMN(3), in intel_cx0_phy_set_signal_levels()
443 intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_TX(1), in intel_cx0_phy_set_signal_levels()
449 for (ln = 0; ln < crtc_state->lane_count; ln++) { in intel_cx0_phy_set_signal_levels()
458 intel_cx0_rmw(i915, encoder->port, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 0), in intel_cx0_phy_set_signal_levels()
460 C10_PHY_OVRD_LEVEL(trans->entries[level].snps.pre_cursor), in intel_cx0_phy_set_signal_levels()
462 intel_cx0_rmw(i915, encoder->port, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 1), in intel_cx0_phy_set_signal_levels()
464 C10_PHY_OVRD_LEVEL(trans->entries[level].snps.vswing), in intel_cx0_phy_set_signal_levels()
466 intel_cx0_rmw(i915, encoder->port, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 2), in intel_cx0_phy_set_signal_levels()
468 C10_PHY_OVRD_LEVEL(trans->entries[level].snps.post_cursor), in intel_cx0_phy_set_signal_levels()
473 intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_OVRD, in intel_cx0_phy_set_signal_levels()
478 intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_CONTROL(1), in intel_cx0_phy_set_signal_levels()
486 * Note: The tables below are with SSC. In non-ssc
1786 if (clock == tables[i]->clock) in intel_c10_phy_check_hdmi_link_rate()
1806 MISSING_CASE(encoder->type); in intel_c10pll_tables_get()
1813 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_c10pll_update_pll()
1814 struct intel_cx0pll_state *pll_state = &crtc_state->cx0pll_state; in intel_c10pll_update_pll()
1821 pll_state->ssc_enabled = in intel_c10pll_update_pll()
1822 (intel_dp->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5); in intel_c10pll_update_pll()
1826 if (pll_state->ssc_enabled) in intel_c10pll_update_pll()
1829 drm_WARN_ON(&i915->drm, ARRAY_SIZE(pll_state->c10.pll) < 9); in intel_c10pll_update_pll()
1831 pll_state->c10.pll[i] = 0; in intel_c10pll_update_pll()
1842 return -EINVAL; in intel_c10pll_calc_state()
1845 if (crtc_state->port_clock == tables[i]->clock) { in intel_c10pll_calc_state()
1846 crtc_state->cx0pll_state.c10 = *tables[i]; in intel_c10pll_calc_state()
1853 return -EINVAL; in intel_c10pll_calc_state()
1859 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_c10pll_readout_hw_state()
1868 * to do this to read PHY internal registers from MsgBus. in intel_c10pll_readout_hw_state()
1870 intel_cx0_rmw(i915, encoder->port, lane, PHY_C10_VDR_CONTROL(1), in intel_c10pll_readout_hw_state()
1874 for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++) in intel_c10pll_readout_hw_state()
1875 pll_state->pll[i] = intel_cx0_read(i915, encoder->port, lane, in intel_c10pll_readout_hw_state()
1878 pll_state->cmn = intel_cx0_read(i915, encoder->port, lane, PHY_C10_VDR_CMN(0)); in intel_c10pll_readout_hw_state()
1879 pll_state->tx = intel_cx0_read(i915, encoder->port, lane, PHY_C10_VDR_TX(0)); in intel_c10pll_readout_hw_state()
1888 const struct intel_c10pll_state *pll_state = &crtc_state->cx0pll_state.c10; in intel_c10_pll_program()
1891 intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1), in intel_c10_pll_program()
1896 intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CUSTOM_WIDTH, in intel_c10_pll_program()
1899 intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1), in intel_c10_pll_program()
1904 for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++) in intel_c10_pll_program()
1905 intel_cx0_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C10_VDR_PLL(i), in intel_c10_pll_program()
1906 pll_state->pll[i], in intel_c10_pll_program()
1909 …intel_cx0_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C10_VDR_CMN(0), pll_state->cmn, MB_WRITE… in intel_c10_pll_program()
1910 …intel_cx0_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C10_VDR_TX(0), pll_state->tx, MB_WRITE_C… in intel_c10_pll_program()
1912 intel_cx0_rmw(i915, encoder->port, INTEL_CX0_LANE0, PHY_C10_VDR_CONTROL(1), in intel_c10_pll_program()
1925 fracen = hw_state->pll[0] & C10_PLL0_FRACEN; in intel_c10pll_dump_hw_state()
1926 drm_dbg_kms(&i915->drm, "c10pll_hw_state: fracen: %s, ", in intel_c10pll_dump_hw_state()
1930 frac_quot = hw_state->pll[12] << 8 | hw_state->pll[11]; in intel_c10pll_dump_hw_state()
1931 frac_rem = hw_state->pll[14] << 8 | hw_state->pll[13]; in intel_c10pll_dump_hw_state()
1932 frac_den = hw_state->pll[10] << 8 | hw_state->pll[9]; in intel_c10pll_dump_hw_state()
1933 drm_dbg_kms(&i915->drm, "quot: %u, rem: %u, den: %u,\n", in intel_c10pll_dump_hw_state()
1937 multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, hw_state->pll[3]) << 8 | in intel_c10pll_dump_hw_state()
1938 hw_state->pll[2]) / 2 + 16; in intel_c10pll_dump_hw_state()
1939 tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, hw_state->pll[15]); in intel_c10pll_dump_hw_state()
1940 drm_dbg_kms(&i915->drm, in intel_c10pll_dump_hw_state()
1943 drm_dbg_kms(&i915->drm, "c10pll_rawhw_state:"); in intel_c10pll_dump_hw_state()
1944 drm_dbg_kms(&i915->drm, "tx: 0x%x, cmn: 0x%x\n", hw_state->tx, hw_state->cmn); in intel_c10pll_dump_hw_state()
1946 BUILD_BUG_ON(ARRAY_SIZE(hw_state->pll) % 4); in intel_c10pll_dump_hw_state()
1947 for (i = 0; i < ARRAY_SIZE(hw_state->pll); i = i + 4) in intel_c10pll_dump_hw_state()
1948 drm_dbg_kms(&i915->drm, "pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x\n", in intel_c10pll_dump_hw_state()
1949 i, hw_state->pll[i], i + 1, hw_state->pll[i + 1], in intel_c10pll_dump_hw_state()
1950 i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]); in intel_c10pll_dump_hw_state()
1967 return -EINVAL; in intel_c20_compute_hdmi_tmds_pll()
1991 pll_state->clock = pixel_clock; in intel_c20_compute_hdmi_tmds_pll()
1992 pll_state->tx[0] = 0xbe88; in intel_c20_compute_hdmi_tmds_pll()
1993 pll_state->tx[1] = 0x9800; in intel_c20_compute_hdmi_tmds_pll()
1994 pll_state->tx[2] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
1995 pll_state->cmn[0] = 0x0500; in intel_c20_compute_hdmi_tmds_pll()
1996 pll_state->cmn[1] = 0x0005; in intel_c20_compute_hdmi_tmds_pll()
1997 pll_state->cmn[2] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
1998 pll_state->cmn[3] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
1999 pll_state->mpllb[0] = (MPLL_TX_CLK_DIV(mpll_tx_clk_div) | in intel_c20_compute_hdmi_tmds_pll()
2001 pll_state->mpllb[1] = (CAL_DAC_CODE(CAL_DAC_CODE_31) | in intel_c20_compute_hdmi_tmds_pll()
2004 pll_state->mpllb[2] = (MPLLB_ANA_FREQ_VCO(mpllb_ana_freq_vco) | in intel_c20_compute_hdmi_tmds_pll()
2007 pll_state->mpllb[3] = (V2I(V2I_2) | in intel_c20_compute_hdmi_tmds_pll()
2010 pll_state->mpllb[4] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
2011 pll_state->mpllb[5] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
2012 pll_state->mpllb[6] = (C20_MPLLB_FRACEN | SSC_UP_SPREAD); in intel_c20_compute_hdmi_tmds_pll()
2013 pll_state->mpllb[7] = MPLL_FRACN_DEN; in intel_c20_compute_hdmi_tmds_pll()
2014 pll_state->mpllb[8] = mpll_fracn_quot; in intel_c20_compute_hdmi_tmds_pll()
2015 pll_state->mpllb[9] = mpll_fracn_rem; in intel_c20_compute_hdmi_tmds_pll()
2016 pll_state->mpllb[10] = HDMI_DIV(HDMI_DIV_1); in intel_c20_compute_hdmi_tmds_pll()
2027 if (clock == tables[i]->clock) in intel_c20_phy_check_hdmi_link_rate()
2041 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); in intel_cx0_phy_check_hdmi_link_rate()
2057 MISSING_CASE(encoder->type); in intel_c20_pll_tables_get()
2069 if (intel_c20_compute_hdmi_tmds_pll(crtc_state->port_clock, in intel_c20pll_calc_state()
2070 &crtc_state->cx0pll_state.c20) == 0) in intel_c20pll_calc_state()
2076 return -EINVAL; in intel_c20pll_calc_state()
2079 if (crtc_state->port_clock == tables[i]->clock) { in intel_c20pll_calc_state()
2080 crtc_state->cx0pll_state.c20 = *tables[i]; in intel_c20pll_calc_state()
2085 return -EINVAL; in intel_c20pll_calc_state()
2091 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0pll_calc_state()
2092 enum phy phy = intel_port_to_phy(i915, encoder->port); in intel_cx0pll_calc_state()
2111 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_c20pll_readout_hw_state()
2119 …cntx = intel_cx0_read(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_… in intel_c20pll_readout_hw_state()
2122 for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) { in intel_c20pll_readout_hw_state()
2124 pll_state->tx[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, in intel_c20pll_readout_hw_state()
2127 pll_state->tx[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, in intel_c20pll_readout_hw_state()
2132 for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) { in intel_c20pll_readout_hw_state()
2134 pll_state->cmn[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, in intel_c20pll_readout_hw_state()
2137 pll_state->cmn[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, in intel_c20pll_readout_hw_state()
2141 if (pll_state->tx[0] & C20_PHY_USE_MPLLB) { in intel_c20pll_readout_hw_state()
2143 for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) { in intel_c20pll_readout_hw_state()
2145 pll_state->mpllb[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, in intel_c20pll_readout_hw_state()
2148 pll_state->mpllb[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, in intel_c20pll_readout_hw_state()
2153 for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) { in intel_c20pll_readout_hw_state()
2155 pll_state->mplla[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, in intel_c20pll_readout_hw_state()
2158 pll_state->mplla[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, in intel_c20pll_readout_hw_state()
2171 drm_dbg_kms(&i915->drm, "c20pll_hw_state:\n"); in intel_c20pll_dump_hw_state()
2172 drm_dbg_kms(&i915->drm, "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n", in intel_c20pll_dump_hw_state()
2173 hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]); in intel_c20pll_dump_hw_state()
2174 drm_dbg_kms(&i915->drm, "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n", in intel_c20pll_dump_hw_state()
2175 hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]); in intel_c20pll_dump_hw_state()
2177 if (intel_c20_use_mplla(hw_state->clock)) { in intel_c20pll_dump_hw_state()
2178 for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++) in intel_c20pll_dump_hw_state()
2179 drm_dbg_kms(&i915->drm, "mplla[%d] = 0x%.4x\n", i, hw_state->mplla[i]); in intel_c20pll_dump_hw_state()
2181 for (i = 0; i < ARRAY_SIZE(hw_state->mpllb); i++) in intel_c20pll_dump_hw_state()
2182 drm_dbg_kms(&i915->drm, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]); in intel_c20pll_dump_hw_state()
2269 /* TODO: optimize re-calibration in legacy mode */ in intel_c20_protocol_switch_valid()
2287 const struct intel_c20pll_state *pll_state = &crtc_state->cx0pll_state.c20; in intel_c20_pll_program()
2289 int lane = crtc_state->lane_count > 2 ? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0; in intel_c20_pll_program()
2290 u32 clock = crtc_state->port_clock; in intel_c20_pll_program()
2298 …cntx = intel_cx0_read(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & BIT(… in intel_c20_pll_program()
2307 …intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(… in intel_c20_pll_program()
2313 for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) { in intel_c20_pll_program()
2315 …intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_A_TX_CNTX_CFG(i), pll_state->tx… in intel_c20_pll_program()
2317 …intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_B_TX_CNTX_CFG(i), pll_state->tx… in intel_c20_pll_program()
2321 for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) { in intel_c20_pll_program()
2323 …intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_A_CMN_CNTX_CFG(i), pll_state->c… in intel_c20_pll_program()
2325 …intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_B_CMN_CNTX_CFG(i), pll_state->c… in intel_c20_pll_program()
2330 for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) { in intel_c20_pll_program()
2332 intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, in intel_c20_pll_program()
2334 pll_state->mplla[i]); in intel_c20_pll_program()
2336 intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, in intel_c20_pll_program()
2338 pll_state->mplla[i]); in intel_c20_pll_program()
2341 for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) { in intel_c20_pll_program()
2343 intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, in intel_c20_pll_program()
2345 pll_state->mpllb[i]); in intel_c20_pll_program()
2347 intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, in intel_c20_pll_program()
2349 pll_state->mpllb[i]); in intel_c20_pll_program()
2354 intel_cx0_rmw(i915, encoder->port, lane, PHY_C20_VDR_CUSTOM_WIDTH, in intel_c20_pll_program()
2361 intel_cx0_rmw(i915, encoder->port, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE, in intel_c20_pll_program()
2366 intel_cx0_rmw(i915, encoder->port, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE, in intel_c20_pll_program()
2371 intel_cx0_write(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE, in intel_c20_pll_program()
2380 intel_cx0_rmw(i915, encoder->port, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE, in intel_c20_pll_program()
2391 if (pll_state->pll[0] & C10_PLL0_FRACEN) { in intel_c10pll_calc_port_clock()
2392 frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11]; in intel_c10pll_calc_port_clock()
2393 frac_rem = pll_state->pll[14] << 8 | pll_state->pll[13]; in intel_c10pll_calc_port_clock()
2394 frac_den = pll_state->pll[10] << 8 | pll_state->pll[9]; in intel_c10pll_calc_port_clock()
2397 multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, pll_state->pll[3]) << 8 | in intel_c10pll_calc_port_clock()
2398 pll_state->pll[2]) / 2 + 16; in intel_c10pll_calc_port_clock()
2400 tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state->pll[15]); in intel_c10pll_calc_port_clock()
2401 hdmi_div = REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state->pll[15]); in intel_c10pll_calc_port_clock()
2421 unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state->tx[0]); in intel_c20pll_calc_port_clock()
2423 if (pll_state->tx[0] & C20_PHY_USE_MPLLB) { in intel_c20pll_calc_port_clock()
2425 frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state->mpllb[6]); in intel_c20pll_calc_port_clock()
2426 frac_quot = pll_state->mpllb[8]; in intel_c20pll_calc_port_clock()
2427 frac_rem = pll_state->mpllb[9]; in intel_c20pll_calc_port_clock()
2428 frac_den = pll_state->mpllb[7]; in intel_c20pll_calc_port_clock()
2429 multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mpllb[0]); in intel_c20pll_calc_port_clock()
2430 tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]); in intel_c20pll_calc_port_clock()
2431 ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mpllb[6]); in intel_c20pll_calc_port_clock()
2435 frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state->mplla[6]); in intel_c20pll_calc_port_clock()
2436 frac_quot = pll_state->mplla[8]; in intel_c20pll_calc_port_clock()
2437 frac_rem = pll_state->mplla[9]; in intel_c20pll_calc_port_clock()
2438 frac_den = pll_state->mplla[7]; in intel_c20pll_calc_port_clock()
2439 multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mplla[0]); in intel_c20pll_calc_port_clock()
2440 tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK, pll_state->mplla[1]); in intel_c20pll_calc_port_clock()
2441 ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mplla[6]); in intel_c20pll_calc_port_clock()
2442 fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN, pll_state->mplla[0]); in intel_c20pll_calc_port_clock()
2451 vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(ref, (multiplier << (17 - 2)) + frac) >> 17, 10); in intel_c20pll_calc_port_clock()
2460 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_program_port_clock_ctl()
2463 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(encoder->port), XELPDP_PORT_REVERSAL, in intel_program_port_clock_ctl()
2472 is_hdmi_frl(crtc_state->port_clock)) in intel_program_port_clock_ctl()
2479 if (crtc_state->port_clock == 1000000 || crtc_state->port_clock == 2000000) in intel_program_port_clock_ctl()
2480 val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLA : 0; in intel_program_port_clock_ctl()
2482 val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0; in intel_program_port_clock_ctl()
2484 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), in intel_program_port_clock_ctl()
2528 drm_dbg_kms(&i915->drm, in intel_cx0_powerdown_change_sequence()
2542 drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n", in intel_cx0_powerdown_change_sequence()
2584 enum port port = encoder->port; in intel_cx0_phy_lane_reset()
2600 drm_warn(&i915->drm, "PHY %c failed to bring out of SOC reset after %dus.\n", in intel_cx0_phy_lane_reset()
2609 drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n", in intel_cx0_phy_lane_reset()
2620 drm_warn(&i915->drm, "PHY %c failed to request refclk after %dus.\n", in intel_cx0_phy_lane_reset()
2631 drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dms.\n", in intel_cx0_phy_lane_reset()
2643 enum port port = encoder->port; in intel_cx0_program_phy_lane()
2706 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0pll_enable()
2707 enum phy phy = intel_port_to_phy(i915, encoder->port); in intel_cx0pll_enable()
2709 bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; in intel_cx0pll_enable()
2716 * clock muxes, gating and SSC in intel_cx0pll_enable()
2727 intel_cx0_powerdown_change_sequence(i915, encoder->port, INTEL_CX0_BOTH_LANES, in intel_cx0pll_enable()
2736 /* 5. Program PHY internal PLL internal registers. */ in intel_cx0pll_enable()
2746 intel_cx0_program_phy_lane(i915, encoder, crtc_state->lane_count, lane_reversal); in intel_cx0pll_enable()
2749 * 7. Follow the Display Voltage Frequency Switching - Sequence in intel_cx0pll_enable()
2757 intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), in intel_cx0pll_enable()
2758 crtc_state->port_clock); in intel_cx0pll_enable()
2764 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), in intel_cx0pll_enable()
2769 if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), in intel_cx0pll_enable()
2773 drm_warn(&i915->drm, "Port %c PLL not locked after %dus.\n", in intel_cx0pll_enable()
2781 /* TODO: enable TBT-ALT mode */ in intel_cx0pll_enable()
2787 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_mtl_tbt_calc_port_clock()
2789 u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port)); in intel_mtl_tbt_calc_port_clock()
2793 drm_WARN_ON(&i915->drm, !(val & XELPDP_FORWARD_CLOCK_UNGATE)); in intel_mtl_tbt_calc_port_clock()
2794 drm_WARN_ON(&i915->drm, !(val & XELPDP_TBT_CLOCK_REQUEST)); in intel_mtl_tbt_calc_port_clock()
2795 drm_WARN_ON(&i915->drm, !(val & XELPDP_TBT_CLOCK_ACK)); in intel_mtl_tbt_calc_port_clock()
2832 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_mtl_tbt_pll_enable()
2833 enum phy phy = intel_port_to_phy(i915, encoder->port); in intel_mtl_tbt_pll_enable()
2838 * clock muxes, gating and SSC in intel_mtl_tbt_pll_enable()
2840 val |= XELPDP_DDI_CLOCK_SELECT(intel_mtl_tbt_clock_select(i915, crtc_state->port_clock)); in intel_mtl_tbt_pll_enable()
2842 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), in intel_mtl_tbt_pll_enable()
2846 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port)); in intel_mtl_tbt_pll_enable()
2849 * 3. Follow the Display Voltage Frequency Switching - Sequence in intel_mtl_tbt_pll_enable()
2857 intel_de_write(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), val); in intel_mtl_tbt_pll_enable()
2860 if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), in intel_mtl_tbt_pll_enable()
2864 drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not locked after 100us.\n", in intel_mtl_tbt_pll_enable()
2865 encoder->base.base.id, encoder->base.name, phy_name(phy)); in intel_mtl_tbt_pll_enable()
2876 intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), in intel_mtl_tbt_pll_enable()
2877 crtc_state->port_clock); in intel_mtl_tbt_pll_enable()
2893 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0pll_disable()
2894 enum phy phy = intel_port_to_phy(i915, encoder->port); in intel_cx0pll_disable()
2899 intel_cx0_powerdown_change_sequence(i915, encoder->port, INTEL_CX0_BOTH_LANES, in intel_cx0pll_disable()
2912 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), in intel_cx0pll_disable()
2917 intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 0); in intel_cx0pll_disable()
2922 if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), in intel_cx0pll_disable()
2926 drm_warn(&i915->drm, "Port %c PLL not unlocked after %dus.\n", in intel_cx0pll_disable()
2935 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), in intel_cx0pll_disable()
2937 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), in intel_cx0pll_disable()
2945 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_mtl_tbt_pll_disable()
2946 enum phy phy = intel_port_to_phy(i915, encoder->port); in intel_mtl_tbt_pll_disable()
2956 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), in intel_mtl_tbt_pll_disable()
2960 if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), in intel_mtl_tbt_pll_disable()
2962 drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not unlocked after 10us.\n", in intel_mtl_tbt_pll_disable()
2963 encoder->base.base.id, encoder->base.name, phy_name(phy)); in intel_mtl_tbt_pll_disable()
2973 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), in intel_mtl_tbt_pll_disable()
2978 intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 0); in intel_mtl_tbt_pll_disable()
2995 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_mtl_port_pll_type()
3000 u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port)); in intel_mtl_port_pll_type()
3015 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_c10pll_state_verify()
3016 const struct intel_c10pll_state *mpllb_sw_state = &state->cx0pll_state.c10; in intel_c10pll_state_verify()
3019 for (i = 0; i < ARRAY_SIZE(mpllb_sw_state->pll); i++) { in intel_c10pll_state_verify()
3020 u8 expected = mpllb_sw_state->pll[i]; in intel_c10pll_state_verify()
3022 I915_STATE_WARN(i915, mpllb_hw_state->pll[i] != expected, in intel_c10pll_state_verify()
3024 crtc->base.base.id, crtc->base.name, i, in intel_c10pll_state_verify()
3025 expected, mpllb_hw_state->pll[i]); in intel_c10pll_state_verify()
3028 I915_STATE_WARN(i915, mpllb_hw_state->tx != mpllb_sw_state->tx, in intel_c10pll_state_verify()
3030 crtc->base.base.id, crtc->base.name, in intel_c10pll_state_verify()
3031 mpllb_sw_state->tx, mpllb_hw_state->tx); in intel_c10pll_state_verify()
3033 I915_STATE_WARN(i915, mpllb_hw_state->cmn != mpllb_sw_state->cmn, in intel_c10pll_state_verify()
3035 crtc->base.base.id, crtc->base.name, in intel_c10pll_state_verify()
3036 mpllb_sw_state->cmn, mpllb_hw_state->cmn); in intel_c10pll_state_verify()
3042 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0pll_readout_hw_state()
3043 enum phy phy = intel_port_to_phy(i915, encoder->port); in intel_cx0pll_readout_hw_state()
3046 intel_c10pll_readout_hw_state(encoder, &pll_state->c10); in intel_cx0pll_readout_hw_state()
3048 intel_c20pll_readout_hw_state(encoder, &pll_state->c20); in intel_cx0pll_readout_hw_state()
3054 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0pll_calc_port_clock()
3055 enum phy phy = intel_port_to_phy(i915, encoder->port); in intel_cx0pll_calc_port_clock()
3058 return intel_c10pll_calc_port_clock(encoder, &pll_state->c10); in intel_cx0pll_calc_port_clock()
3060 return intel_c20pll_calc_port_clock(encoder, &pll_state->c20); in intel_cx0pll_calc_port_clock()
3068 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_c20pll_state_verify()
3069 const struct intel_c20pll_state *mpll_sw_state = &state->cx0pll_state.c20; in intel_c20pll_state_verify()
3070 bool sw_use_mpllb = mpll_sw_state->tx[0] & C20_PHY_USE_MPLLB; in intel_c20pll_state_verify()
3071 bool hw_use_mpllb = mpll_hw_state->tx[0] & C20_PHY_USE_MPLLB; in intel_c20pll_state_verify()
3076 crtc->base.base.id, crtc->base.name, in intel_c20pll_state_verify()
3080 for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mpllb); i++) { in intel_c20pll_state_verify()
3081 I915_STATE_WARN(i915, mpll_hw_state->mpllb[i] != mpll_sw_state->mpllb[i], in intel_c20pll_state_verify()
3083 crtc->base.base.id, crtc->base.name, i, in intel_c20pll_state_verify()
3084 mpll_sw_state->mpllb[i], mpll_hw_state->mpllb[i]); in intel_c20pll_state_verify()
3087 for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mplla); i++) { in intel_c20pll_state_verify()
3088 I915_STATE_WARN(i915, mpll_hw_state->mplla[i] != mpll_sw_state->mplla[i], in intel_c20pll_state_verify()
3090 crtc->base.base.id, crtc->base.name, i, in intel_c20pll_state_verify()
3091 mpll_sw_state->mplla[i], mpll_hw_state->mplla[i]); in intel_c20pll_state_verify()
3095 for (i = 0; i < ARRAY_SIZE(mpll_sw_state->tx); i++) { in intel_c20pll_state_verify()
3096 I915_STATE_WARN(i915, mpll_hw_state->tx[i] != mpll_sw_state->tx[i], in intel_c20pll_state_verify()
3098 crtc->base.base.id, crtc->base.name, i, in intel_c20pll_state_verify()
3099 mpll_sw_state->tx[i], mpll_hw_state->tx[i]); in intel_c20pll_state_verify()
3102 for (i = 0; i < ARRAY_SIZE(mpll_sw_state->cmn); i++) { in intel_c20pll_state_verify()
3103 I915_STATE_WARN(i915, mpll_hw_state->cmn[i] != mpll_sw_state->cmn[i], in intel_c20pll_state_verify()
3105 crtc->base.base.id, crtc->base.name, i, in intel_c20pll_state_verify()
3106 mpll_sw_state->cmn[i], mpll_hw_state->cmn[i]); in intel_c20pll_state_verify()
3113 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_cx0pll_state_verify()
3123 if (!new_crtc_state->hw.active) in intel_cx0pll_state_verify()
3132 phy = intel_port_to_phy(i915, encoder->port); in intel_cx0pll_state_verify()