1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DISPLAY_CORE_H__ 7 #define __INTEL_DISPLAY_CORE_H__ 8 9 #include <linux/list.h> 10 #include <linux/llist.h> 11 #include <linux/mutex.h> 12 #include <linux/types.h> 13 #include <linux/wait.h> 14 #include <linux/workqueue.h> 15 16 #include <drm/drm_connector.h> 17 #include <drm/drm_modeset_lock.h> 18 19 #include "intel_cdclk.h" 20 #include "intel_display_device.h" 21 #include "intel_display_limits.h" 22 #include "intel_display_params.h" 23 #include "intel_display_power.h" 24 #include "intel_dpll_mgr.h" 25 #include "intel_fbc.h" 26 #include "intel_global_state.h" 27 #include "intel_gmbus.h" 28 #include "intel_opregion.h" 29 #include "intel_wm_types.h" 30 31 struct drm_i915_private; 32 struct drm_property; 33 struct drm_property_blob; 34 struct i915_audio_component; 35 struct i915_hdcp_arbiter; 36 struct intel_atomic_state; 37 struct intel_audio_funcs; 38 struct intel_cdclk_funcs; 39 struct intel_cdclk_vals; 40 struct intel_color_funcs; 41 struct intel_crtc; 42 struct intel_crtc_state; 43 struct intel_dmc; 44 struct intel_dpll_funcs; 45 struct intel_dpll_mgr; 46 struct intel_fbdev; 47 struct intel_fdi_funcs; 48 struct intel_hotplug_funcs; 49 struct intel_initial_plane_config; 50 struct intel_overlay; 51 52 /* Amount of SAGV/QGV points, BSpec precisely defines this */ 53 #define I915_NUM_QGV_POINTS 8 54 55 /* Amount of PSF GV points, BSpec precisely defines this */ 56 #define I915_NUM_PSF_GV_POINTS 3 57 58 struct intel_display_funcs { 59 /* 60 * Returns the active state of the crtc, and if the crtc is active, 61 * fills out the pipe-config with the hw state. 62 */ 63 bool (*get_pipe_config)(struct intel_crtc *, 64 struct intel_crtc_state *); 65 void (*get_initial_plane_config)(struct intel_crtc *, 66 struct intel_initial_plane_config *); 67 void (*crtc_enable)(struct intel_atomic_state *state, 68 struct intel_crtc *crtc); 69 void (*crtc_disable)(struct intel_atomic_state *state, 70 struct intel_crtc *crtc); 71 void (*commit_modeset_enables)(struct intel_atomic_state *state); 72 }; 73 74 /* functions used for watermark calcs for display. */ 75 struct intel_wm_funcs { 76 /* update_wm is for legacy wm management */ 77 void (*update_wm)(struct drm_i915_private *dev_priv); 78 int (*compute_pipe_wm)(struct intel_atomic_state *state, 79 struct intel_crtc *crtc); 80 int (*compute_intermediate_wm)(struct intel_atomic_state *state, 81 struct intel_crtc *crtc); 82 void (*initial_watermarks)(struct intel_atomic_state *state, 83 struct intel_crtc *crtc); 84 void (*atomic_update_watermarks)(struct intel_atomic_state *state, 85 struct intel_crtc *crtc); 86 void (*optimize_watermarks)(struct intel_atomic_state *state, 87 struct intel_crtc *crtc); 88 int (*compute_global_watermarks)(struct intel_atomic_state *state); 89 void (*get_hw_state)(struct drm_i915_private *i915); 90 }; 91 92 struct intel_audio_state { 93 struct intel_encoder *encoder; 94 u8 eld[MAX_ELD_BYTES]; 95 }; 96 97 struct intel_audio { 98 /* hda/i915 audio component */ 99 struct i915_audio_component *component; 100 bool component_registered; 101 /* mutex for audio/video sync */ 102 struct mutex mutex; 103 int power_refcount; 104 u32 freq_cntrl; 105 106 /* current audio state for the audio component hooks */ 107 struct intel_audio_state state[I915_MAX_TRANSCODERS]; 108 109 /* necessary resource sharing with HDMI LPE audio driver. */ 110 struct { 111 struct platform_device *platdev; 112 int irq; 113 } lpe; 114 }; 115 116 /* 117 * dpll and cdclk state is protected by connection_mutex dpll.lock serializes 118 * intel_{prepare,enable,disable}_shared_dpll. Must be global rather than per 119 * dpll, because on some platforms plls share registers. 120 */ 121 struct intel_dpll { 122 struct mutex lock; 123 124 int num_shared_dpll; 125 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; 126 const struct intel_dpll_mgr *mgr; 127 128 struct { 129 int nssc; 130 int ssc; 131 } ref_clks; 132 133 /* 134 * Bitmask of PLLs using the PCH SSC, indexed using enum intel_dpll_id. 135 */ 136 u8 pch_ssc_use; 137 }; 138 139 struct intel_frontbuffer_tracking { 140 spinlock_t lock; 141 142 /* 143 * Tracking bits for delayed frontbuffer flushing du to gpu activity or 144 * scheduled flips. 145 */ 146 unsigned busy_bits; 147 unsigned flip_bits; 148 }; 149 150 struct intel_hotplug { 151 struct delayed_work hotplug_work; 152 153 const u32 *hpd, *pch_hpd; 154 155 struct { 156 unsigned long last_jiffies; 157 int count; 158 enum { 159 HPD_ENABLED = 0, 160 HPD_DISABLED = 1, 161 HPD_MARK_DISABLED = 2 162 } state; 163 } stats[HPD_NUM_PINS]; 164 u32 event_bits; 165 u32 retry_bits; 166 struct delayed_work reenable_work; 167 168 u32 long_port_mask; 169 u32 short_port_mask; 170 struct work_struct dig_port_work; 171 172 struct work_struct poll_init_work; 173 bool poll_enabled; 174 175 unsigned int hpd_storm_threshold; 176 /* Whether or not to count short HPD IRQs in HPD storms */ 177 u8 hpd_short_storm_enabled; 178 179 /* Last state reported by oob_hotplug_event for each encoder */ 180 unsigned long oob_hotplug_last_state; 181 182 /* 183 * if we get a HPD irq from DP and a HPD irq from non-DP 184 * the non-DP HPD could block the workqueue on a mode config 185 * mutex getting, that userspace may have taken. However 186 * userspace is waiting on the DP workqueue to run which is 187 * blocked behind the non-DP one. 188 */ 189 struct workqueue_struct *dp_wq; 190 191 /* 192 * Flag to track if long HPDs need not to be processed 193 * 194 * Some panels generate long HPDs while keep connected to the port. 195 * This can cause issues with CI tests results. In CI systems we 196 * don't expect to disconnect the panels and could ignore the long 197 * HPDs generated from the faulty panels. This flag can be used as 198 * cue to ignore the long HPDs and can be set / unset using debugfs. 199 */ 200 bool ignore_long_hpd; 201 }; 202 203 struct intel_vbt_data { 204 /* bdb version */ 205 u16 version; 206 207 /* Feature bits */ 208 unsigned int int_tv_support:1; 209 unsigned int int_crt_support:1; 210 unsigned int lvds_use_ssc:1; 211 unsigned int int_lvds_support:1; 212 unsigned int display_clock_mode:1; 213 unsigned int fdi_rx_polarity_inverted:1; 214 int lvds_ssc_freq; 215 enum drm_panel_orientation orientation; 216 217 bool override_afc_startup; 218 u8 override_afc_startup_val; 219 220 int crt_ddc_pin; 221 222 struct list_head display_devices; 223 struct list_head bdb_blocks; 224 225 struct sdvo_device_mapping { 226 u8 initialized; 227 u8 dvo_port; 228 u8 slave_addr; 229 u8 dvo_wiring; 230 u8 i2c_pin; 231 u8 ddc_pin; 232 } sdvo_mappings[2]; 233 }; 234 235 struct intel_wm { 236 /* 237 * Raw watermark latency values: 238 * in 0.1us units for WM0, 239 * in 0.5us units for WM1+. 240 */ 241 /* primary */ 242 u16 pri_latency[5]; 243 /* sprite */ 244 u16 spr_latency[5]; 245 /* cursor */ 246 u16 cur_latency[5]; 247 /* 248 * Raw watermark memory latency values 249 * for SKL for all 8 levels 250 * in 1us units. 251 */ 252 u16 skl_latency[8]; 253 254 /* current hardware state */ 255 union { 256 struct ilk_wm_values hw; 257 struct vlv_wm_values vlv; 258 struct g4x_wm_values g4x; 259 }; 260 261 u8 num_levels; 262 263 /* 264 * Should be held around atomic WM register writing; also 265 * protects * intel_crtc->wm.active and 266 * crtc_state->wm.need_postvbl_update. 267 */ 268 struct mutex wm_mutex; 269 270 bool ipc_enabled; 271 }; 272 273 struct intel_display { 274 /* Display functions */ 275 struct { 276 /* Top level crtc-ish functions */ 277 const struct intel_display_funcs *display; 278 279 /* Display CDCLK functions */ 280 const struct intel_cdclk_funcs *cdclk; 281 282 /* Display pll funcs */ 283 const struct intel_dpll_funcs *dpll; 284 285 /* irq display functions */ 286 const struct intel_hotplug_funcs *hotplug; 287 288 /* pm display functions */ 289 const struct intel_wm_funcs *wm; 290 291 /* fdi display functions */ 292 const struct intel_fdi_funcs *fdi; 293 294 /* Display internal color functions */ 295 const struct intel_color_funcs *color; 296 297 /* Display internal audio functions */ 298 const struct intel_audio_funcs *audio; 299 } funcs; 300 301 struct { 302 /* backlight registers and fields in struct intel_panel */ 303 struct mutex lock; 304 } backlight; 305 306 struct { 307 struct intel_global_obj obj; 308 309 struct intel_bw_info { 310 /* for each QGV point */ 311 unsigned int deratedbw[I915_NUM_QGV_POINTS]; 312 /* for each PSF GV point */ 313 unsigned int psf_bw[I915_NUM_PSF_GV_POINTS]; 314 /* Peak BW for each QGV point */ 315 unsigned int peakbw[I915_NUM_QGV_POINTS]; 316 u8 num_qgv_points; 317 u8 num_psf_gv_points; 318 u8 num_planes; 319 } max[6]; 320 } bw; 321 322 struct { 323 /* The current hardware cdclk configuration */ 324 struct intel_cdclk_config hw; 325 326 /* cdclk, divider, and ratio table from bspec */ 327 const struct intel_cdclk_vals *table; 328 329 struct intel_global_obj obj; 330 331 unsigned int max_cdclk_freq; 332 } cdclk; 333 334 struct { 335 struct drm_property_blob *glk_linear_degamma_lut; 336 } color; 337 338 struct { 339 /* The current hardware dbuf configuration */ 340 u8 enabled_slices; 341 342 struct intel_global_obj obj; 343 } dbuf; 344 345 struct { 346 /* 347 * dkl.phy_lock protects against concurrent access of the 348 * Dekel TypeC PHYs. 349 */ 350 spinlock_t phy_lock; 351 } dkl; 352 353 struct { 354 struct intel_dmc *dmc; 355 intel_wakeref_t wakeref; 356 } dmc; 357 358 struct { 359 /* VLV/CHV/BXT/GLK DSI MMIO register base address */ 360 u32 mmio_base; 361 } dsi; 362 363 struct { 364 /* list of fbdev register on this device */ 365 struct intel_fbdev *fbdev; 366 struct work_struct suspend_work; 367 } fbdev; 368 369 struct { 370 unsigned int pll_freq; 371 u32 rx_config; 372 } fdi; 373 374 struct { 375 struct list_head obj_list; 376 } global; 377 378 struct { 379 /* 380 * Base address of where the gmbus and gpio blocks are located 381 * (either on PCH or on SoC for platforms without PCH). 382 */ 383 u32 mmio_base; 384 385 /* 386 * gmbus.mutex protects against concurrent usage of the single 387 * hw gmbus controller on different i2c buses. 388 */ 389 struct mutex mutex; 390 391 struct intel_gmbus *bus[GMBUS_NUM_PINS]; 392 393 wait_queue_head_t wait_queue; 394 } gmbus; 395 396 struct { 397 struct i915_hdcp_arbiter *arbiter; 398 bool comp_added; 399 400 /* 401 * HDCP message struct for allocation of memory which can be 402 * reused when sending message to gsc cs. 403 * this is only populated post Meteorlake 404 */ 405 struct intel_hdcp_gsc_message *hdcp_message; 406 /* Mutex to protect the above hdcp related values. */ 407 struct mutex hdcp_mutex; 408 } hdcp; 409 410 struct { 411 /* 412 * HTI (aka HDPORT) state read during initial hw readout. Most 413 * platforms don't have HTI, so this will just stay 0. Those 414 * that do will use this later to figure out which PLLs and PHYs 415 * are unavailable for driver usage. 416 */ 417 u32 state; 418 } hti; 419 420 struct { 421 /* Access with DISPLAY_INFO() */ 422 const struct intel_display_device_info *__device_info; 423 424 /* Access with DISPLAY_RUNTIME_INFO() */ 425 struct intel_display_runtime_info __runtime_info; 426 } info; 427 428 struct { 429 bool false_color; 430 } ips; 431 432 struct { 433 wait_queue_head_t waitqueue; 434 435 /* mutex to protect pmdemand programming sequence */ 436 struct mutex lock; 437 438 struct intel_global_obj obj; 439 } pmdemand; 440 441 struct { 442 struct i915_power_domains domains; 443 444 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */ 445 u32 chv_phy_control; 446 447 /* perform PHY state sanity checks? */ 448 bool chv_phy_assert[2]; 449 } power; 450 451 struct { 452 u32 mmio_base; 453 454 /* protects panel power sequencer state */ 455 struct mutex mutex; 456 } pps; 457 458 struct { 459 struct drm_property *broadcast_rgb; 460 struct drm_property *force_audio; 461 } properties; 462 463 struct { 464 unsigned long mask; 465 } quirks; 466 467 struct { 468 /* restore state for suspend/resume and display reset */ 469 struct drm_atomic_state *modeset_state; 470 struct drm_modeset_acquire_ctx reset_ctx; 471 } restore; 472 473 struct { 474 enum { 475 I915_SAGV_UNKNOWN = 0, 476 I915_SAGV_DISABLED, 477 I915_SAGV_ENABLED, 478 I915_SAGV_NOT_CONTROLLED 479 } status; 480 481 u32 block_time_us; 482 } sagv; 483 484 struct { 485 /* 486 * DG2: Mask of PHYs that were not calibrated by the firmware 487 * and should not be used. 488 */ 489 u8 phy_failed_calibration; 490 } snps; 491 492 struct { 493 /* 494 * Shadows for CHV DPLL_MD regs to keep the state 495 * checker somewhat working in the presence hardware 496 * crappiness (can't read out DPLL_MD for pipes B & C). 497 */ 498 u32 chv_dpll_md[I915_MAX_PIPES]; 499 u32 bxt_phy_grc; 500 } state; 501 502 struct { 503 /* ordered wq for modesets */ 504 struct workqueue_struct *modeset; 505 506 /* unbound hipri wq for page flips/plane updates */ 507 struct workqueue_struct *flip; 508 } wq; 509 510 /* Grouping using named structs. Keep sorted. */ 511 struct intel_audio audio; 512 struct intel_dpll dpll; 513 struct intel_fbc *fbc[I915_MAX_FBCS]; 514 struct intel_frontbuffer_tracking fb_tracking; 515 struct intel_hotplug hotplug; 516 struct intel_opregion opregion; 517 struct intel_overlay *overlay; 518 struct intel_display_params params; 519 struct intel_vbt_data vbt; 520 struct intel_wm wm; 521 }; 522 523 #endif /* __INTEL_DISPLAY_CORE_H__ */ 524