Lines Matching +full:ssc +full:- +full:internal
2 * Copyright © 2006-2016 Intel Corporation
44 * per-pipe or per-encoder dedicated PLLs, others allow the use of any PLL
123 shared_dpll[pll->index] = pll->state; in intel_atomic_duplicate_dpll_state()
131 drm_WARN_ON(s->dev, !drm_modeset_is_locked(&s->dev->mode_config.connection_mutex)); in intel_atomic_get_shared_dpll_state()
133 if (!state->dpll_set) { in intel_atomic_get_shared_dpll_state()
134 state->dpll_set = true; in intel_atomic_get_shared_dpll_state()
136 intel_atomic_duplicate_dpll_state(to_i915(s->dev), in intel_atomic_get_shared_dpll_state()
137 state->shared_dpll); in intel_atomic_get_shared_dpll_state()
140 return state->shared_dpll; in intel_atomic_get_shared_dpll_state()
144 * intel_get_shared_dpll_by_id - get a DPLL given its id
159 if (pll->info->id == id) in intel_get_shared_dpll_by_id()
175 if (drm_WARN(&i915->drm, !pll, in assert_shared_dpll()
182 pll->info->name, str_on_off(state), in assert_shared_dpll()
188 return TC_PORT_1 + id - DPLL_ID_ICL_MGPLL1; in icl_pll_id_to_tc_port()
193 return tc_port - TC_PORT_1 + DPLL_ID_ICL_MGPLL1; in icl_tc_port_to_pll_id()
201 return DG1_DPLL_ENABLE(pll->info->id); in intel_combo_pll_enable_reg()
203 (pll->info->id == DPLL_ID_EHL_DPLL4)) in intel_combo_pll_enable_reg()
206 return ICL_DPLL_ENABLE(pll->info->id); in intel_combo_pll_enable_reg()
213 const enum intel_dpll_id id = pll->info->id; in intel_tc_pll_enable_reg()
225 if (pll->info->power_domain) in _intel_enable_shared_dpll()
226 pll->wakeref = intel_display_power_get(i915, pll->info->power_domain); in _intel_enable_shared_dpll()
228 pll->info->funcs->enable(i915, pll); in _intel_enable_shared_dpll()
229 pll->on = true; in _intel_enable_shared_dpll()
235 pll->info->funcs->disable(i915, pll); in _intel_disable_shared_dpll()
236 pll->on = false; in _intel_disable_shared_dpll()
238 if (pll->info->power_domain) in _intel_disable_shared_dpll()
239 intel_display_power_put(i915, pll->info->power_domain, pll->wakeref); in _intel_disable_shared_dpll()
243 * intel_enable_shared_dpll - enable a CRTC's shared DPLL
250 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_enable_shared_dpll()
251 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_enable_shared_dpll()
252 struct intel_shared_dpll *pll = crtc_state->shared_dpll; in intel_enable_shared_dpll()
253 unsigned int pipe_mask = BIT(crtc->pipe); in intel_enable_shared_dpll()
256 if (drm_WARN_ON(&i915->drm, pll == NULL)) in intel_enable_shared_dpll()
259 mutex_lock(&i915->display.dpll.lock); in intel_enable_shared_dpll()
260 old_mask = pll->active_mask; in intel_enable_shared_dpll()
262 if (drm_WARN_ON(&i915->drm, !(pll->state.pipe_mask & pipe_mask)) || in intel_enable_shared_dpll()
263 drm_WARN_ON(&i915->drm, pll->active_mask & pipe_mask)) in intel_enable_shared_dpll()
266 pll->active_mask |= pipe_mask; in intel_enable_shared_dpll()
268 drm_dbg_kms(&i915->drm, in intel_enable_shared_dpll()
270 pll->info->name, pll->active_mask, pll->on, in intel_enable_shared_dpll()
271 crtc->base.base.id, crtc->base.name); in intel_enable_shared_dpll()
274 drm_WARN_ON(&i915->drm, !pll->on); in intel_enable_shared_dpll()
278 drm_WARN_ON(&i915->drm, pll->on); in intel_enable_shared_dpll()
280 drm_dbg_kms(&i915->drm, "enabling %s\n", pll->info->name); in intel_enable_shared_dpll()
285 mutex_unlock(&i915->display.dpll.lock); in intel_enable_shared_dpll()
289 * intel_disable_shared_dpll - disable a CRTC's shared DPLL
296 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_disable_shared_dpll()
297 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_disable_shared_dpll()
298 struct intel_shared_dpll *pll = crtc_state->shared_dpll; in intel_disable_shared_dpll()
299 unsigned int pipe_mask = BIT(crtc->pipe); in intel_disable_shared_dpll()
308 mutex_lock(&i915->display.dpll.lock); in intel_disable_shared_dpll()
309 if (drm_WARN(&i915->drm, !(pll->active_mask & pipe_mask), in intel_disable_shared_dpll()
310 "%s not used by [CRTC:%d:%s]\n", pll->info->name, in intel_disable_shared_dpll()
311 crtc->base.base.id, crtc->base.name)) in intel_disable_shared_dpll()
314 drm_dbg_kms(&i915->drm, in intel_disable_shared_dpll()
316 pll->info->name, pll->active_mask, pll->on, in intel_disable_shared_dpll()
317 crtc->base.base.id, crtc->base.name); in intel_disable_shared_dpll()
320 drm_WARN_ON(&i915->drm, !pll->on); in intel_disable_shared_dpll()
322 pll->active_mask &= ~pipe_mask; in intel_disable_shared_dpll()
323 if (pll->active_mask) in intel_disable_shared_dpll()
326 drm_dbg_kms(&i915->drm, "disabling %s\n", pll->info->name); in intel_disable_shared_dpll()
331 mutex_unlock(&i915->display.dpll.lock); in intel_disable_shared_dpll()
342 drm_WARN_ON(&i915->drm, dpll_mask & BIT(pll->info->id)); in intel_dpll_mask_all()
344 dpll_mask |= BIT(pll->info->id); in intel_dpll_mask_all()
356 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_find_shared_dpll()
362 shared_dpll = intel_atomic_get_shared_dpll_state(&state->base); in intel_find_shared_dpll()
364 drm_WARN_ON(&i915->drm, dpll_mask & ~dpll_mask_all); in intel_find_shared_dpll()
374 if (shared_dpll[pll->index].pipe_mask == 0) { in intel_find_shared_dpll()
381 &shared_dpll[pll->index].hw_state, in intel_find_shared_dpll()
383 drm_dbg_kms(&i915->drm, in intel_find_shared_dpll()
385 crtc->base.base.id, crtc->base.name, in intel_find_shared_dpll()
386 pll->info->name, in intel_find_shared_dpll()
387 shared_dpll[pll->index].pipe_mask, in intel_find_shared_dpll()
388 pll->active_mask); in intel_find_shared_dpll()
395 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] allocated %s\n", in intel_find_shared_dpll()
396 crtc->base.base.id, crtc->base.name, in intel_find_shared_dpll()
397 unused_pll->info->name); in intel_find_shared_dpll()
405 * intel_reference_shared_dpll_crtc - Get a DPLL reference for a CRTC
417 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_reference_shared_dpll_crtc()
419 drm_WARN_ON(&i915->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) != 0); in intel_reference_shared_dpll_crtc()
421 shared_dpll_state->pipe_mask |= BIT(crtc->pipe); in intel_reference_shared_dpll_crtc()
423 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] reserving %s\n", in intel_reference_shared_dpll_crtc()
424 crtc->base.base.id, crtc->base.name, pll->info->name); in intel_reference_shared_dpll_crtc()
435 shared_dpll = intel_atomic_get_shared_dpll_state(&state->base); in intel_reference_shared_dpll()
437 if (shared_dpll[pll->index].pipe_mask == 0) in intel_reference_shared_dpll()
438 shared_dpll[pll->index].hw_state = *pll_state; in intel_reference_shared_dpll()
440 intel_reference_shared_dpll_crtc(crtc, pll, &shared_dpll[pll->index]); in intel_reference_shared_dpll()
444 * intel_unreference_shared_dpll_crtc - Drop a DPLL reference for a CRTC
456 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_unreference_shared_dpll_crtc()
458 drm_WARN_ON(&i915->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) == 0); in intel_unreference_shared_dpll_crtc()
460 shared_dpll_state->pipe_mask &= ~BIT(crtc->pipe); in intel_unreference_shared_dpll_crtc()
462 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] releasing %s\n", in intel_unreference_shared_dpll_crtc()
463 crtc->base.base.id, crtc->base.name, pll->info->name); in intel_unreference_shared_dpll_crtc()
472 shared_dpll = intel_atomic_get_shared_dpll_state(&state->base); in intel_unreference_shared_dpll()
474 intel_unreference_shared_dpll_crtc(crtc, pll, &shared_dpll[pll->index]); in intel_unreference_shared_dpll()
485 new_crtc_state->shared_dpll = NULL; in intel_put_dpll()
487 if (!old_crtc_state->shared_dpll) in intel_put_dpll()
490 intel_unreference_shared_dpll(state, crtc, old_crtc_state->shared_dpll); in intel_put_dpll()
494 * intel_shared_dpll_swap_state - make atomic DPLL configuration effective
498 * helper does not handle driver-specific global state.
506 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_shared_dpll_swap_state()
507 struct intel_shared_dpll_state *shared_dpll = state->shared_dpll; in intel_shared_dpll_swap_state()
511 if (!state->dpll_set) in intel_shared_dpll_swap_state()
515 swap(pll->state, shared_dpll[pll->index]); in intel_shared_dpll_swap_state()
522 const enum intel_dpll_id id = pll->info->id; in ibx_pch_dpll_get_hw_state()
532 hw_state->dpll = val; in ibx_pch_dpll_get_hw_state()
533 hw_state->fp0 = intel_de_read(i915, PCH_FP0(id)); in ibx_pch_dpll_get_hw_state()
534 hw_state->fp1 = intel_de_read(i915, PCH_FP1(id)); in ibx_pch_dpll_get_hw_state()
556 const enum intel_dpll_id id = pll->info->id; in ibx_pch_dpll_enable()
561 intel_de_write(i915, PCH_FP0(id), pll->state.hw_state.fp0); in ibx_pch_dpll_enable()
562 intel_de_write(i915, PCH_FP1(id), pll->state.hw_state.fp1); in ibx_pch_dpll_enable()
564 intel_de_write(i915, PCH_DPLL(id), pll->state.hw_state.dpll); in ibx_pch_dpll_enable()
575 intel_de_write(i915, PCH_DPLL(id), pll->state.hw_state.dpll); in ibx_pch_dpll_enable()
583 const enum intel_dpll_id id = pll->info->id; in ibx_pch_dpll_disable()
603 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in ibx_get_dpll()
608 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ in ibx_get_dpll()
609 id = (enum intel_dpll_id) crtc->pipe; in ibx_get_dpll()
612 drm_dbg_kms(&i915->drm, in ibx_get_dpll()
613 "[CRTC:%d:%s] using pre-allocated %s\n", in ibx_get_dpll()
614 crtc->base.base.id, crtc->base.name, in ibx_get_dpll()
615 pll->info->name); in ibx_get_dpll()
618 &crtc_state->dpll_hw_state, in ibx_get_dpll()
624 return -EINVAL; in ibx_get_dpll()
628 pll, &crtc_state->dpll_hw_state); in ibx_get_dpll()
630 crtc_state->shared_dpll = pll; in ibx_get_dpll()
638 drm_dbg_kms(&i915->drm, in ibx_dump_hw_state()
641 hw_state->dpll, in ibx_dump_hw_state()
642 hw_state->dpll_md, in ibx_dump_hw_state()
643 hw_state->fp0, in ibx_dump_hw_state()
644 hw_state->fp1); in ibx_dump_hw_state()
670 const enum intel_dpll_id id = pll->info->id; in hsw_ddi_wrpll_enable()
672 intel_de_write(i915, WRPLL_CTL(id), pll->state.hw_state.wrpll); in hsw_ddi_wrpll_enable()
680 intel_de_write(i915, SPLL_CTL, pll->state.hw_state.spll); in hsw_ddi_spll_enable()
688 const enum intel_dpll_id id = pll->info->id; in hsw_ddi_wrpll_disable()
697 if (i915->display.dpll.pch_ssc_use & BIT(id)) in hsw_ddi_wrpll_disable()
704 enum intel_dpll_id id = pll->info->id; in hsw_ddi_spll_disable()
713 if (i915->display.dpll.pch_ssc_use & BIT(id)) in hsw_ddi_spll_disable()
721 const enum intel_dpll_id id = pll->info->id; in hsw_ddi_wrpll_get_hw_state()
731 hw_state->wrpll = val; in hsw_ddi_wrpll_get_hw_state()
751 hw_state->spll = val; in hsw_ddi_spll_get_hw_state()
847 if (best->p == 0) { in hsw_wrpll_update_rnp()
848 best->p = p; in hsw_wrpll_update_rnp()
849 best->n2 = n2; in hsw_wrpll_update_rnp()
850 best->r2 = r2; in hsw_wrpll_update_rnp()
859 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) / in hsw_wrpll_update_rnp()
864 * If the discrepancy is above the PPM-based budget, always prefer to in hsw_wrpll_update_rnp()
869 b = freq2k * budget * best->p * best->r2; in hsw_wrpll_update_rnp()
871 diff_best = abs_diff(freq2k * best->p * best->r2, in hsw_wrpll_update_rnp()
872 LC_FREQ_2K * best->n2); in hsw_wrpll_update_rnp()
878 if (best->p * best->r2 * diff < p * r2 * diff_best) { in hsw_wrpll_update_rnp()
879 best->p = p; in hsw_wrpll_update_rnp()
880 best->n2 = n2; in hsw_wrpll_update_rnp()
881 best->r2 = r2; in hsw_wrpll_update_rnp()
885 best->p = p; in hsw_wrpll_update_rnp()
886 best->n2 = n2; in hsw_wrpll_update_rnp()
887 best->r2 = r2; in hsw_wrpll_update_rnp()
890 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) { in hsw_wrpll_update_rnp()
891 best->p = p; in hsw_wrpll_update_rnp()
892 best->n2 = n2; in hsw_wrpll_update_rnp()
893 best->r2 = r2; in hsw_wrpll_update_rnp()
970 u32 wrpll = pll_state->wrpll; in hsw_ddi_wrpll_get_freq()
974 /* Muxed-SSC for BDW, non-SSC for non-ULT HSW. */ in hsw_ddi_wrpll_get_freq()
976 refclk = i915->display.dpll.ref_clks.nssc; in hsw_ddi_wrpll_get_freq()
986 refclk = i915->display.dpll.ref_clks.ssc; in hsw_ddi_wrpll_get_freq()
1008 struct drm_i915_private *i915 = to_i915(state->base.dev); in hsw_ddi_wrpll_compute_dpll()
1013 hsw_ddi_calculate_wrpll(crtc_state->port_clock * 1000, &r2, &n2, &p); in hsw_ddi_wrpll_compute_dpll()
1015 crtc_state->dpll_hw_state.wrpll = in hsw_ddi_wrpll_compute_dpll()
1020 crtc_state->port_clock = hsw_ddi_wrpll_get_freq(i915, NULL, in hsw_ddi_wrpll_compute_dpll()
1021 &crtc_state->dpll_hw_state); in hsw_ddi_wrpll_compute_dpll()
1034 &crtc_state->dpll_hw_state, in hsw_ddi_wrpll_get_dpll()
1042 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in hsw_ddi_lcpll_compute_dpll()
1043 int clock = crtc_state->port_clock; in hsw_ddi_lcpll_compute_dpll()
1051 drm_dbg_kms(&i915->drm, "Invalid clock for DP: %d\n", in hsw_ddi_lcpll_compute_dpll()
1053 return -EINVAL; in hsw_ddi_lcpll_compute_dpll()
1060 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in hsw_ddi_lcpll_get_dpll()
1063 int clock = crtc_state->port_clock; in hsw_ddi_lcpll_get_dpll()
1094 switch (pll->info->id) { in hsw_ddi_lcpll_get_freq()
1105 drm_WARN(&i915->drm, 1, "bad port clock sel\n"); in hsw_ddi_lcpll_get_freq()
1119 if (drm_WARN_ON(crtc->base.dev, crtc_state->port_clock / 2 != 135000)) in hsw_ddi_spll_compute_dpll()
1120 return -EINVAL; in hsw_ddi_spll_compute_dpll()
1122 crtc_state->dpll_hw_state.spll = in hsw_ddi_spll_compute_dpll()
1135 return intel_find_shared_dpll(state, crtc, &crtc_state->dpll_hw_state, in hsw_ddi_spll_get_dpll()
1145 switch (pll_state->spll & SPLL_FREQ_MASK) { in hsw_ddi_spll_get_freq()
1156 drm_WARN(&i915->drm, 1, "bad spll freq\n"); in hsw_ddi_spll_get_freq()
1177 return -EINVAL; in hsw_compute_dpll()
1196 return -EINVAL; in hsw_get_dpll()
1199 pll, &crtc_state->dpll_hw_state); in hsw_get_dpll()
1201 crtc_state->shared_dpll = pll; in hsw_get_dpll()
1208 i915->display.dpll.ref_clks.ssc = 135000; in hsw_update_dpll_ref_clks()
1209 /* Non-SSC is only used on non-ULT HSW. */ in hsw_update_dpll_ref_clks()
1211 i915->display.dpll.ref_clks.nssc = 24000; in hsw_update_dpll_ref_clks()
1213 i915->display.dpll.ref_clks.nssc = 135000; in hsw_update_dpll_ref_clks()
1219 drm_dbg_kms(&i915->drm, "dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", in hsw_dump_hw_state()
1220 hw_state->wrpll, hw_state->spll); in hsw_dump_hw_state()
1317 const enum intel_dpll_id id = pll->info->id; in skl_ddi_pll_write_ctrl1()
1321 pll->state.hw_state.ctrl1 << (id * 6)); in skl_ddi_pll_write_ctrl1()
1329 const enum intel_dpll_id id = pll->info->id; in skl_ddi_pll_enable()
1333 intel_de_write(i915, regs[id].cfgcr1, pll->state.hw_state.cfgcr1); in skl_ddi_pll_enable()
1334 intel_de_write(i915, regs[id].cfgcr2, pll->state.hw_state.cfgcr2); in skl_ddi_pll_enable()
1342 drm_err(&i915->drm, "DPLL %d not locked\n", id); in skl_ddi_pll_enable()
1355 const enum intel_dpll_id id = pll->info->id; in skl_ddi_pll_disable()
1373 const enum intel_dpll_id id = pll->info->id; in skl_ddi_pll_get_hw_state()
1389 hw_state->ctrl1 = (val >> (id * 6)) & 0x3f; in skl_ddi_pll_get_hw_state()
1393 hw_state->cfgcr1 = intel_de_read(i915, regs[id].cfgcr1); in skl_ddi_pll_get_hw_state()
1394 hw_state->cfgcr2 = intel_de_read(i915, regs[id].cfgcr2); in skl_ddi_pll_get_hw_state()
1409 const enum intel_dpll_id id = pll->info->id; in skl_ddi_dpll0_get_hw_state()
1423 if (drm_WARN_ON(&i915->drm, !(val & LCPLL_PLL_ENABLE))) in skl_ddi_dpll0_get_hw_state()
1427 hw_state->ctrl1 = (val >> (id * 6)) & 0x3f; in skl_ddi_dpll0_get_hw_state()
1444 /* DCO freq must be within +1%/-6% of the DCO central freq */
1461 deviation < ctx->min_deviation) { in skl_wrpll_try_divider()
1462 ctx->min_deviation = deviation; in skl_wrpll_try_divider()
1463 ctx->central_freq = central_freq; in skl_wrpll_try_divider()
1464 ctx->dco_freq = dco_freq; in skl_wrpll_try_divider()
1465 ctx->p = divider; in skl_wrpll_try_divider()
1469 deviation < ctx->min_deviation) { in skl_wrpll_try_divider()
1470 ctx->min_deviation = deviation; in skl_wrpll_try_divider()
1471 ctx->central_freq = central_freq; in skl_wrpll_try_divider()
1472 ctx->dco_freq = dco_freq; in skl_wrpll_try_divider()
1473 ctx->p = divider; in skl_wrpll_try_divider()
1546 params->central_freq = 0; in skl_wrpll_params_populate()
1549 params->central_freq = 1; in skl_wrpll_params_populate()
1552 params->central_freq = 3; in skl_wrpll_params_populate()
1557 params->pdiv = 0; in skl_wrpll_params_populate()
1560 params->pdiv = 1; in skl_wrpll_params_populate()
1563 params->pdiv = 2; in skl_wrpll_params_populate()
1566 params->pdiv = 4; in skl_wrpll_params_populate()
1574 params->kdiv = 0; in skl_wrpll_params_populate()
1577 params->kdiv = 1; in skl_wrpll_params_populate()
1580 params->kdiv = 2; in skl_wrpll_params_populate()
1583 params->kdiv = 3; in skl_wrpll_params_populate()
1589 params->qdiv_ratio = p1; in skl_wrpll_params_populate()
1590 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1; in skl_wrpll_params_populate()
1598 params->dco_integer = div_u64(dco_freq, ref_clock * KHz(1)); in skl_wrpll_params_populate()
1599 params->dco_fraction = in skl_wrpll_params_populate()
1600 div_u64((div_u64(dco_freq, ref_clock / KHz(1)) - in skl_wrpll_params_populate()
1601 params->dco_integer * MHz(1)) * 0x8000, MHz(1)); in skl_wrpll_params_populate()
1662 return -EINVAL; in skl_ddi_calculate_wrpll()
1680 int ref_clock = i915->display.dpll.ref_clks.nssc; in skl_ddi_wrpll_get_freq()
1683 p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK; in skl_ddi_wrpll_get_freq()
1684 p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK; in skl_ddi_wrpll_get_freq()
1686 if (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_MODE(1)) in skl_ddi_wrpll_get_freq()
1687 p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8; in skl_ddi_wrpll_get_freq()
1704 * Incorrect ASUS-Z170M BIOS setting, the HW seems to ignore bit#0, in skl_ddi_wrpll_get_freq()
1707 drm_dbg_kms(&i915->drm, "Invalid WRPLL PDIV divider value, fixing it.\n"); in skl_ddi_wrpll_get_freq()
1735 dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK) * in skl_ddi_wrpll_get_freq()
1738 dco_freq += ((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * in skl_ddi_wrpll_get_freq()
1741 if (drm_WARN_ON(&i915->drm, p0 == 0 || p1 == 0 || p2 == 0)) in skl_ddi_wrpll_get_freq()
1749 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in skl_ddi_hdmi_pll_dividers()
1762 ret = skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000, in skl_ddi_hdmi_pll_dividers()
1763 i915->display.dpll.ref_clks.nssc, &wrpll_params); in skl_ddi_hdmi_pll_dividers()
1777 crtc_state->dpll_hw_state.ctrl1 = ctrl1; in skl_ddi_hdmi_pll_dividers()
1778 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1; in skl_ddi_hdmi_pll_dividers()
1779 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2; in skl_ddi_hdmi_pll_dividers()
1781 crtc_state->port_clock = skl_ddi_wrpll_get_freq(i915, NULL, in skl_ddi_hdmi_pll_dividers()
1782 &crtc_state->dpll_hw_state); in skl_ddi_hdmi_pll_dividers()
1797 switch (crtc_state->port_clock / 2) { in skl_ddi_dp_set_dpll_hw_state()
1819 crtc_state->dpll_hw_state.ctrl1 = ctrl1; in skl_ddi_dp_set_dpll_hw_state()
1830 switch ((pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0)) >> in skl_ddi_lcpll_get_freq()
1851 drm_WARN(&i915->drm, 1, "Unsupported link rate\n"); in skl_ddi_lcpll_get_freq()
1870 return -EINVAL; in skl_compute_dpll()
1883 &crtc_state->dpll_hw_state, in skl_get_dpll()
1887 &crtc_state->dpll_hw_state, in skl_get_dpll()
1892 return -EINVAL; in skl_get_dpll()
1895 pll, &crtc_state->dpll_hw_state); in skl_get_dpll()
1897 crtc_state->shared_dpll = pll; in skl_get_dpll()
1908 * the internal shift for each field in skl_ddi_pll_get_freq()
1910 if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) in skl_ddi_pll_get_freq()
1918 /* No SSC ref */ in skl_update_dpll_ref_clks()
1919 i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; in skl_update_dpll_ref_clks()
1925 drm_dbg_kms(&i915->drm, "dpll_hw_state: " in skl_dump_hw_state()
1927 hw_state->ctrl1, in skl_dump_hw_state()
1928 hw_state->cfgcr1, in skl_dump_hw_state()
1929 hw_state->cfgcr2); in skl_dump_hw_state()
1968 enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */ in bxt_ddi_pll_enable()
1974 /* Non-SSC reference */ in bxt_ddi_pll_enable()
1983 drm_err(&i915->drm, in bxt_ddi_pll_enable()
1993 PORT_PLL_P1_MASK | PORT_PLL_P2_MASK, pll->state.hw_state.ebb0); in bxt_ddi_pll_enable()
1997 PORT_PLL_M2_INT_MASK, pll->state.hw_state.pll0); in bxt_ddi_pll_enable()
2001 PORT_PLL_N_MASK, pll->state.hw_state.pll1); in bxt_ddi_pll_enable()
2005 PORT_PLL_M2_FRAC_MASK, pll->state.hw_state.pll2); in bxt_ddi_pll_enable()
2009 PORT_PLL_M2_FRAC_ENABLE, pll->state.hw_state.pll3); in bxt_ddi_pll_enable()
2016 temp |= pll->state.hw_state.pll6; in bxt_ddi_pll_enable()
2021 PORT_PLL_TARGET_CNT_MASK, pll->state.hw_state.pll8); in bxt_ddi_pll_enable()
2024 PORT_PLL_LOCK_THRESHOLD_MASK, pll->state.hw_state.pll9); in bxt_ddi_pll_enable()
2029 temp |= pll->state.hw_state.pll10; in bxt_ddi_pll_enable()
2037 temp |= pll->state.hw_state.ebb4; in bxt_ddi_pll_enable()
2046 drm_err(&i915->drm, "PLL %d not locked\n", port); in bxt_ddi_pll_enable()
2061 temp |= pll->state.hw_state.pcsdw12; in bxt_ddi_pll_enable()
2068 enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */ in bxt_ddi_pll_disable()
2079 drm_err(&i915->drm, in bxt_ddi_pll_disable()
2088 enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */ in bxt_ddi_pll_get_hw_state()
2108 hw_state->ebb0 = intel_de_read(i915, BXT_PORT_PLL_EBB_0(phy, ch)); in bxt_ddi_pll_get_hw_state()
2109 hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK; in bxt_ddi_pll_get_hw_state()
2111 hw_state->ebb4 = intel_de_read(i915, BXT_PORT_PLL_EBB_4(phy, ch)); in bxt_ddi_pll_get_hw_state()
2112 hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE; in bxt_ddi_pll_get_hw_state()
2114 hw_state->pll0 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 0)); in bxt_ddi_pll_get_hw_state()
2115 hw_state->pll0 &= PORT_PLL_M2_INT_MASK; in bxt_ddi_pll_get_hw_state()
2117 hw_state->pll1 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 1)); in bxt_ddi_pll_get_hw_state()
2118 hw_state->pll1 &= PORT_PLL_N_MASK; in bxt_ddi_pll_get_hw_state()
2120 hw_state->pll2 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 2)); in bxt_ddi_pll_get_hw_state()
2121 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK; in bxt_ddi_pll_get_hw_state()
2123 hw_state->pll3 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 3)); in bxt_ddi_pll_get_hw_state()
2124 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE; in bxt_ddi_pll_get_hw_state()
2126 hw_state->pll6 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 6)); in bxt_ddi_pll_get_hw_state()
2127 hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK | in bxt_ddi_pll_get_hw_state()
2131 hw_state->pll8 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 8)); in bxt_ddi_pll_get_hw_state()
2132 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK; in bxt_ddi_pll_get_hw_state()
2134 hw_state->pll9 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 9)); in bxt_ddi_pll_get_hw_state()
2135 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK; in bxt_ddi_pll_get_hw_state()
2137 hw_state->pll10 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 10)); in bxt_ddi_pll_get_hw_state()
2138 hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H | in bxt_ddi_pll_get_hw_state()
2146 hw_state->pcsdw12 = intel_de_read(i915, in bxt_ddi_pll_get_hw_state()
2148 if (intel_de_read(i915, BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12) in bxt_ddi_pll_get_hw_state()
2149 drm_dbg(&i915->drm, in bxt_ddi_pll_get_hw_state()
2151 hw_state->pcsdw12, in bxt_ddi_pll_get_hw_state()
2154 hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD; in bxt_ddi_pll_get_hw_state()
2164 /* pre-calculated values for DP linkrates */
2180 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in bxt_ddi_hdmi_pll_dividers()
2188 return -EINVAL; in bxt_ddi_hdmi_pll_dividers()
2190 drm_WARN_ON(&i915->drm, clk_div->m1 != 2); in bxt_ddi_hdmi_pll_dividers()
2198 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in bxt_ddi_dp_pll_dividers()
2203 if (crtc_state->port_clock == bxt_dp_clk_val[i].dot) { in bxt_ddi_dp_pll_dividers()
2209 chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, clk_div); in bxt_ddi_dp_pll_dividers()
2211 drm_WARN_ON(&i915->drm, clk_div->vco == 0 || in bxt_ddi_dp_pll_dividers()
2212 clk_div->dot != crtc_state->port_clock); in bxt_ddi_dp_pll_dividers()
2218 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in bxt_ddi_set_dpll_hw_state()
2219 struct intel_dpll_hw_state *dpll_hw_state = &crtc_state->dpll_hw_state; in bxt_ddi_set_dpll_hw_state()
2220 int clock = crtc_state->port_clock; in bxt_ddi_set_dpll_hw_state()
2221 int vco = clk_div->vco; in bxt_ddi_set_dpll_hw_state()
2242 drm_err(&i915->drm, "Invalid VCO\n"); in bxt_ddi_set_dpll_hw_state()
2243 return -EINVAL; in bxt_ddi_set_dpll_hw_state()
2257 dpll_hw_state->ebb0 = PORT_PLL_P1(clk_div->p1) | PORT_PLL_P2(clk_div->p2); in bxt_ddi_set_dpll_hw_state()
2258 dpll_hw_state->pll0 = PORT_PLL_M2_INT(clk_div->m2 >> 22); in bxt_ddi_set_dpll_hw_state()
2259 dpll_hw_state->pll1 = PORT_PLL_N(clk_div->n); in bxt_ddi_set_dpll_hw_state()
2260 dpll_hw_state->pll2 = PORT_PLL_M2_FRAC(clk_div->m2 & 0x3fffff); in bxt_ddi_set_dpll_hw_state()
2262 if (clk_div->m2 & 0x3fffff) in bxt_ddi_set_dpll_hw_state()
2263 dpll_hw_state->pll3 = PORT_PLL_M2_FRAC_ENABLE; in bxt_ddi_set_dpll_hw_state()
2265 dpll_hw_state->pll6 = PORT_PLL_PROP_COEFF(prop_coef) | in bxt_ddi_set_dpll_hw_state()
2269 dpll_hw_state->pll8 = PORT_PLL_TARGET_CNT(targ_cnt); in bxt_ddi_set_dpll_hw_state()
2271 dpll_hw_state->pll9 = PORT_PLL_LOCK_THRESHOLD(5); in bxt_ddi_set_dpll_hw_state()
2273 dpll_hw_state->pll10 = PORT_PLL_DCO_AMP(15) | in bxt_ddi_set_dpll_hw_state()
2276 dpll_hw_state->ebb4 = PORT_PLL_10BIT_CLK_ENABLE; in bxt_ddi_set_dpll_hw_state()
2278 dpll_hw_state->pcsdw12 = LANESTAGGER_STRAP_OVRD | lanestagger; in bxt_ddi_set_dpll_hw_state()
2290 clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK, pll_state->pll0) << 22; in bxt_ddi_pll_get_freq()
2291 if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE) in bxt_ddi_pll_get_freq()
2292 clock.m2 |= REG_FIELD_GET(PORT_PLL_M2_FRAC_MASK, pll_state->pll2); in bxt_ddi_pll_get_freq()
2293 clock.n = REG_FIELD_GET(PORT_PLL_N_MASK, pll_state->pll1); in bxt_ddi_pll_get_freq()
2294 clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK, pll_state->ebb0); in bxt_ddi_pll_get_freq()
2295 clock.p2 = REG_FIELD_GET(PORT_PLL_P2_MASK, pll_state->ebb0); in bxt_ddi_pll_get_freq()
2297 return chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, &clock); in bxt_ddi_pll_get_freq()
2313 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in bxt_ddi_hdmi_set_dpll_hw_state()
2323 crtc_state->port_clock = bxt_ddi_pll_get_freq(i915, NULL, in bxt_ddi_hdmi_set_dpll_hw_state()
2324 &crtc_state->dpll_hw_state); in bxt_ddi_hdmi_set_dpll_hw_state()
2341 return -EINVAL; in bxt_compute_dpll()
2350 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in bxt_get_dpll()
2355 id = (enum intel_dpll_id) encoder->port; in bxt_get_dpll()
2358 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] using pre-allocated %s\n", in bxt_get_dpll()
2359 crtc->base.base.id, crtc->base.name, pll->info->name); in bxt_get_dpll()
2362 pll, &crtc_state->dpll_hw_state); in bxt_get_dpll()
2364 crtc_state->shared_dpll = pll; in bxt_get_dpll()
2371 i915->display.dpll.ref_clks.ssc = 100000; in bxt_update_dpll_ref_clks()
2372 i915->display.dpll.ref_clks.nssc = 100000; in bxt_update_dpll_ref_clks()
2373 /* DSI non-SSC ref 19.2MHz */ in bxt_update_dpll_ref_clks()
2379 drm_dbg_kms(&i915->drm, "dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," in bxt_dump_hw_state()
2382 hw_state->ebb0, in bxt_dump_hw_state()
2383 hw_state->ebb4, in bxt_dump_hw_state()
2384 hw_state->pll0, in bxt_dump_hw_state()
2385 hw_state->pll1, in bxt_dump_hw_state()
2386 hw_state->pll2, in bxt_dump_hw_state()
2387 hw_state->pll3, in bxt_dump_hw_state()
2388 hw_state->pll6, in bxt_dump_hw_state()
2389 hw_state->pll8, in bxt_dump_hw_state()
2390 hw_state->pll9, in bxt_dump_hw_state()
2391 hw_state->pll10, in bxt_dump_hw_state()
2392 hw_state->pcsdw12); in bxt_dump_hw_state()
2465 params->kdiv = 1; in icl_wrpll_params_populate()
2468 params->kdiv = 2; in icl_wrpll_params_populate()
2471 params->kdiv = 4; in icl_wrpll_params_populate()
2479 params->pdiv = 1; in icl_wrpll_params_populate()
2482 params->pdiv = 2; in icl_wrpll_params_populate()
2485 params->pdiv = 4; in icl_wrpll_params_populate()
2488 params->pdiv = 8; in icl_wrpll_params_populate()
2496 params->qdiv_ratio = qdiv; in icl_wrpll_params_populate()
2497 params->qdiv_mode = (qdiv == 1) ? 0 : 1; in icl_wrpll_params_populate()
2501 params->dco_integer = dco >> 15; in icl_wrpll_params_populate()
2502 params->dco_fraction = dco & 0x7fff; in icl_wrpll_params_populate()
2506 * Display WA #22010492432: ehl, tgl, adl-s, adl-p
2515 i915->display.dpll.ref_clks.nssc == 38400; in ehl_combo_pll_div_frac_wa_needed()
2607 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in icl_calc_dp_combo_pll()
2609 i915->display.dpll.ref_clks.nssc == 24000 ? in icl_calc_dp_combo_pll()
2612 int clock = crtc_state->port_clock; in icl_calc_dp_combo_pll()
2623 return -EINVAL; in icl_calc_dp_combo_pll()
2629 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in icl_calc_tbt_pll()
2632 switch (i915->display.dpll.ref_clks.nssc) { in icl_calc_tbt_pll()
2634 MISSING_CASE(i915->display.dpll.ref_clks.nssc); in icl_calc_tbt_pll()
2645 switch (i915->display.dpll.ref_clks.nssc) { in icl_calc_tbt_pll()
2647 MISSING_CASE(i915->display.dpll.ref_clks.nssc); in icl_calc_tbt_pll()
2670 drm_WARN_ON(&i915->drm, 1); in icl_ddi_tbt_pll_get_freq()
2677 int ref_clock = i915->display.dpll.ref_clks.nssc; in icl_wrpll_ref_clock()
2693 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in icl_calc_wrpll()
2695 u32 afe_clock = crtc_state->port_clock * 5; in icl_calc_wrpll()
2713 dco_centrality = abs(dco - dco_mid); in icl_calc_wrpll()
2724 return -EINVAL; in icl_calc_wrpll()
2741 p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK; in icl_ddi_combo_pll_get_freq()
2742 p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK; in icl_ddi_combo_pll_get_freq()
2744 if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1)) in icl_ddi_combo_pll_get_freq()
2745 p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >> in icl_ddi_combo_pll_get_freq()
2777 dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * in icl_ddi_combo_pll_get_freq()
2780 dco_fraction = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >> in icl_ddi_combo_pll_get_freq()
2788 if (drm_WARN_ON(&i915->drm, p0 == 0 || p1 == 0 || p2 == 0)) in icl_ddi_combo_pll_get_freq()
2798 u32 dco_fraction = pll_params->dco_fraction; in icl_calc_dpll_state()
2803 pll_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(dco_fraction) | in icl_calc_dpll_state()
2804 pll_params->dco_integer; in icl_calc_dpll_state()
2806 pll_state->cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params->qdiv_ratio) | in icl_calc_dpll_state()
2807 DPLL_CFGCR1_QDIV_MODE(pll_params->qdiv_mode) | in icl_calc_dpll_state()
2808 DPLL_CFGCR1_KDIV(pll_params->kdiv) | in icl_calc_dpll_state()
2809 DPLL_CFGCR1_PDIV(pll_params->pdiv); in icl_calc_dpll_state()
2812 pll_state->cfgcr1 |= TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL; in icl_calc_dpll_state()
2814 pll_state->cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400; in icl_calc_dpll_state()
2816 if (i915->display.vbt.override_afc_startup) in icl_calc_dpll_state()
2817 pll_state->div0 = TGL_DPLL0_DIV0_AFC_STARTUP(i915->display.vbt.override_afc_startup_val); in icl_calc_dpll_state()
2836 for (div2 = 10; div2 > 0; div2--) { in icl_mg_pll_find_divisors()
2848 * working on HW for DP alt-mode at least in icl_mg_pll_find_divisors()
2878 state->mg_refclkin_ctl = MG_REFCLKIN_CTL_OD_2_MUX(1); in icl_mg_pll_find_divisors()
2880 state->mg_clktop2_coreclkctl1 = in icl_mg_pll_find_divisors()
2883 state->mg_clktop2_hsclkctl = in icl_mg_pll_find_divisors()
2893 return -EINVAL; in icl_mg_pll_find_divisors()
2898 * adapted to integer-only calculation, that's why it looks so different.
2903 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in icl_calc_mg_pll_state()
2904 int refclk_khz = i915->display.dpll.ref_clks.nssc; in icl_calc_mg_pll_state()
2905 int clock = crtc_state->port_clock; in icl_calc_mg_pll_state()
2931 return -EINVAL; in icl_calc_mg_pll_state()
2957 return -EINVAL; in icl_calc_mg_pll_state()
3008 pll_state->mg_pll_div0 = DKL_PLL_DIV0_INTEG_COEFF(int_coeff) | in icl_calc_mg_pll_state()
3012 if (i915->display.vbt.override_afc_startup) { in icl_calc_mg_pll_state()
3013 u8 val = i915->display.vbt.override_afc_startup_val; in icl_calc_mg_pll_state()
3015 pll_state->mg_pll_div0 |= DKL_PLL_DIV0_AFC_STARTUP(val); in icl_calc_mg_pll_state()
3018 pll_state->mg_pll_div1 = DKL_PLL_DIV1_IREF_TRIM(iref_trim) | in icl_calc_mg_pll_state()
3021 pll_state->mg_pll_ssc = DKL_PLL_SSC_IREF_NDIV_RATIO(iref_ndiv) | in icl_calc_mg_pll_state()
3026 pll_state->mg_pll_bias = (m2div_frac ? DKL_PLL_BIAS_FRAC_EN_H : 0) | in icl_calc_mg_pll_state()
3029 pll_state->mg_pll_tdc_coldst_bias = in icl_calc_mg_pll_state()
3034 pll_state->mg_pll_div0 = in icl_calc_mg_pll_state()
3039 pll_state->mg_pll_div1 = in icl_calc_mg_pll_state()
3045 pll_state->mg_pll_lf = in icl_calc_mg_pll_state()
3052 pll_state->mg_pll_frac_lock = in icl_calc_mg_pll_state()
3059 pll_state->mg_pll_frac_lock |= in icl_calc_mg_pll_state()
3062 pll_state->mg_pll_ssc = in icl_calc_mg_pll_state()
3070 pll_state->mg_pll_tdc_coldst_bias = in icl_calc_mg_pll_state()
3077 pll_state->mg_pll_bias = in icl_calc_mg_pll_state()
3087 pll_state->mg_pll_tdc_coldst_bias_mask = in icl_calc_mg_pll_state()
3089 pll_state->mg_pll_bias_mask = 0; in icl_calc_mg_pll_state()
3091 pll_state->mg_pll_tdc_coldst_bias_mask = -1U; in icl_calc_mg_pll_state()
3092 pll_state->mg_pll_bias_mask = -1U; in icl_calc_mg_pll_state()
3095 pll_state->mg_pll_tdc_coldst_bias &= in icl_calc_mg_pll_state()
3096 pll_state->mg_pll_tdc_coldst_bias_mask; in icl_calc_mg_pll_state()
3097 pll_state->mg_pll_bias &= pll_state->mg_pll_bias_mask; in icl_calc_mg_pll_state()
3110 ref_clock = i915->display.dpll.ref_clks.nssc; in icl_ddi_mg_pll_get_freq()
3113 m1 = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK; in icl_ddi_mg_pll_get_freq()
3115 m2_int = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBDIV_INT_MASK; in icl_ddi_mg_pll_get_freq()
3117 if (pll_state->mg_pll_bias & DKL_PLL_BIAS_FRAC_EN_H) { in icl_ddi_mg_pll_get_freq()
3118 m2_frac = pll_state->mg_pll_bias & in icl_ddi_mg_pll_get_freq()
3125 m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK; in icl_ddi_mg_pll_get_freq()
3126 m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK; in icl_ddi_mg_pll_get_freq()
3128 if (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) { in icl_ddi_mg_pll_get_freq()
3129 m2_frac = pll_state->mg_pll_div0 & in icl_ddi_mg_pll_get_freq()
3137 switch (pll_state->mg_clktop2_hsclkctl & in icl_ddi_mg_pll_get_freq()
3152 MISSING_CASE(pll_state->mg_clktop2_hsclkctl); in icl_ddi_mg_pll_get_freq()
3156 div2 = (pll_state->mg_clktop2_hsclkctl & in icl_ddi_mg_pll_get_freq()
3176 * icl_set_active_port_dpll - select the active port DPLL for a given CRTC
3187 &crtc_state->icl_port_dplls[port_dpll_id]; in icl_set_active_port_dpll()
3189 crtc_state->shared_dpll = port_dpll->pll; in icl_set_active_port_dpll()
3190 crtc_state->dpll_hw_state = port_dpll->hw_state; in icl_set_active_port_dpll()
3202 primary_port = encoder->type == INTEL_OUTPUT_DP_MST ? in icl_update_active_dpll()
3203 enc_to_mst(encoder)->primary : in icl_update_active_dpll()
3217 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in icl_compute_combo_phy_dpll()
3221 &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_compute_combo_phy_dpll()
3234 icl_calc_dpll_state(i915, &pll_params, &port_dpll->hw_state); in icl_compute_combo_phy_dpll()
3239 crtc_state->port_clock = icl_ddi_combo_pll_get_freq(i915, NULL, in icl_compute_combo_phy_dpll()
3240 &port_dpll->hw_state); in icl_compute_combo_phy_dpll()
3249 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in icl_get_combo_phy_dpll()
3253 &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_get_combo_phy_dpll()
3254 enum port port = encoder->port; in icl_get_combo_phy_dpll()
3291 port_dpll->pll = intel_find_shared_dpll(state, crtc, in icl_get_combo_phy_dpll()
3292 &port_dpll->hw_state, in icl_get_combo_phy_dpll()
3294 if (!port_dpll->pll) in icl_get_combo_phy_dpll()
3295 return -EINVAL; in icl_get_combo_phy_dpll()
3298 port_dpll->pll, &port_dpll->hw_state); in icl_get_combo_phy_dpll()
3308 struct drm_i915_private *i915 = to_i915(state->base.dev); in icl_compute_tc_phy_dplls()
3312 &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_compute_tc_phy_dplls()
3316 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_compute_tc_phy_dplls()
3321 icl_calc_dpll_state(i915, &pll_params, &port_dpll->hw_state); in icl_compute_tc_phy_dplls()
3323 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY]; in icl_compute_tc_phy_dplls()
3324 ret = icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state); in icl_compute_tc_phy_dplls()
3331 crtc_state->port_clock = icl_ddi_mg_pll_get_freq(i915, NULL, in icl_compute_tc_phy_dplls()
3332 &port_dpll->hw_state); in icl_compute_tc_phy_dplls()
3341 struct drm_i915_private *i915 = to_i915(state->base.dev); in icl_get_tc_phy_dplls()
3345 &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_get_tc_phy_dplls()
3349 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_get_tc_phy_dplls()
3350 port_dpll->pll = intel_find_shared_dpll(state, crtc, in icl_get_tc_phy_dplls()
3351 &port_dpll->hw_state, in icl_get_tc_phy_dplls()
3353 if (!port_dpll->pll) in icl_get_tc_phy_dplls()
3354 return -EINVAL; in icl_get_tc_phy_dplls()
3356 port_dpll->pll, &port_dpll->hw_state); in icl_get_tc_phy_dplls()
3359 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY]; in icl_get_tc_phy_dplls()
3361 encoder->port)); in icl_get_tc_phy_dplls()
3362 port_dpll->pll = intel_find_shared_dpll(state, crtc, in icl_get_tc_phy_dplls()
3363 &port_dpll->hw_state, in icl_get_tc_phy_dplls()
3365 if (!port_dpll->pll) { in icl_get_tc_phy_dplls()
3366 ret = -EINVAL; in icl_get_tc_phy_dplls()
3370 port_dpll->pll, &port_dpll->hw_state); in icl_get_tc_phy_dplls()
3377 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_get_tc_phy_dplls()
3378 intel_unreference_shared_dpll(state, crtc, port_dpll->pll); in icl_get_tc_phy_dplls()
3387 struct drm_i915_private *i915 = to_i915(state->base.dev); in icl_compute_dplls()
3388 enum phy phy = intel_port_to_phy(i915, encoder->port); in icl_compute_dplls()
3404 struct drm_i915_private *i915 = to_i915(state->base.dev); in icl_get_dplls()
3405 enum phy phy = intel_port_to_phy(i915, encoder->port); in icl_get_dplls()
3414 return -EINVAL; in icl_get_dplls()
3426 new_crtc_state->shared_dpll = NULL; in icl_put_dplls()
3430 &old_crtc_state->icl_port_dplls[id]; in icl_put_dplls()
3432 &new_crtc_state->icl_port_dplls[id]; in icl_put_dplls()
3434 new_port_dpll->pll = NULL; in icl_put_dplls()
3436 if (!old_port_dpll->pll) in icl_put_dplls()
3439 intel_unreference_shared_dpll(state, crtc, old_port_dpll->pll); in icl_put_dplls()
3447 const enum intel_dpll_id id = pll->info->id; in mg_pll_get_hw_state()
3464 hw_state->mg_refclkin_ctl = intel_de_read(i915, in mg_pll_get_hw_state()
3466 hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK; in mg_pll_get_hw_state()
3468 hw_state->mg_clktop2_coreclkctl1 = in mg_pll_get_hw_state()
3470 hw_state->mg_clktop2_coreclkctl1 &= in mg_pll_get_hw_state()
3473 hw_state->mg_clktop2_hsclkctl = in mg_pll_get_hw_state()
3475 hw_state->mg_clktop2_hsclkctl &= in mg_pll_get_hw_state()
3481 hw_state->mg_pll_div0 = intel_de_read(i915, MG_PLL_DIV0(tc_port)); in mg_pll_get_hw_state()
3482 hw_state->mg_pll_div1 = intel_de_read(i915, MG_PLL_DIV1(tc_port)); in mg_pll_get_hw_state()
3483 hw_state->mg_pll_lf = intel_de_read(i915, MG_PLL_LF(tc_port)); in mg_pll_get_hw_state()
3484 hw_state->mg_pll_frac_lock = intel_de_read(i915, in mg_pll_get_hw_state()
3486 hw_state->mg_pll_ssc = intel_de_read(i915, MG_PLL_SSC(tc_port)); in mg_pll_get_hw_state()
3488 hw_state->mg_pll_bias = intel_de_read(i915, MG_PLL_BIAS(tc_port)); in mg_pll_get_hw_state()
3489 hw_state->mg_pll_tdc_coldst_bias = in mg_pll_get_hw_state()
3492 if (i915->display.dpll.ref_clks.nssc == 38400) { in mg_pll_get_hw_state()
3493 hw_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART; in mg_pll_get_hw_state()
3494 hw_state->mg_pll_bias_mask = 0; in mg_pll_get_hw_state()
3496 hw_state->mg_pll_tdc_coldst_bias_mask = -1U; in mg_pll_get_hw_state()
3497 hw_state->mg_pll_bias_mask = -1U; in mg_pll_get_hw_state()
3500 hw_state->mg_pll_tdc_coldst_bias &= hw_state->mg_pll_tdc_coldst_bias_mask; in mg_pll_get_hw_state()
3501 hw_state->mg_pll_bias &= hw_state->mg_pll_bias_mask; in mg_pll_get_hw_state()
3513 const enum intel_dpll_id id = pll->info->id; in dkl_pll_get_hw_state()
3532 hw_state->mg_refclkin_ctl = intel_dkl_phy_read(i915, in dkl_pll_get_hw_state()
3534 hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK; in dkl_pll_get_hw_state()
3536 hw_state->mg_clktop2_hsclkctl = in dkl_pll_get_hw_state()
3538 hw_state->mg_clktop2_hsclkctl &= in dkl_pll_get_hw_state()
3544 hw_state->mg_clktop2_coreclkctl1 = in dkl_pll_get_hw_state()
3546 hw_state->mg_clktop2_coreclkctl1 &= in dkl_pll_get_hw_state()
3549 hw_state->mg_pll_div0 = intel_dkl_phy_read(i915, DKL_PLL_DIV0(tc_port)); in dkl_pll_get_hw_state()
3551 if (i915->display.vbt.override_afc_startup) in dkl_pll_get_hw_state()
3553 hw_state->mg_pll_div0 &= val; in dkl_pll_get_hw_state()
3555 hw_state->mg_pll_div1 = intel_dkl_phy_read(i915, DKL_PLL_DIV1(tc_port)); in dkl_pll_get_hw_state()
3556 hw_state->mg_pll_div1 &= (DKL_PLL_DIV1_IREF_TRIM_MASK | in dkl_pll_get_hw_state()
3559 hw_state->mg_pll_ssc = intel_dkl_phy_read(i915, DKL_PLL_SSC(tc_port)); in dkl_pll_get_hw_state()
3560 hw_state->mg_pll_ssc &= (DKL_PLL_SSC_IREF_NDIV_RATIO_MASK | in dkl_pll_get_hw_state()
3565 hw_state->mg_pll_bias = intel_dkl_phy_read(i915, DKL_PLL_BIAS(tc_port)); in dkl_pll_get_hw_state()
3566 hw_state->mg_pll_bias &= (DKL_PLL_BIAS_FRAC_EN_H | in dkl_pll_get_hw_state()
3569 hw_state->mg_pll_tdc_coldst_bias = in dkl_pll_get_hw_state()
3571 hw_state->mg_pll_tdc_coldst_bias &= (DKL_PLL_TDC_SSC_STEP_SIZE_MASK | in dkl_pll_get_hw_state()
3585 const enum intel_dpll_id id = pll->info->id; in icl_pll_get_hw_state()
3600 hw_state->cfgcr0 = intel_de_read(i915, ADLS_DPLL_CFGCR0(id)); in icl_pll_get_hw_state()
3601 hw_state->cfgcr1 = intel_de_read(i915, ADLS_DPLL_CFGCR1(id)); in icl_pll_get_hw_state()
3603 hw_state->cfgcr0 = intel_de_read(i915, DG1_DPLL_CFGCR0(id)); in icl_pll_get_hw_state()
3604 hw_state->cfgcr1 = intel_de_read(i915, DG1_DPLL_CFGCR1(id)); in icl_pll_get_hw_state()
3606 hw_state->cfgcr0 = intel_de_read(i915, in icl_pll_get_hw_state()
3608 hw_state->cfgcr1 = intel_de_read(i915, in icl_pll_get_hw_state()
3611 hw_state->cfgcr0 = intel_de_read(i915, in icl_pll_get_hw_state()
3613 hw_state->cfgcr1 = intel_de_read(i915, in icl_pll_get_hw_state()
3615 if (i915->display.vbt.override_afc_startup) { in icl_pll_get_hw_state()
3616 hw_state->div0 = intel_de_read(i915, TGL_DPLL0_DIV0(id)); in icl_pll_get_hw_state()
3617 hw_state->div0 &= TGL_DPLL0_DIV0_AFC_STARTUP_MASK; in icl_pll_get_hw_state()
3622 hw_state->cfgcr0 = intel_de_read(i915, in icl_pll_get_hw_state()
3624 hw_state->cfgcr1 = intel_de_read(i915, in icl_pll_get_hw_state()
3627 hw_state->cfgcr0 = intel_de_read(i915, in icl_pll_get_hw_state()
3629 hw_state->cfgcr1 = intel_de_read(i915, in icl_pll_get_hw_state()
3659 struct intel_dpll_hw_state *hw_state = &pll->state.hw_state; in icl_dpll_write()
3660 const enum intel_dpll_id id = pll->info->id; in icl_dpll_write()
3687 intel_de_write(i915, cfgcr0_reg, hw_state->cfgcr0); in icl_dpll_write()
3688 intel_de_write(i915, cfgcr1_reg, hw_state->cfgcr1); in icl_dpll_write()
3689 drm_WARN_ON_ONCE(&i915->drm, i915->display.vbt.override_afc_startup && in icl_dpll_write()
3691 if (i915->display.vbt.override_afc_startup && in icl_dpll_write()
3694 TGL_DPLL0_DIV0_AFC_STARTUP_MASK, hw_state->div0); in icl_dpll_write()
3701 struct intel_dpll_hw_state *hw_state = &pll->state.hw_state; in icl_mg_pll_write()
3702 enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id); in icl_mg_pll_write()
3711 MG_REFCLKIN_CTL_OD_2_MUX_MASK, hw_state->mg_refclkin_ctl); in icl_mg_pll_write()
3715 hw_state->mg_clktop2_coreclkctl1); in icl_mg_pll_write()
3722 hw_state->mg_clktop2_hsclkctl); in icl_mg_pll_write()
3724 intel_de_write(i915, MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0); in icl_mg_pll_write()
3725 intel_de_write(i915, MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1); in icl_mg_pll_write()
3726 intel_de_write(i915, MG_PLL_LF(tc_port), hw_state->mg_pll_lf); in icl_mg_pll_write()
3728 hw_state->mg_pll_frac_lock); in icl_mg_pll_write()
3729 intel_de_write(i915, MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc); in icl_mg_pll_write()
3732 hw_state->mg_pll_bias_mask, hw_state->mg_pll_bias); in icl_mg_pll_write()
3735 hw_state->mg_pll_tdc_coldst_bias_mask, in icl_mg_pll_write()
3736 hw_state->mg_pll_tdc_coldst_bias); in icl_mg_pll_write()
3744 struct intel_dpll_hw_state *hw_state = &pll->state.hw_state; in dkl_pll_write()
3745 enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id); in dkl_pll_write()
3755 val |= hw_state->mg_refclkin_ctl; in dkl_pll_write()
3760 val |= hw_state->mg_clktop2_coreclkctl1; in dkl_pll_write()
3768 val |= hw_state->mg_clktop2_hsclkctl; in dkl_pll_write()
3772 if (i915->display.vbt.override_afc_startup) in dkl_pll_write()
3775 hw_state->mg_pll_div0); in dkl_pll_write()
3780 val |= hw_state->mg_pll_div1; in dkl_pll_write()
3788 val |= hw_state->mg_pll_ssc; in dkl_pll_write()
3794 val |= hw_state->mg_pll_bias; in dkl_pll_write()
3800 val |= hw_state->mg_pll_tdc_coldst_bias; in dkl_pll_write()
3817 drm_err(&i915->drm, "PLL %d Power not enabled\n", in icl_pll_power_enable()
3818 pll->info->id); in icl_pll_power_enable()
3829 drm_err(&i915->drm, "PLL %d not locked\n", pll->info->id); in icl_pll_enable()
3837 pll->info->id != DPLL_ID_ICL_DPLL0) in adlp_cmtg_clock_gating_wa()
3840 * Wa_16011069516:adl-p[a0] in adlp_cmtg_clock_gating_wa()
3852 if (drm_WARN_ON(&i915->drm, val & ~DISABLE_DPT_CLK_GATING)) in adlp_cmtg_clock_gating_wa()
3853 drm_dbg_kms(&i915->drm, "Unexpected flags in TRANS_CMTG_CHICKEN: %08x\n", val); in adlp_cmtg_clock_gating_wa()
3935 drm_err(&i915->drm, "PLL %d locked\n", pll->info->id); in icl_pll_disable()
3946 drm_err(&i915->drm, "PLL %d Power not disabled\n", in icl_pll_disable()
3947 pll->info->id); in icl_pll_disable()
3974 /* No SSC ref */ in icl_update_dpll_ref_clks()
3975 i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; in icl_update_dpll_ref_clks()
3981 drm_dbg_kms(&i915->drm, in icl_dump_hw_state()
3988 hw_state->cfgcr0, hw_state->cfgcr1, in icl_dump_hw_state()
3989 hw_state->div0, in icl_dump_hw_state()
3990 hw_state->mg_refclkin_ctl, in icl_dump_hw_state()
3991 hw_state->mg_clktop2_coreclkctl1, in icl_dump_hw_state()
3992 hw_state->mg_clktop2_hsclkctl, in icl_dump_hw_state()
3993 hw_state->mg_pll_div0, in icl_dump_hw_state()
3994 hw_state->mg_pll_div1, in icl_dump_hw_state()
3995 hw_state->mg_pll_lf, in icl_dump_hw_state()
3996 hw_state->mg_pll_frac_lock, in icl_dump_hw_state()
3997 hw_state->mg_pll_ssc, in icl_dump_hw_state()
3998 hw_state->mg_pll_bias, in icl_dump_hw_state()
3999 hw_state->mg_pll_tdc_coldst_bias); in icl_dump_hw_state()
4163 * intel_shared_dpll_init - Initialize shared DPLLs
4174 mutex_init(&i915->display.dpll.lock); in intel_shared_dpll_init()
4205 dpll_info = dpll_mgr->dpll_info; in intel_shared_dpll_init()
4208 if (drm_WARN_ON(&i915->drm, in intel_shared_dpll_init()
4209 i >= ARRAY_SIZE(i915->display.dpll.shared_dplls))) in intel_shared_dpll_init()
4213 if (drm_WARN_ON(&i915->drm, dpll_info[i].id >= 32)) in intel_shared_dpll_init()
4216 i915->display.dpll.shared_dplls[i].info = &dpll_info[i]; in intel_shared_dpll_init()
4217 i915->display.dpll.shared_dplls[i].index = i; in intel_shared_dpll_init()
4220 i915->display.dpll.mgr = dpll_mgr; in intel_shared_dpll_init()
4221 i915->display.dpll.num_shared_dpll = i; in intel_shared_dpll_init()
4225 * intel_compute_shared_dplls - compute DPLL state CRTC and encoder combination
4242 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_compute_shared_dplls()
4243 const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr; in intel_compute_shared_dplls()
4245 if (drm_WARN_ON(&i915->drm, !dpll_mgr)) in intel_compute_shared_dplls()
4246 return -EINVAL; in intel_compute_shared_dplls()
4248 return dpll_mgr->compute_dplls(state, crtc, encoder); in intel_compute_shared_dplls()
4252 * intel_reserve_shared_dplls - reserve DPLLs for CRTC and encoder combination
4275 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_reserve_shared_dplls()
4276 const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr; in intel_reserve_shared_dplls()
4278 if (drm_WARN_ON(&i915->drm, !dpll_mgr)) in intel_reserve_shared_dplls()
4279 return -EINVAL; in intel_reserve_shared_dplls()
4281 return dpll_mgr->get_dplls(state, crtc, encoder); in intel_reserve_shared_dplls()
4285 * intel_release_shared_dplls - end use of DPLLs by CRTC in atomic state
4298 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_release_shared_dplls()
4299 const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr; in intel_release_shared_dplls()
4310 dpll_mgr->put_dplls(state, crtc); in intel_release_shared_dplls()
4314 * intel_update_active_dpll - update the active DPLL for a CRTC/encoder
4327 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_update_active_dpll()
4328 const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr; in intel_update_active_dpll()
4330 if (drm_WARN_ON(&i915->drm, !dpll_mgr)) in intel_update_active_dpll()
4333 dpll_mgr->update_active_dpll(state, crtc, encoder); in intel_update_active_dpll()
4337 * intel_dpll_get_freq - calculate the DPLL's output frequency
4348 if (drm_WARN_ON(&i915->drm, !pll->info->funcs->get_freq)) in intel_dpll_get_freq()
4351 return pll->info->funcs->get_freq(i915, pll, pll_state); in intel_dpll_get_freq()
4355 * intel_dpll_get_hw_state - readout the DPLL's hardware state
4366 return pll->info->funcs->get_hw_state(i915, pll, hw_state); in intel_dpll_get_hw_state()
4374 pll->on = intel_dpll_get_hw_state(i915, pll, &pll->state.hw_state); in readout_dpll_hw_state()
4376 if (pll->on && pll->info->power_domain) in readout_dpll_hw_state()
4377 pll->wakeref = intel_display_power_get(i915, pll->info->power_domain); in readout_dpll_hw_state()
4379 pll->state.pipe_mask = 0; in readout_dpll_hw_state()
4380 for_each_intel_crtc(&i915->drm, crtc) { in readout_dpll_hw_state()
4382 to_intel_crtc_state(crtc->base.state); in readout_dpll_hw_state()
4384 if (crtc_state->hw.active && crtc_state->shared_dpll == pll) in readout_dpll_hw_state()
4385 intel_reference_shared_dpll_crtc(crtc, pll, &pll->state); in readout_dpll_hw_state()
4387 pll->active_mask = pll->state.pipe_mask; in readout_dpll_hw_state()
4389 drm_dbg_kms(&i915->drm, in readout_dpll_hw_state()
4391 pll->info->name, pll->state.pipe_mask, pll->on); in readout_dpll_hw_state()
4396 if (i915->display.dpll.mgr && i915->display.dpll.mgr->update_ref_clks) in intel_dpll_update_ref_clks()
4397 i915->display.dpll.mgr->update_ref_clks(i915); in intel_dpll_update_ref_clks()
4412 if (!pll->on) in sanitize_dpll_state()
4417 if (pll->active_mask) in sanitize_dpll_state()
4420 drm_dbg_kms(&i915->drm, in sanitize_dpll_state()
4422 pll->info->name); in sanitize_dpll_state()
4437 * intel_dpll_dump_hw_state - write hw_state to dmesg
4446 if (i915->display.dpll.mgr) { in intel_dpll_dump_hw_state()
4447 i915->display.dpll.mgr->dump_hw_state(i915, hw_state); in intel_dpll_dump_hw_state()
4452 drm_dbg_kms(&i915->drm, in intel_dpll_dump_hw_state()
4455 hw_state->dpll, in intel_dpll_dump_hw_state()
4456 hw_state->dpll_md, in intel_dpll_dump_hw_state()
4457 hw_state->fp0, in intel_dpll_dump_hw_state()
4458 hw_state->fp1); in intel_dpll_dump_hw_state()
4474 drm_dbg_kms(&i915->drm, "%s\n", pll->info->name); in verify_single_dpll_state()
4478 if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) { in verify_single_dpll_state()
4479 I915_STATE_WARN(i915, !pll->on && pll->active_mask, in verify_single_dpll_state()
4481 I915_STATE_WARN(i915, pll->on && !pll->active_mask, in verify_single_dpll_state()
4483 I915_STATE_WARN(i915, pll->on != active, in verify_single_dpll_state()
4485 pll->on, active); in verify_single_dpll_state()
4490 pll->active_mask & ~pll->state.pipe_mask, in verify_single_dpll_state()
4492 pll->active_mask, pll->state.pipe_mask); in verify_single_dpll_state()
4497 pipe_mask = BIT(crtc->pipe); in verify_single_dpll_state()
4499 if (new_crtc_state->hw.active) in verify_single_dpll_state()
4500 I915_STATE_WARN(i915, !(pll->active_mask & pipe_mask), in verify_single_dpll_state()
4502 pipe_name(crtc->pipe), pll->active_mask); in verify_single_dpll_state()
4504 I915_STATE_WARN(i915, pll->active_mask & pipe_mask, in verify_single_dpll_state()
4506 pipe_name(crtc->pipe), pll->active_mask); in verify_single_dpll_state()
4508 I915_STATE_WARN(i915, !(pll->state.pipe_mask & pipe_mask), in verify_single_dpll_state()
4510 pipe_mask, pll->state.pipe_mask); in verify_single_dpll_state()
4513 pll->on && memcmp(&pll->state.hw_state, &dpll_hw_state, in verify_single_dpll_state()
4521 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_shared_dpll_state_verify()
4527 if (new_crtc_state->shared_dpll) in intel_shared_dpll_state_verify()
4528 verify_single_dpll_state(i915, new_crtc_state->shared_dpll, in intel_shared_dpll_state_verify()
4531 if (old_crtc_state->shared_dpll && in intel_shared_dpll_state_verify()
4532 old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) { in intel_shared_dpll_state_verify()
4533 u8 pipe_mask = BIT(crtc->pipe); in intel_shared_dpll_state_verify()
4534 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll; in intel_shared_dpll_state_verify()
4536 I915_STATE_WARN(i915, pll->active_mask & pipe_mask, in intel_shared_dpll_state_verify()
4538 pipe_name(crtc->pipe), pll->active_mask); in intel_shared_dpll_state_verify()
4539 I915_STATE_WARN(i915, pll->state.pipe_mask & pipe_mask, in intel_shared_dpll_state_verify()
4541 pipe_name(crtc->pipe), pll->state.pipe_mask); in intel_shared_dpll_state_verify()
4547 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_shared_dpll_verify_disabled()