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/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Dmti,gic.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Burton <paulburton@kernel.org>
11 - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
15 It also supports local (per-processor) interrupts and software-generated
16 interrupts which can be used as IPIs. The GIC also includes a free-running
17 global timer, per-CPU count/compare timers, and a watchdog.
23 "#interrupt-cells":
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/linux-5.10/arch/ia64/include/asm/
Dhw_irq.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (C) 2001-2003 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
23 * 1,3-14 are reserved from firmware
25 * 16-255 (vectored external interrupts) are available
37 #define AUTO_ASSIGN -1
42 * Vectors 0x10-0x1f are used for low priority interrupts, e.g. CMCI.
45 #define IA64_CMCP_VECTOR 0x1d /* corrected machine-check polling vector */
47 #define IA64_CMC_VECTOR 0x1f /* corrected machine-check interrupt vector */
49 * Vectors 0x20-0x2f are reserved for legacy ISA IRQs.
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/linux-5.10/Documentation/devicetree/bindings/powerpc/
Dibm,powerpc-cpu-features.txt3 (skiboot/doc/device-tree/ibm,powerpc-cpu-features/binding.txt)
9 ibm,powerpc-cpu-features binding
12 This device tree binding describes CPU features available to software, with
19 /cpus/ibm,powerpc-cpu-features node binding
20 -------------------------------------------
22 Node: ibm,powerpc-cpu-features
24 Description: Container of CPU feature nodes.
26 The node name must be "ibm,powerpc-cpu-features".
35 - compatible
38 Definition: "ibm,powerpc-cpu-features"
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/linux-5.10/arch/xtensa/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
47 Xtensa processors are 32-bit RISC machines designed by Tensilica
52 a home page at <http://www.linux-xtensa.org/>.
96 bool "fsf - default (not generic) configuration"
100 bool "dc232b - Diamond 232L Standard Core Rev.B (LE)"
107 bool "dc233c - Diamond 233L Standard Core Rev.C (LE)"
143 ie: it supports a TLB with auto-loading, page protection.
185 This option is used to indicate that the system-on-a-chip (SOC)
187 the CPU core definition and currently needs to be selected manually.
199 bool "Enable Symmetric multi-processing support"
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/linux-5.10/arch/m68k/
DKconfig.machine1 # SPDX-License-Identifier: GPL-2.0
21 This option enables support for the 68000-based Atari series of
44 Say Y here if you want to run Linux on an MC680x0-based Apollo
63 build a kernel which can run on MVME147 single-board computers. If
118 The Q40 is a Motorola 68040-based successor to the Sinclair QL
121 Q60. Select your CPU below. For 68LC060 don't forget to enable FPU
179 Disable the CPU internal registers protection in user mode,
270 Support for the Sysam AMCORE open-hardware generic board.
276 Support for the Sysam stmark2 open-hardware generic board.
309 bool "Netburner MOD-5272 board support"
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/linux-5.10/drivers/irqchip/
Dirq-mips-gic.c6 * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
10 #define pr_fmt(fmt) "irq-mips-gic: " fmt
24 #include <asm/mips-cps.h>
28 #include <dt-bindings/interrupt-controller/mips-gic.h>
33 /* Add 2 to convert GIC CPU pin to core interrupt */
42 #define GIC_HWIRQ_TO_LOCAL(x) ((x) - GIC_LOCAL_HWIRQ_BASE)
45 #define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE)
102 irq -= GIC_PIN_TO_VEC_OFFSET; in gic_bind_eic_interrupt()
108 static void gic_send_ipi(struct irq_data *d, unsigned int cpu) in gic_send_ipi() argument
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/linux-5.10/arch/xtensa/include/asm/
Dmmu_context.h8 * Copyright (C) 2001 - 2013 Tensilica Inc.
23 #include <asm/vectors.h>
27 #include <asm-generic/mm_hooks.h>
28 #include <asm-generic/percpu.h>
35 #define cpu_asid_cache(cpu) per_cpu(asid_cache, cpu) argument
39 * any user or kernel context. We use the reserved values in the
44 * 2 reserved
45 * 3 reserved
51 #define ASID_MASK ((1 << XCHAL_MMU_ASID_BITS) - 1)
70 static inline void get_new_mmu_context(struct mm_struct *mm, unsigned int cpu) in get_new_mmu_context() argument
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/linux-5.10/kernel/irq/
Dmatrix.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/cpu.h>
43 * irq_alloc_matrix - Allocate a irq_matrix structure and initialize it
62 m->matrix_bits = matrix_bits; in irq_alloc_matrix()
63 m->alloc_start = alloc_start; in irq_alloc_matrix()
64 m->alloc_end = alloc_end; in irq_alloc_matrix()
65 m->alloc_size = alloc_end - alloc_start; in irq_alloc_matrix()
66 m->maps = alloc_percpu(*m->maps); in irq_alloc_matrix()
67 if (!m->maps) { in irq_alloc_matrix()
75 * irq_matrix_online - Bring the local CPU matrix online
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/linux-5.10/arch/x86/kernel/apic/
Dvector.c1 // SPDX-License-Identifier: GPL-2.0-only
30 unsigned int cpu; member
67 info->mask = mask; in init_irq_alloc_info()
83 while (irqd->parent_data) in apic_chip_data()
84 irqd = irqd->parent_data; in apic_chip_data()
86 return irqd->chip_data; in apic_chip_data()
93 return apicd ? &apicd->hw_irq_cfg : NULL; in irqd_cfg()
108 INIT_HLIST_NODE(&apicd->clist); in alloc_apic_chip_data()
118 unsigned int cpu) in apic_update_irq_cfg() argument
124 apicd->hw_irq_cfg.vector = vector; in apic_update_irq_cfg()
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/linux-5.10/Documentation/arm/
Dmemory.rst13 The ARM CPU is capable of addressing a maximum of 4GB virtual memory
30 ffff1000 ffff7fff Reserved.
33 ffff0000 ffff0fff CPU vector page.
34 The CPU vectors are mapped here if the
35 CPU supports vector relocation (control
39 in proc-xscale.S to flush the whole data
43 DTCM mounted inside the CPU.
46 ITCM mounted inside the CPU.
54 VMALLOC_START VMALLOC_END-1 vmalloc() / ioremap() space.
63 PAGE_OFFSET high_memory-1 Kernel direct-mapped RAM region.
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/linux-5.10/arch/arc/kernel/
Dentry-arcv2.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * ARCv2 ISA based core Low Level Intr/Traps/Exceptions(non-TLB) Handling
16 ; first 16 lines are reserved for exceptions and are not configurable.
19 .cpu HS
28 # Initial 16 slots are Exception Vectors
43 VECTOR reserved ; Reserved slots
44 VECTOR reserved ; Reserved slots
46 # Begin Interrupt Vectors
57 .rept NR_CPU_IRQS - 8
63 reserved: label
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/linux-5.10/arch/x86/include/asm/
Dsegment.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 ((((base) & _AC(0xff000000,ULL)) << (56-24)) | \
15 (((limit) & _AC(0x000f0000,ULL)) << (48-16)) | \
60 * The layout of the per-CPU GDT under Linux:
62 * 0 - null <=== cacheline #1
63 * 1 - reserved
64 * 2 - reserved
65 * 3 - reserved
67 * 4 - unused <=== cacheline #2
68 * 5 - unused
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/linux-5.10/Documentation/filesystems/
Dxfs-delayed-logging-design.rst1 .. SPDX-License-Identifier: GPL-2.0
7 Introduction to Re-logging in XFS
12 logged are made up of the changes to in-core structures rather than on-disk
13 structures. Other objects - typically buffers - have their physical changes
24 "re-logging". Conceptually, this is quite simple - all it requires is that any
48 (increasing) LSN of each subsequent transaction - the LSN is effectively a
51 This relogging is also used to implement long-running, multiple-commit
65 the log - repeated operations to the same objects write the same changes to
74 doing aggregation of transactions in memory - batching them, if you like - to
79 buffers available and the size of each is 32kB - the size can be increased up
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/linux-5.10/arch/arm64/kvm/
Darm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
84 if (cap->flags) in kvm_vm_ioctl_enable_cap()
85 return -EINVAL; in kvm_vm_ioctl_enable_cap()
87 switch (cap->cap) { in kvm_vm_ioctl_enable_cap()
90 kvm->arch.return_nisv_io_abort_to_user = true; in kvm_vm_ioctl_enable_cap()
93 r = -EINVAL; in kvm_vm_ioctl_enable_cap()
109 * Although this is a per-CPU feature, we make it global because in set_default_csv2()
116 kvm->arch.pfr0_csv2 = 1; in set_default_csv2()
120 * kvm_arch_init_vm - initializes a VM data structure
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/linux-5.10/arch/powerpc/include/asm/
Dreg.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * number used in the Programming Environments Manual For 32-Bit
17 #include <asm/asm-const.h>
18 #include <asm/feature-fixups.h>
76 /* so tests for these bits fail on 32-bit */
119 #define MSR_TS_N 0 /* Non-transactional */
123 #define MSR_TM_RESV(x) (((x) & MSR_TS_MASK) == MSR_TS_MASK) /* Reserved */
164 /* Power Management - Processor Stop Status and Control Register Fields */
168 #define PSSCR_PSLL_MASK 0x000F0000 /* Power-Saving Level Limit */
172 #define PSSCR_PLS 0xf000000000000000 /* Power-saving Level Status */
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/linux-5.10/drivers/infiniband/hw/efa/
Defa_main.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 * Copyright 2018-2020 Amazon.com, Inc. or its affiliates. All rights reserved.
43 ibdev_err(&dev->ibdev, in unimplemented_aenq_handler()
51 atomic64_inc(&dev->stats.keep_alive_rcvd); in efa_keep_alive()
63 struct pci_dev *pdev = dev->pdev; in efa_release_bars()
74 efa_com_admin_q_comp_intr_handler(&dev->edev); in efa_intr_msix_mgmnt()
75 efa_com_aenq_intr_handler(&dev->edev, data); in efa_intr_msix_mgmnt()
85 irq = &dev->admin_irq; in efa_request_mgmnt_irq()
86 err = request_irq(irq->vector, irq->handler, 0, irq->name, in efa_request_mgmnt_irq()
87 irq->data); in efa_request_mgmnt_irq()
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/linux-5.10/arch/powerpc/kernel/
Dhead_book3s_32.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
9 * Low-level exception handlers and MMU support
14 * This file contains the low-level support and setup for the
28 #include <asm/asm-offsets.h>
33 #include <asm/feature-fixups.h>
38 /* see the comment for clear_bats() -- Cort */ \
66 * -- Cort
78 * pointer (r1) points to just below the end of the half-meg region
79 * from 0x380000 - 0x400000, which is mapped in already.
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Dhead_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
9 * Low-level exception handlers and MMU support
16 * This file contains the entry point for the 64-bit kernel along
17 * with some early initialization code common to all 64-bit powerpc
27 #include <asm/head-64.h>
28 #include <asm/asm-offsets.h>
41 #include <asm/ppc-opcode.h>
43 #include <asm/feature-fixups.h>
46 * spin code sits at 0x0000...0x00ff. On server, the vectors follow
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/linux-5.10/arch/arm64/kernel/
Dhead.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Low-level CPU initialisation
6 * Copyright (C) 1994-2002 Russell King
7 * Copyright (C) 2003-2012 ARM Ltd.
14 #include <linux/irqchip/arm-gic-v3.h>
21 #include <asm/asm-offsets.h>
26 #include <asm/kernel-pgtable.h>
29 #include <asm/pgtable-hwdef.h>
37 #include "efi-header.S"
47 * ---------------------------
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Dentry.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Low-level exception handling code
10 #include <linux/arm-smccc.h>
16 #include <asm/asm-offsets.h>
29 #include <asm/asm-uaccess.h>
56 *-----------------
86 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp
88 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0
89 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp
111 * after panic() re-enables interrupts.
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/linux-5.10/drivers/net/ethernet/intel/fm10k/
Dfm10k_main.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2019 Intel Corporation. */
18 "Copyright(c) 2013 - 2019 Intel Corporation.";
28 * fm10k_init_module - Driver Registration Routine
42 return -ENOMEM; in fm10k_init_module()
51 * fm10k_exit_module - Driver Exit Cleanup Routine
70 struct page *page = bi->page; in fm10k_alloc_mapped_page()
80 rx_ring->rx_stats.alloc_failed++; in fm10k_alloc_mapped_page()
85 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); in fm10k_alloc_mapped_page()
90 if (dma_mapping_error(rx_ring->dev, dma)) { in fm10k_alloc_mapped_page()
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/linux-5.10/fs/xfs/
Dxfs_log_priv.h1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2000-2003,2005 Silicon Graphics, Inc.
4 * All Rights Reserved.
63 * By covering, we mean changing the h_tail_lsn in the last on-disk
64 * log write such that no allocation transactions will be re-done during
65 * recovery after a system crash. Recovery starts at the last on-disk
69 * space allocation transactions which can undo non-transactional changes
82 * non-dummy transaction. The first dummy changes the h_tail_lsn to
91 * IDLE -- no logging has been done on the file system or
93 * NEED -- logging has occurred and we need a dummy transaction
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/linux-5.10/arch/mips/include/asm/netlogic/xlp-hal/
Dpic.h2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
69 #define PIC_IRT_RVEC 20 /* Interrupt receive vectors */
229 int sch, int vec, int dt, int db, int cpu) in nlm_9xx_pic_write_irt() argument
236 (cpu & 0x3ff); in nlm_9xx_pic_write_irt()
257 int sch, int vec, int cpu) in nlm_pic_write_irt_direct() argument
261 1, 0, cpu); in nlm_pic_write_irt_direct()
264 (cpu >> 4), /* thread group */ in nlm_pic_write_irt_direct()
265 1 << (cpu & 0xf)); /* thread mask */ in nlm_pic_write_irt_direct()
287 nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu) in nlm_pic_set_timer() argument
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/linux-5.10/arch/powerpc/sysdev/
Dmpic.c9 * Copyright 2010-2012 Freescale Semiconductor, Inc.
150 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
160 unsigned int cpu = 0; in mpic_processor_id() local
162 if (!(mpic->flags & MPIC_SECONDARY)) in mpic_processor_id()
163 cpu = hard_smp_processor_id(); in mpic_processor_id()
165 return cpu; in mpic_processor_id()
180 return dcr_read(rb->dhost, reg); in _mpic_read()
183 return in_be32(rb->base + (reg >> 2)); in _mpic_read()
186 return in_le32(rb->base + (reg >> 2)); in _mpic_read()
197 dcr_write(rb->dhost, reg, value); in _mpic_write()
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/linux-5.10/arch/arm/mach-sa1100/
Dgeneric.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-sa1100/generic.c
15 #include <linux/dma-mapping.h>
23 #include <linux/irqchip/irq-sa11x0.h>
70 unsigned int sa11x0_getspeed(unsigned int cpu) in sa11x0_getspeed() argument
72 if (cpu) in sa11x0_getspeed()
78 * Default power-off for SA1100
86 /* enable wake-up on GPIO0 (Assabet...) */ in sa1100_power_off()
105 /* Use on-chip reset capability */ in sa11x0_restart()
113 dev->dev.platform_data = data; in sa11x0_register_device()
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