Lines Matching +full:reserved +full:- +full:cpu +full:- +full:vectors
1 # SPDX-License-Identifier: GPL-2.0
47 Xtensa processors are 32-bit RISC machines designed by Tensilica
52 a home page at <http://www.linux-xtensa.org/>.
96 bool "fsf - default (not generic) configuration"
100 bool "dc232b - Diamond 232L Standard Core Rev.B (LE)"
107 bool "dc233c - Diamond 233L Standard Core Rev.C (LE)"
143 ie: it supports a TLB with auto-loading, page protection.
185 This option is used to indicate that the system-on-a-chip (SOC)
187 the CPU core definition and currently needs to be selected manually.
199 bool "Enable Symmetric multi-processing support"
203 Enabled SMP Software; allows more than one CPU/CORE
208 int "Maximum number of CPUs (2-32)"
213 bool "Enable CPU hotplug support"
217 controlled through /sys/devices/system/cpu.
219 Say N if you want to disable CPU hotplug.
300 On some platforms (XT2000, for example), the CPU clock rate can
327 XT2000 is the name of Tensilica's feature-rich emulation platform.
349 int "CPU clock rate [MHz]"
356 The BogoMIPS value can easily be derived from the CPU frequency.
368 architectures, you should supply some command-line options at build
393 tristate "Host file-based simulated block device support"
402 int "Number of host file-based simulated block devices"
425 Another simulated disk in a host file for a buildroot-independent
450 bool "Use 8-bit access to XTFPGA LCD"
454 LCD may be connected with 4- or 8-bit interface, 8-bit access may
455 only be used with 8-bit interface. Please consult prototyping user
471 This unfortunately won't work for U-Boot and likely also wont
477 xt-gdb can't place a Software Breakpoint in the 0XD region prior
485 Selecting this will cause U-Boot to set the KERNEL Load and Entry
491 bool "Kernel Execute-In-Place from ROM"
494 Execute-In-Place allows the kernel to run from non-volatile storage
495 directly addressable by the CPU, such as NOR flash. This saves RAM
497 to RAM. Read-write sections, such as the data section and stack,
518 region: bits 0..3 -- for addresses 0x00000000..0x1fffffff,
519 bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on.
534 3: special (c and e are illegal, f is reserved).
538 2: WB, no-write-allocate cache,
549 Unpacked kernel image (including vectors) must be located completely
578 prompt "Relocatable vectors location"
581 Choose whether relocatable vectors are merged into the kernel .text
583 configurations without VECBASE register where vectors are always
584 placed at their hardware-defined locations.
587 bool "Merge relocatable vectors into kernel text"
590 This option puts relocatable vectors into the kernel .text section
595 bool "Put relocatable vectors at fixed address"
597 This option puts relocatable vectors at specific virtual address.
598 Vectors are merged with the .init data in the kernel image and
600 Use it to put vectors into IRAM or out of FLASH on kernels with
601 XIP-aware MTD support.
606 hex "Kernel vectors virtual address"
610 This is the virtual address of the (relocatable) vectors base.