arm64/kernel/head.S

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * Low-level CPU initialisation
6  * Copyright (C) 1994-2002 Russell King
7  * Copyright (C) 2003-2012 ARM Ltd.
14 #include <linux/irqchip/arm-gic-v3.h>
21 #include <asm/asm-offsets.h>
26 #include <asm/kernel-pgtable.h>
29 #include <asm/pgtable-hwdef.h>
37 #include "efi-header.S"
47  * ---------------------------
50  *   MMU = off, D-cache = off, I-cache = on or off,
56  * Note that the callee-saved registers are used for storing variables
63 	 * DO NOT MODIFY. Image header expected by Linux boot-loaders.
74 	.long	0				// reserved
76 	.quad	0				// Image load offset from start of RAM, little-endian
77 	le64sym	_kernel_size_le			// Effective size of kernel image, little-endian
78 	le64sym	_kernel_flags_le		// Informative flags, little-endian
79 	.quad	0				// reserved
80 	.quad	0				// reserved
81 	.quad	0				// reserved
84 	.long	pe_header - _head		// Offset to the PE header.
89 	.long	0				// reserved
109 	and	x23, x23, MIN_KIMG_ALIGN - 1	// KASLR offset, defaults to 0
113 	 * The following calls CPU setup code, see arch/arm64/mm/proc.S for
115 	 * On return, the CPU will be ready for the MMU to be turned on and
149  * Returns:	tbl -> next level table page address
169  *	eindex:	end index to write - [index, eindex] written to
210 	and	\iend, \iend, \istart	// iend = (vend >> shift) & (ptrs - 1)
213 	add	\iend, \iend, \istart	// iend += (count - 1) * ptrs
232  *	vend:	end address to map - we map [vstart, vend]
234  *	phys:	physical address corresponding to vstart - physical memory is contiguous
237  * Temporaries:	istart, iend, tmp, count, sv - these need to be different registers
264 	bic \count, \phys, #SWAPPER_BLOCK_SIZE - 1
271  *   - identity mapping to enable the MMU (low address, TTBR0)
272  *   - first few MB of the kernel linear mapping to jump to once the MMU has
331 	 * entire ID map region can be mapped. As T0SZ == (64 - #bits used),
346 #define EXTRA_SHIFT	(PGDIR_SHIFT + PAGE_SHIFT - 3)
347 #define EXTRA_PTRS	(1 << (PHYS_MASK_SHIFT - EXTRA_SHIFT))
365 	 * translation level, but the top-level table has more entries.
367 	mov	x4, #1 << (PHYS_MASK_SHIFT - PGDIR_SHIFT)
386 	sub	x6, x6, x3			// _end - _text
392 	 * Since the page tables have been populated with non-cacheable
426 	adr_l	x8, vectors			// load VBAR_EL1 with virtual
430 	stp	xzr, x30, [sp, #-16]!
455 	tst	x23, ~(MIN_KIMG_ALIGN - 1)	// already running randomized?
498 	mov	w0, #BOOT_CPU_MODE_EL1		// This cpu booted in EL1
508 	 * x2 being non-zero indicates that we do have VHE, and that the
526 	 * Allow Non-secure EL1 and EL0 to access physical timer and counter.
606 	/* Stage-2 translation */
611 	mov	w0, #BOOT_CPU_MODE_EL2		// This CPU booted in EL2
620 	 * requires no configuration, and all non-hyp-specific EL2 setup
650 	mov	w0, #BOOT_CPU_MODE_EL2		// This CPU booted in EL2
655  * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed
663 1:	str	w0, [x1]			// This CPU has booted in EL1
677  * We need to find out the CPU boot mode long after boot, so we need to
680  * This is not in .bss, because we set it sufficiently early that the boot-time
688  * The booting CPU updates the failed status @__early_cpu_boot_status,
738 	adr_l	x5, vectors
767  * The booting CPU updates the failed status @__early_cpu_boot_status,
771  *  - Corrupts tmp1, tmp2
772  *  - Writes 'status' to __early_cpu_boot_status and makes sure
793  * Checks if the selected granule size is supported by the CPU.
794  * If it isn't, park the CPU
812 	 * Invalidate the local I-cache so that any instructions fetched
843 	/* Indicate that this CPU can't boot and is stuck in the kernel */
869 	ldr	x14, [x9, #-8]
895 	 * Excluding the least significant bit in the bitmap, each non-zero
901 	 * a single bitmap can encode up to 63 relocations in a 64-bit object.
911 	 * __relocate_kernel is called twice with non-zero displacements (i.e.
989 	msr	sctlr_el1, x19			// re-enable the MMU