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/qemu/hw/arm/
H A Dxlnx-versal-virt.c13 #include "qemu/error-report.h"
20 #include "hw/qdev-properties.h"
21 #include "hw/arm/xlnx-versal.h"
26 #define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt")
61 s->fdt = create_device_tree(&s->fdt_size); in fdt_create()
62 if (!s->fdt) { in fdt_create()
68 s->phandle.gic = qemu_fdt_alloc_phandle(s->fdt); in fdt_create()
69 for (i = 0; i < ARRAY_SIZE(s->phandle.ethernet_phy); i++) { in fdt_create()
70 s->phandle.ethernet_phy[i] = qemu_fdt_alloc_phandle(s->fdt); in fdt_create()
72 s->phandle.clk_25Mhz = qemu_fdt_alloc_phandle(s->fdt); in fdt_create()
[all …]
/qemu/tests/qtest/
H A Dtest-x86-cpuid-compat.c6 #include "libqtest-single.h"
15 resp = qmp("{'execute': 'query-cpus-fast', 'arguments': {}}"); in get_cpu0_qom_path()
20 path = g_strdup(qdict_get_str(cpu0, "qom-path")); in get_cpu0_qom_path()
27 QDict *resp = qmp("{ 'execute': 'qom-get'," in qom_get()
59 qtest_start(args->cmdline); in test_cpuid_prop()
61 value = qobject_to(QNum, qom_get(path, args->property)); in test_cpuid_prop()
63 g_assert_cmpint(val, ==, args->expected_value); in test_cpuid_prop()
81 cmdline = g_strdup_printf("-cpu %s", cpu); in add_cpuid_test()
90 cmdline = g_strdup_printf("-machine %s %s", machine, cmdline); in add_cpuid_test()
93 args->cmdline = cmdline; in add_cpuid_test()
[all …]
/qemu/hw/riscv/
H A Dsifive_u.c2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
15 * 5) OTP (One-Time Programmable) memory with stored serial number
39 #include "qemu/error-report.h"
99 uint64_t mem_size = ms->ram_size; in create_fdt()
111 "sifive,plic-1.0.0", "riscv,plic0" in create_fdt()
114 fdt = ms->fdt = create_device_tree(&s->fdt_size); in create_fdt()
122 "sifive,hifive-unleashed-a00"); in create_fdt()
123 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); in create_fdt()
124 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); in create_fdt()
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/qemu/target/xtensa/
H A Dcore-lx106.c13 * names of its contributors may be used to endorse or promote products
31 #include "qemu/host-utils.h"
33 #include "core-lx106/core-isa.h"
37 #include "core-lx106/xtensa-modules.c.inc"
42 .reg = {
43 #include "core-lx106/gdb-config.c.inc"
H A Dcore-dc232b.c13 * names of its contributors may be used to endorse or promote products
31 #include "qemu/host-utils.h"
34 #include "core-dc232b/core-isa.h"
38 #include "core-dc232b/xtensa-modules.c.inc"
43 .reg = {
44 #include "core-dc232b/gdb-config.c.inc"
H A Dcore-de212.c13 * names of its contributors may be used to endorse or promote products
31 #include "qemu/host-utils.h"
33 #include "core-de212/core-isa.h"
37 #include "core-de212/xtensa-modules.c.inc"
42 .reg = {
43 #include "core-de212/gdb-config.c.inc"
H A Dcore-dc233c.c13 * names of its contributors may be used to endorse or promote products
31 #include "qemu/host-utils.h"
33 #include "core-dc233c/core-isa.h"
37 #include "core-dc233c/xtensa-modules.c.inc"
42 .reg = {
43 #include "core-dc233c/gdb-config.c.inc"
H A Dcore-test_kc705_be.c13 * names of its contributors may be used to endorse or promote products
31 #include "qemu/host-utils.h"
33 #include "core-test_kc705_be/core-isa.h"
37 #include "core-test_kc705_be/xtensa-modules.c.inc"
42 .reg = {
43 #include "core-test_kc705_be/gdb-config.c.inc"
H A Dcore-test_mmuhifi_c3.c13 * names of its contributors may be used to endorse or promote products
31 #include "qemu/host-utils.h"
33 #include "core-test_mmuhifi_c3/core-isa.h"
37 #include "core-test_mmuhifi_c3/xtensa-modules.c.inc"
42 .reg = {
43 #include "core-test_mmuhifi_c3/gdb-config.c.inc"
H A Dcore-sample_controller.c13 * names of its contributors may be used to endorse or promote products
31 #include "qemu/host-utils.h"
33 #include "core-sample_controller/core-isa.h"
37 #include "core-sample_controller/xtensa-modules.c.inc"
42 .reg = {
43 #include "core-sample_controller/gdb-config.c.inc"
H A Dcore-fsf.c13 * names of its contributors may be used to endorse or promote products
31 #include "qemu/host-utils.h"
33 #include "core-fsf/core-isa.h"
37 #include "core-fsf/xtensa-modules.c.inc"
43 .reg = {
H A Dcore-de233_fpu.c13 * names of its contributors may be used to endorse or promote products
31 #include "qemu/host-utils.h"
33 #include "core-de233_fpu/core-isa.h"
34 #include "core-de233_fpu/core-matmap.h"
38 #include "core-de233_fpu/xtensa-modules.c.inc"
43 .reg = {
44 #include "core-de233_fpu/gdb-config.c.inc"
H A Dcore-dsp3400.c13 * names of its contributors may be used to endorse or promote products
31 #include "qemu/host-utils.h"
33 #include "core-dsp3400/core-isa.h"
34 #include "core-dsp3400/core-matmap.h"
38 #include "core-dsp3400/xtensa-modules.c.inc"
43 .reg = {
44 #include "core-dsp3400/gdb-config.c.inc"
/qemu/target/i386/
H A Dcpu-internal.h2 * i386 CPU internal definitions to be shared between cpu.c and cpu-system.c
30 /* feature flags names are taken from "Intel Processor Identification and
42 int reg; /* output register (R_* constant) */ member
52 /* Features that shouldn't be auto-enabled by "-cpu host" */
/qemu/hw/scsi/
H A Dlsi53c895a.c13 * as well-behaved operating systems will not try to use them.
28 static const char *names[] = { variable
304 uint32_t scratch[18]; /* SCRATCHA-SCRATCHR */
334 return (s->sien0 & LSI_SIST0_RSL) && (s->scid & LSI_SCID_RRE); in lsi_irq_on_rsl()
341 QTAILQ_FOREACH(p, &s->queue, next) { in get_pending_req()
342 if (p->pending) { in get_pending_req()
352 s->carry = 0; in lsi_soft_reset()
354 s->msg_action = LSI_MSG_ACTION_COMMAND; in lsi_soft_reset()
355 s->msg_len = 0; in lsi_soft_reset()
356 s->waiting = LSI_NOWAIT; in lsi_soft_reset()
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/qemu/tests/tcg/multiarch/gdbstub/
H A Dregisters.py4 # This is launched via tests/guest-debug/run-test.py but you can also
7 # SPDX-License-Identifier: GPL-2.0-or-later
22 reg_map hash containing the names, regnums and initial values of
31 xml = gdb.execute("maint print xml-tdesc", False, True)
42 regs = f.findall("reg")
47 top = int(regs[-1].attrib["regnum"])
82 Cross-check the list of remote-registers with the XML info.
85 remote = gdb.execute("maint print remote-registers", False, True)
129 print(f"xml-tdesc has {total_regs} registers")
130 print(f"remote-registers has {total_r_regs} registers")
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/qemu/docs/specs/
H A Dfw_cfg.rst5 Guest-side Hardware Interface
15 ---------------------------
19 * Width: 16-bit
20 * Endianness: little-endian (if IOport), or big-endian (if MMIO)
34 the selector value is between 0x4000-0x7fff or 0xc000-0xffff.
38 longer supported, and will be ignored (treated as no-ops)!
49 items are accessed with a selector value between 0x0000-0x7fff, and
51 value between 0x8000-0xffff.
54 -------------
58 * Width: 8-bit (if IOport), 8/16/32/64-bit (if MMIO)
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/qemu/target/hexagon/idef-parser/
H A Didef-parser.lex2 %option 8bit reentrant bison-bridge
4 %option bison-locations
8 * Copyright(c) 2019-2023 rev.ng Labs Srl. All Rights Reserved.
29 #include "idef-parser.h"
30 #include "idef-parser.tab.h"
33 #define YY_USER_ACTION yylloc->first_column = yylloc->last_column; \
35 yylloc->last_column++; \
44 DIGIT [0-9]
45 LOWER_ID [a-z]
46 UPPER_ID [A-Z]
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/qemu/pc-bios/dtb/
H A Dcanyonlands.dts4 * Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
34 reg = <0x00000000>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
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/qemu/docs/devel/testing/
H A Dqgraph.rst29 so the sdhci-test should only care of linking its qgraph node with
34 ---------------
45 - **QNODE_MACHINE**: for example ``arm/raspi2b``
46 - **QNODE_DRIVER**: for example ``generic-sdhci``
47 - **QNODE_INTERFACE**: for example ``sdhci`` (interface for all ``-sdhci``
54 - **QNODE_TEST**: for example ``sdhci-test``. A test consumes an interface
59 - QNODE_MACHINE: each machine struct must have a ``QGuestAllocator`` and
63 - QNODE_DRIVER: driver names must be unique, and machines and nodes
72 - ``X CONSUMES Y``: ``Y`` can be plugged into ``X``
73 - ``X PRODUCES Y``: ``X`` provides the interface ``Y``
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/qemu/include/hw/xen/interface/
H A Dphysdev.h1 /* SPDX-License-Identifier: MIT */
15 * @args == Operation-specific extra arguments (NULL if none).
19 * Notify end-of-interrupt (EOI) for the specified IRQ.
88 * Set the current VCPU's I/O-port permissions bitmap.
105 * Read or write an IO-APIC register.
113 uint32_t reg; member
150 /* IN - high 16 bits hold segment for ..._MSI_SEG and ..._MULTI_MSI */
295 * MSI-X capable devices won't (prepare) or may (release) change.
327 * Notify that some PIRQ-bound event channels have been unmasked.
335 * These all-capitals physdev operation names are superceded by the new names
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/qemu/hw/core/
H A Dsysbus-fdt.c30 #include "hw/core/sysbus-fdt.h"
31 #include "qemu/error-report.h"
34 #include "hw/platform-bus.h"
35 #include "hw/vfio/vfio-platform.h"
36 #include "hw/vfio/vfio-calxeda-xgmac.h"
37 #include "hw/vfio/vfio-amd-xgbe.h"
38 #include "hw/vfio/vfio-region.h"
40 #include "hw/uefi/var-service-api.h"
103 if (props[i].optional && prop_len == -FDT_ERR_NOTFOUND) { in copy_properties_from_host()
121 {"#clock-cells", false},
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/qemu/disas/
H A Dmicroblaze.c138 /* mask is reg num - max_reg_num, ie reg_num - 32 in this case */
163 #define REG_MSR 33 /* machine status reg */
164 #define REG_EAR 35 /* Exception reg */
165 #define REG_ESR 37 /* Exception reg */
166 #define REG_FSR 39 /* FPU Status reg */
167 #define REG_BTR 43 /* Branch Target reg */
168 #define REG_EDR 45 /* Exception reg */
169 #define REG_PVR 40960 /* Program Verification reg */
171 #define REG_PID 36864 /* MMU: Process ID reg */
172 #define REG_ZPR 36865 /* MMU: Zone Protect reg */
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/qemu/hw/xtensa/
H A Dmx_pic.c2 * Copyright (c) 2013 - 2019, Max Filippov, Open Source and Linux Lab.
13 * names of its contributors may be used to endorse or promote products
68 MemoryRegion reg; member
76 struct XtensaMxPic *mx = mx_cpu->mx; in xtensa_mx_pic_ext_reg_read()
79 return mx->mirout[offset - MIROUT]; in xtensa_mx_pic_ext_reg_read()
81 return mx->cpu[offset - MIPICAUSE].mipicause; in xtensa_mx_pic_ext_reg_read()
85 return mx->mieng; in xtensa_mx_pic_ext_reg_read()
88 return mx->miasg; in xtensa_mx_pic_ext_reg_read()
91 return mx->mipipart; in xtensa_mx_pic_ext_reg_read()
94 return ((mx->n_cpu - 1) << 18) | (mx_cpu - mx->cpu); in xtensa_mx_pic_ext_reg_read()
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/qemu/target/arm/
H A Dcpregs.h18 * <http://www.gnu.org/licenses/gpl-2.0.html>
25 #include "target/arm/kvm-consts.h"
52 /* Flag: For ARM_CP_STATE_AA32, sysreg is 64-bit. */
92 * Flag: Writes to the sysreg might change the exception level - typically
93 * on older ARM chips. For those cases we need to re-read the new el when
111 * - UNDEF: discard the cpreg,
112 * - KEEP: retain the cpreg as is,
113 * - C_NZ: set const on the cpreg, but retain resetvalue,
114 * - else: set const on the cpreg, zero resetvalue, aka RES0.
153 * non-secure/secure bank (AArch32 only)
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