18  * <http://www.gnu.org/licenses/gpl-2.0.html>
25 #include "target/arm/kvm-consts.h"
52     /* Flag: For ARM_CP_STATE_AA32, sysreg is 64-bit. */
92      * Flag: Writes to the sysreg might change the exception level - typically
93      * on older ARM chips. For those cases we need to re-read the new el when
111      *   - UNDEF: discard the cpreg,
112      *   -  KEEP: retain the cpreg as is,
113      *   -  C_NZ: set const on the cpreg, but retain resetvalue,
114      *   -  else: set const on the cpreg, zero resetvalue, aka RES0.
153  *  non-secure/secure bank (AArch32 only)
173  * To enable banking of coprocessor registers depending on ns-bit we
174  * add a bit to distinguish between secure and non-secure cpregs in the
208          * KVM is always non-secure so add the NS flag on AArch32 register  in kvm_to_cpreg_id()
257  * The existence of both or neither secure and non-secure flags indicates that
258  * the register has both a secure and non-secure hash entry.  A single one of
263  * or non-secure.
268     ARM_CP_SECSTATE_NS =  (1 << 1), /* bit[1]: Non-secure state register */
273  * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
279  * (ie anything visible in PL2 is visible in S-PL1, some things are only
280  * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
300      * For user-mode some registers are accessible to EL0 via a kernel
301      * trap-and-emulate ABI. In this case we define the read permissions
343      * Note that this is not a catch-all case -- the set of cases which may
411 /* 51-53: RES0 */
414 /* 56-63: RES0 */
637 /* Which fine-grained trap bit register to check, if any */
646  * bit names across the various FGT registers.
648 #define DO_BIT(REG, BITNAME)                                    \  argument
649     FGT_##BITNAME = FGT_##REG | R_##REG##_EL2_##BITNAME##_SHIFT
652 #define DO_REV_BIT(REG, BITNAME)                                        \  argument
653     FGT_##BITNAME = FGT_##REG | FGT_REV | R_##REG##_EL2_##BITNAME##_SHIFT
662 #define DO_TLBINXS_BIT(REG, BITNAME)                             \  argument
663     FGT_##BITNAME = FGT_##REG | R_##REG##_EL2_##BITNAME##_SHIFT, \
675      * with the corresponding HFGWTR/HDFGTWTR bit being RES0, and vice-versa
693      * it as trap-on-writes.
868      * 'wildcard' field -- any value of that field in the MRC/MCR insn
875      * For AArch64-visible registers, opc0 is also used.
877      * way to distinguish (for KVM's benefit) guest-visible system registers
898      * Which fine-grained trap register bit to check, if any. This
917      * fieldoffset is non-zero, the reset value of the register.
929      * Offsets of the secure and non-secure fields in CPUARMState for the
965      * readfn and it has side effects (for instance clear-on-read bits).
972      * writefn and it masks out "unwritable" bits or has write-one-to-clear
985      * For ARMv8.1-VHE register aliases, we overwrite the read/write
1003     (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
1005     (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
1007 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, const ARMCPRegInfo *reg,
1031  * Definition of an ARM co-processor register as viewed from
1062 /* CPWriteFn that can be used to implement writes-ignored behaviour */
1065 /* CPReadFn that can be used for read-as-zero behaviour */
1068 /* CPWriteFn that just writes the value to ri->fieldoffset */
1083     return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);  in cpreg_field_is_64bit()
1089     return (ri->access >> ((current_el * 2) + isread)) & 1;  in cp_access_ok()
1114     return ri->state == ARM_CP_STATE_AA64 &&  in arm_cpreg_in_idspace()
1115         arm_cpreg_encoding_in_idspace(ri->opc0, ri->opc1, ri->opc2,  in arm_cpreg_in_idspace()
1116                                       ri->crn, ri->crm);  in arm_cpreg_in_idspace()
1137      * their names (I_TZTZL). However the underlying principle is "if  in arm_cpreg_traps_in_nv()
1145      * that we do not consistently use the right architectural names  in arm_cpreg_traps_in_nv()
1158     return ri->opc1 == 4 || ri->opc1 == 5;  in arm_cpreg_traps_in_nv()
1163     ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
1168             (_env)->cp15._regname##_s = (_val);                 \
1170             (_env)->cp15._regname##_ns = (_val);                \