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/qemu/docs/
H A Drdma.txt151 infiniband receiver side, whereas RDMA messages (used
162 on the receiver side is registered and pinned, we're
170 receiver must have reserved space (using a receive
178 1. Receiver and Sender are started (command line or libvirt):
180 3. Receiver does listen()
182 5. Receiver accept()
245 from the receiver to tell us that the receiver
362 the sender and the receiver populate the list of RAMBlocks
/qemu/hw/char/
H A Dstm32l4x5_usart.c2 * STM32L4X5 USART (Universal Synchronous Asynchronous Receiver Transmitter)
38 FIELD(CR1, RTOIE, 26, 1) /* Receiver timeout interrupt enable */
45 FIELD(CR1, WAKE, 11, 1) /* Receiver wakeup method */
54 FIELD(CR1, RE, 2, 1) /* Receiver enable */
60 FIELD(CR2, RTOEN, 23, 1) /* Receiver timeout enable */
93 FIELD(CR3, DMAR, 6, 1) /* DMA enable receiver */
107 FIELD(RTOR, RTO, 0, 24) /* Receiver timeout value */
119 FIELD(ISR, RWU, 19, 1) /* Receiver wakeup from Mute mode */
126 FIELD(ISR, RTOF, 11, 1) /* Receiver timeout */
142 FIELD(ICR, RTOCF, 11, 1) /* Receiver timeout clear flag */
H A Davr_usart.c121 /* Receiver disabled, ignore. */ in avr_usart_read()
207 /* Receiver disabled, flush input buffer. */ in avr_usart_write()
H A Dmcf_uart.c150 case 2: /* Reset receiver. */ in mcf_do_command()
187 /* Receiver command. */ in mcf_do_command()
H A Dserial.c44 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
46 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
53 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
54 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
88 #define UART_LSR_DR 0x01 /* Receiver data ready */
H A Dnrf51_uart.c5 * Receiver/Transmitter" for hardware specifications:
H A Dtrace-events124 stm32l4x5_usart_receiver_not_enabled(uint8_t ue_bit, uint8_t re_bit) "USART: Receiver not enabled, …
/qemu/net/
H A Dfilter-buffer.c49 * for the next filter or receiver to notify us that it can receive in filter_buffer_release_timer()
75 * For some reason, receiver could not receive more packets in filter_buffer_receive_iov()
79 * the packets without caring about the receiver. This is suboptimal. in filter_buffer_receive_iov()
H A Dfilter.c76 /* no receiver, or sender been deleted, no need to pass it further */ in qemu_netfilter_pass_to_next()
108 * We have gone through all filters, pass it to receiver. in qemu_netfilter_pass_to_next()
109 * Do the valid check again in case sender or receiver been in qemu_netfilter_pass_to_next()
118 /* no receiver, or sender been deleted */ in qemu_netfilter_pass_to_next()
H A Dtap-linux.c133 * to other guests on the same host, the receiver
/qemu/include/hw/char/
H A Dimx_serial.h43 #define USR1_RRDY (1<<9) /* receiver ready */
46 #define USR1_RXDS (1<<6) /* Receiver is idle */
74 #define UCR2_RXEN (1<<1) /* Receiver enable */
H A Dstm32l4x5_usart.h2 * STM32L4X5 USART (Universal Synchronous Asynchronous Receiver Transmitter)
/qemu/tests/qtest/
H A Dstm32l4x5_usart-test.c195 /* Enable the transmitter, the receiver and the USART. */ in init_uart()
314 /* Disable the transmitter and receiver. */ in test_ack()
318 /* Test ISR ACK for transmitter and receiver disabled */ in test_ack()
323 /* Enable the transmitter and receiver. */ in test_ack()
327 /* Test ISR ACK for transmitter and receiver disabled */ in test_ack()
/qemu/include/hw/net/
H A Dmii.h104 #define MII_STAT1000_LOK (1 << 13) /* Local Receiver Status */
105 #define MII_STAT1000_ROK (1 << 12) /* Remote Receiver Status */
/qemu/hw/net/
H A Dne2000.c94 #define ENISR_RX 0x01 /* Receiver, no error */
96 #define ENISR_RX_ERR 0x04 /* Receiver, with error */
98 #define ENISR_OVER 0x10 /* Receiver overwrote the ring */
111 #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
H A Drtl8139.c787 * rings after the receiver were enabled. */
839 /* first check if receiver is enabled */ in rtl8139_do_receive()
843 DPRINTF("receiver disabled ================\n"); in rtl8139_do_receive()
946 /* begin C+ receiver mode */ in rtl8139_do_receive()
1131 /* begin ring receiver mode */ in rtl8139_do_receive()
1134 /* if receiver buffer is empty then avail == 0 */ in rtl8139_do_receive()
1360 DPRINTF("ChipCmd enable receiver\n"); in rtl8139_ChipCmd_write()
1386 DPRINTF("receiver buffer data available 0x%04x\n", unread); in rtl8139_RxBufferEmpty()
1390 DPRINTF("receiver buffer is empty\n"); in rtl8139_RxBufferEmpty()
H A De1000_regs.h121 #define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */
/qemu/include/hw/display/
H A Ddpcd.h68 /* Receiver port capability. */
/qemu/rust/qemu-api/src/
H A Dqom.rs303 /// Return the receiver as a mutable raw pointer to Object.
314 /// Return the receiver as a mutable raw pointer to Object.
465 /// Return the receiver as an Object. This is always safe, even
471 /// Return the receiver as a const raw pointer to Object.
478 /// Return the receiver as a mutable raw pointer to Object.
/qemu/qapi/
H A Dcxl.json252 # @receiver-overflow: Buffer overflows (first 3 bits of header log
276 'receiver-overflow',
/qemu/docs/devel/migration/
H A Dqatzip-compression.rst137 - Receiver memory usage
/qemu/include/hw/intc/
H A Darm_gicv3_common.h101 * independently in the CPU and in the GIC. In that case the receiver should
/qemu/hw/arm/
H A Dstrongarm.c908 #define UTSR0_RID (1 << 2) /* Receiver Idle */
909 #define UTSR0_RBB (1 << 3) /* Receiver begin break */
910 #define UTSR0_REB (1 << 4) /* Receiver end break */
/qemu/migration/
H A Dmultifd-qatzip.c290 error_setg(errp, "multifd %u: [receiver] %s", p->id, err_msg); in qatzip_recv_setup()
/qemu/include/hw/xen/interface/io/
H A Dring.h289 * is a boolean return value. True indicates that the receiver requires an

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