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/linux-6.15/Documentation/devicetree/bindings/dvfs/
Dperformance-domain.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dvfs/performance-domain.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic performance domains
10 - Sudeep Holla <sudeep.holla@arm.com>
13 This binding is intended for performance management of groups of devices or
14 CPUs that run in the same performance domain. Performance domains must not
15 be confused with power domains. A performance domain is defined by a set
16 of devices that always have to run at the same performance level. For a given
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/linux-6.15/arch/arm64/boot/dts/apple/
Dt6002.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
15 #include "multi-die-cpp.h"
17 #include "t600x-common.dtsi"
20 compatible = "apple,t6002", "apple,arm-platform";
22 #address-cells = <2>;
23 #size-cells = <2>;
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Dt600x-common.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
18 cpu-map {
63 enable-method = "spin-table";
64 cpu-release-addr = <0 0>; /* To be filled by loader */
65 next-level-cache = <&l2_cache_0>;
66 i-cache-size = <0x20000>;
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Dt8015.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
16 interrupt-parent = <&aic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
20 clkref: clock-ref {
21 compatible = "fixed-clock";
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Dt8011.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
16 interrupt-parent = <&aic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
20 clkref: clock-ref {
21 compatible = "fixed-clock";
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Dt7001.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/apple-aic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/pinctrl/apple.h>
15 interrupt-parent = <&aic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
23 clkref: clock-ref {
24 compatible = "fixed-clock";
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Ds5l8960x.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/apple-aic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/pinctrl/apple.h>
17 interrupt-parent = <&aic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
21 clkref: clock-ref {
22 compatible = "fixed-clock";
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Dt8103.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
16 compatible = "apple,t8103", "apple,arm-platform";
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <2>;
23 #size-cells = <0>;
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Ds800-0-3.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
16 interrupt-parent = <&aic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
20 clkref: clock-ref {
21 compatible = "fixed-clock";
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Dt7000.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/apple-aic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/pinctrl/apple.h>
17 interrupt-parent = <&aic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
21 clkref: clock-ref {
22 compatible = "fixed-clock";
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Dt8010.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
16 interrupt-parent = <&aic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
20 clkref: clock-ref {
21 compatible = "fixed-clock";
[all …]
Dt8112.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
14 #include <dt-bindings/spmi/spmi.h>
17 compatible = "apple,t8112", "apple,arm-platform";
19 #address-cells = <2>;
20 #size-cells = <2>;
23 #address-cells = <2>;
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Ds8001.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
16 interrupt-parent = <&aic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
20 clkref: clock-ref {
21 compatible = "fixed-clock";
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/linux-6.15/Documentation/devicetree/bindings/cpufreq/
Dapple,cluster-cpufreq.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/apple,cluster-cpufreq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
13 Apple SoCs (e.g. M1) have a per-cpu-cluster DVFS controller that is part of
15 operating-points-v2 table to define the CPU performance states, with the
16 opp-level property specifying the hardware p-state index for that level.
21 - items:
22 - enum:
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Dqemu,virtual-cpufreq.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/qemu,virtual-cpufreq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David Dai <davidai@google.com>
11 - Saravana Kannan <saravanak@google.com>
14 Virtual CPUFreq is a virtualized driver in guest kernels that sends performance
16 is associated with a performance domain which can be shared with other vCPUs.
17 Each performance domain has its own set of registers for performance controls.
21 const: qemu,virtual-cpufreq
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Dcpufreq-mediatek-hw.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/cpufreq-mediatek-hw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Yuan <hector.yuan@mediatek.com>
19 const: mediatek,cpufreq-hw
29 "#performance-domain-cells":
31 Number of cells in a performance domain specifier.
33 performance domains.
37 - compatible
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/linux-6.15/Documentation/scheduler/
Dsched-energy.rst6 ---------------
25 please refer to its documentation (see Documentation/power/energy-model.rst).
29 -----------------------------
32 - energy = [joule] (resource like a battery on powered devices)
33 - power = energy/time = [joule/second] = [watt]
38 performance [inst/s]
39 --------------------
45 -----------
48 while still getting 'good' performance. It is essentially an alternative
49 optimization objective to the current performance-only objective for the
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/linux-6.15/Documentation/arch/powerpc/
Dassociativity.rst6 domains of substantially similar mean performance relative to resources outside
8 performance relative to each other than relative to other resources subsets
9 are represented as being members of a sub-grouping domain. This performance
11 From the platform view, these groups are also referred to as domains.
17 Hypervisor indicates the type/form of associativity used via "ibm,architecture-vec-5 property".
18 Bit 0 of byte 5 in the "ibm,architecture-vec-5" property indicates usage of Form 0 or Form 1.
20 bit 2 of byte 5 in the "ibm,architecture-vec-5" property is used.
23 ------
27 ------
28 With Form 1 a combination of ibm,associativity-reference-points, and ibm,associativity
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/linux-6.15/drivers/pmdomain/qcom/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "Qualcomm PM Domains"
18 be called qcom-cpr
24 QCOM RPMh Power domain driver to support power-domains with
25 performance states. The driver communicates a performance state
36 QCOM RPM Power domain driver to support power-domains with
37 performance states. The driver communicates a performance state
/linux-6.15/Documentation/devicetree/bindings/power/
Dpower-domain.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/power-domain.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic PM domains
10 - Rafael J. Wysocki <rjw@rjwysocki.net>
11 - Kevin Hilman <khilman@kernel.org>
12 - Ulf Hansson <ulf.hansson@linaro.org>
15 System on chip designs are often divided into multiple PM domains that can be
17 leakage current. Moreover, in some cases the similar PM domains may also be
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/linux-6.15/drivers/pmdomain/arm/
Dscmi_perf_domain.c1 // SPDX-License-Identifier: GPL-2.0
3 * SCMI performance domain support.
32 if (!pd->info->set_perf) in scmi_pd_set_perf_state()
36 return -EINVAL; in scmi_pd_set_perf_state()
38 ret = pd->perf_ops->level_set(pd->ph, pd->domain_id, state, false); in scmi_pd_set_perf_state()
40 dev_warn(&genpd->dev, "Failed with %d when trying to set %d perf level", in scmi_pd_set_perf_state()
54 * the performance level can be changed. in scmi_pd_attach_dev()
56 if (!pd->info->set_perf) in scmi_pd_attach_dev()
59 ret = pd->perf_ops->device_opps_add(pd->ph, dev, pd->domain_id); in scmi_pd_attach_dev()
71 if (!pd->info->set_perf) in scmi_pd_detach_dev()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "SCMI performance domain driver"
8 This enables support for the SCMI performance domains which can be
20 This enables support for the SCMI power domains which can be
33 This enables support for the SCPI power domains which can be
/linux-6.15/drivers/base/power/
Dcommon.c1 // SPDX-License-Identifier: GPL-2.0
3 * drivers/base/power/common.c - Common device power management code.
19 * dev_pm_get_subsys_data - Create or refcount power.subsys_data for device.
32 return -ENOMEM; in dev_pm_get_subsys_data()
34 spin_lock_irq(&dev->power.lock); in dev_pm_get_subsys_data()
36 if (dev->power.subsys_data) { in dev_pm_get_subsys_data()
37 dev->power.subsys_data->refcount++; in dev_pm_get_subsys_data()
39 spin_lock_init(&psd->lock); in dev_pm_get_subsys_data()
40 psd->refcount = 1; in dev_pm_get_subsys_data()
41 dev->power.subsys_data = psd; in dev_pm_get_subsys_data()
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/linux-6.15/Documentation/power/
Denergy-model.rst1 .. SPDX-License-Identifier: GPL-2.0
8 -----------
11 the power consumed by devices at various performance levels, and the kernel
12 subsystems willing to use that information to make energy-aware decisions.
18 each and every client subsystem to re-implement support for each and every
23 The power values might be expressed in micro-Watts or in an 'abstract scale'.
26 can be found in the Energy-Aware Scheduler documentation
27 Documentation/scheduler/sched-energy.rst. For some subsystems like thermal or
30 thus the real micro-Watts might be needed. An example of these requirements can
32 Documentation/driver-api/thermal/power_allocator.rst.
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/linux-6.15/Documentation/devicetree/bindings/clock/
Dqcom,x1e80100-camcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,x1e80100-camcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bryan O'Donoghue <bryan.odonoghue@linaro.org>
14 domains on x1e80100.
17 include/dt-bindings/clock/qcom,x1e80100-camcc.h
20 - $ref: qcom,gcc.yaml#
25 - qcom,x1e80100-camcc
32 - description: Camera AHB clock from GCC
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