1// SPDX-License-Identifier: GPL-2.0 OR MIT 2/* 3 * Apple T8010 "A10" SoC 4 * 5 * Other names: H9P, "Cayman" 6 * 7 * Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org> 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/apple-aic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/pinctrl/apple.h> 14 15/ { 16 interrupt-parent = <&aic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 clkref: clock-ref { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <24000000>; 24 clock-output-names = "clkref"; 25 }; 26 27 cpus { 28 #address-cells = <2>; 29 #size-cells = <0>; 30 31 cpu0: cpu@0 { 32 compatible = "apple,hurricane-zephyr"; 33 reg = <0x0 0x0>; 34 cpu-release-addr = <0 0>; /* To be filled by loader */ 35 operating-points-v2 = <&fusion_opp>; 36 performance-domains = <&cpufreq>; 37 enable-method = "spin-table"; 38 device_type = "cpu"; 39 }; 40 41 cpu1: cpu@1 { 42 compatible = "apple,hurricane-zephyr"; 43 reg = <0x0 0x1>; 44 cpu-release-addr = <0 0>; /* To be filled by loader */ 45 operating-points-v2 = <&fusion_opp>; 46 performance-domains = <&cpufreq>; 47 enable-method = "spin-table"; 48 device_type = "cpu"; 49 }; 50 }; 51 52 fusion_opp: opp-table { 53 compatible = "operating-points-v2"; 54 55 /* 56 * Apple Fusion Architecture: Hardware big.LITTLE switcher 57 * that use p-state transitions to switch between cores. 58 * Only one type of core can be active at a given time. 59 * 60 * The E-core frequencies are adjusted so performance scales 61 * linearly with reported clock speed. 62 */ 63 64 opp01 { 65 opp-hz = /bits/ 64 <172000000>; /* 300 MHz, E-core */ 66 opp-level = <1>; 67 clock-latency-ns = <11000>; 68 }; 69 opp02 { 70 opp-hz = /bits/ 64 <230000000>; /* 396 MHz, E-core */ 71 opp-level = <2>; 72 clock-latency-ns = <49000>; 73 }; 74 opp03 { 75 opp-hz = /bits/ 64 <425000000>; /* 732 MHz, E-core */ 76 opp-level = <3>; 77 clock-latency-ns = <13000>; 78 }; 79 opp04 { 80 opp-hz = /bits/ 64 <637000000>; /* 1092 MHz, E-core */ 81 opp-level = <4>; 82 clock-latency-ns = <18000>; 83 }; 84 opp05 { 85 opp-hz = /bits/ 64 <756000000>; 86 opp-level = <5>; 87 clock-latency-ns = <35000>; 88 }; 89 opp06 { 90 opp-hz = /bits/ 64 <1056000000>; 91 opp-level = <6>; 92 clock-latency-ns = <31000>; 93 }; 94 opp07 { 95 opp-hz = /bits/ 64 <1356000000>; 96 opp-level = <7>; 97 clock-latency-ns = <37000>; 98 }; 99 opp08 { 100 opp-hz = /bits/ 64 <1644000000>; 101 opp-level = <8>; 102 clock-latency-ns = <39500>; 103 }; 104 hurricane_opp09: opp09 { 105 opp-hz = /bits/ 64 <1944000000>; 106 opp-level = <9>; 107 clock-latency-ns = <46000>; 108 status = "disabled"; /* Not available on N112 */ 109 }; 110 hurricane_opp10: opp10 { 111 opp-hz = /bits/ 64 <2244000000>; 112 opp-level = <10>; 113 clock-latency-ns = <56000>; 114 status = "disabled"; /* Not available on N112 */ 115 }; 116#if 0 117 /* Not available until CPU deep sleep is implemented */ 118 hurricane_opp11: opp11 { 119 opp-hz = /bits/ 64 <2340000000>; 120 opp-level = <11>; 121 clock-latency-ns = <56000>; 122 turbo-mode; 123 status = "disabled"; /* Not available on N112 */ 124 }; 125#endif 126 }; 127 128 soc { 129 compatible = "simple-bus"; 130 #address-cells = <2>; 131 #size-cells = <2>; 132 nonposted-mmio; 133 ranges; 134 135 cpufreq: performance-controller@202f20000 { 136 compatible = "apple,t8010-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; 137 reg = <0x2 0x02f20000 0 0x1000>; 138 #performance-domain-cells = <0>; 139 }; 140 141 serial0: serial@20a0c0000 { 142 compatible = "apple,s5l-uart"; 143 reg = <0x2 0x0a0c0000 0x0 0x4000>; 144 reg-io-width = <4>; 145 interrupt-parent = <&aic>; 146 interrupts = <AIC_IRQ 218 IRQ_TYPE_LEVEL_HIGH>; 147 /* Use the bootloader-enabled clocks for now. */ 148 clocks = <&clkref>, <&clkref>; 149 clock-names = "uart", "clk_uart_baud0"; 150 power-domains = <&ps_uart0>; 151 status = "disabled"; 152 }; 153 154 pmgr: power-management@20e000000 { 155 compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 156 #address-cells = <1>; 157 #size-cells = <1>; 158 159 reg = <0x2 0xe000000 0 0x8c000>; 160 }; 161 162 aic: interrupt-controller@20e100000 { 163 compatible = "apple,t8010-aic", "apple,aic"; 164 reg = <0x2 0x0e100000 0x0 0x100000>; 165 #interrupt-cells = <3>; 166 interrupt-controller; 167 power-domains = <&ps_aic>; 168 }; 169 170 dwi_bl: backlight@20e200080 { 171 compatible = "apple,t8010-dwi-bl", "apple,dwi-bl"; 172 reg = <0x2 0x0e200080 0x0 0x8>; 173 power-domains = <&ps_dwi>; 174 status = "disabled"; 175 }; 176 177 pinctrl_ap: pinctrl@20f100000 { 178 compatible = "apple,t8010-pinctrl", "apple,pinctrl"; 179 reg = <0x2 0x0f100000 0x0 0x100000>; 180 power-domains = <&ps_gpio>; 181 182 gpio-controller; 183 #gpio-cells = <2>; 184 gpio-ranges = <&pinctrl_ap 0 0 208>; 185 apple,npins = <208>; 186 187 interrupt-controller; 188 #interrupt-cells = <2>; 189 interrupt-parent = <&aic>; 190 interrupts = <AIC_IRQ 42 IRQ_TYPE_LEVEL_HIGH>, 191 <AIC_IRQ 43 IRQ_TYPE_LEVEL_HIGH>, 192 <AIC_IRQ 44 IRQ_TYPE_LEVEL_HIGH>, 193 <AIC_IRQ 45 IRQ_TYPE_LEVEL_HIGH>, 194 <AIC_IRQ 46 IRQ_TYPE_LEVEL_HIGH>, 195 <AIC_IRQ 47 IRQ_TYPE_LEVEL_HIGH>, 196 <AIC_IRQ 48 IRQ_TYPE_LEVEL_HIGH>; 197 }; 198 199 pinctrl_aop: pinctrl@2100f0000 { 200 compatible = "apple,t8010-pinctrl", "apple,pinctrl"; 201 reg = <0x2 0x100f0000 0x0 0x100000>; 202 power-domains = <&ps_aop_gpio>; 203 204 gpio-controller; 205 #gpio-cells = <2>; 206 gpio-ranges = <&pinctrl_aop 0 0 42>; 207 apple,npins = <42>; 208 209 interrupt-controller; 210 #interrupt-cells = <2>; 211 interrupt-parent = <&aic>; 212 interrupts = <AIC_IRQ 128 IRQ_TYPE_LEVEL_HIGH>, 213 <AIC_IRQ 129 IRQ_TYPE_LEVEL_HIGH>, 214 <AIC_IRQ 130 IRQ_TYPE_LEVEL_HIGH>, 215 <AIC_IRQ 131 IRQ_TYPE_LEVEL_HIGH>, 216 <AIC_IRQ 132 IRQ_TYPE_LEVEL_HIGH>, 217 <AIC_IRQ 133 IRQ_TYPE_LEVEL_HIGH>, 218 <AIC_IRQ 134 IRQ_TYPE_LEVEL_HIGH>; 219 }; 220 221 pmgr_mini: power-management@210200000 { 222 compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 223 #address-cells = <1>; 224 #size-cells = <1>; 225 226 reg = <0x2 0x10200000 0 0x84000>; 227 }; 228 229 wdt: watchdog@2102b0000 { 230 compatible = "apple,t8010-wdt", "apple,wdt"; 231 reg = <0x2 0x102b0000 0x0 0x4000>; 232 clocks = <&clkref>; 233 interrupt-parent = <&aic>; 234 interrupts = <AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH>; 235 }; 236 }; 237 238 timer { 239 compatible = "arm,armv8-timer"; 240 interrupt-parent = <&aic>; 241 interrupt-names = "phys", "virt"; 242 /* Note that A10 doesn't actually have a hypervisor (EL2 is not implemented). */ 243 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 244 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; 245 }; 246}; 247 248#include "t8010-pmgr.dtsi" 249