1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple T8103 "M1" SoC 4 * 5 * Other names: H13G, "Tonga" 6 * 7 * Copyright The Asahi Linux Contributors 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/apple-aic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/pinctrl/apple.h> 14 15/ { 16 compatible = "apple,t8103", "apple,arm-platform"; 17 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <2>; 23 #size-cells = <0>; 24 25 cpu-map { 26 cluster0 { 27 core0 { 28 cpu = <&cpu_e0>; 29 }; 30 core1 { 31 cpu = <&cpu_e1>; 32 }; 33 core2 { 34 cpu = <&cpu_e2>; 35 }; 36 core3 { 37 cpu = <&cpu_e3>; 38 }; 39 }; 40 41 cluster1 { 42 core0 { 43 cpu = <&cpu_p0>; 44 }; 45 core1 { 46 cpu = <&cpu_p1>; 47 }; 48 core2 { 49 cpu = <&cpu_p2>; 50 }; 51 core3 { 52 cpu = <&cpu_p3>; 53 }; 54 }; 55 }; 56 57 cpu_e0: cpu@0 { 58 compatible = "apple,icestorm"; 59 device_type = "cpu"; 60 reg = <0x0 0x0>; 61 enable-method = "spin-table"; 62 cpu-release-addr = <0 0>; /* To be filled by loader */ 63 operating-points-v2 = <&ecluster_opp>; 64 capacity-dmips-mhz = <714>; 65 performance-domains = <&cpufreq_e>; 66 next-level-cache = <&l2_cache_0>; 67 i-cache-size = <0x20000>; 68 d-cache-size = <0x10000>; 69 }; 70 71 cpu_e1: cpu@1 { 72 compatible = "apple,icestorm"; 73 device_type = "cpu"; 74 reg = <0x0 0x1>; 75 enable-method = "spin-table"; 76 cpu-release-addr = <0 0>; /* To be filled by loader */ 77 operating-points-v2 = <&ecluster_opp>; 78 capacity-dmips-mhz = <714>; 79 performance-domains = <&cpufreq_e>; 80 next-level-cache = <&l2_cache_0>; 81 i-cache-size = <0x20000>; 82 d-cache-size = <0x10000>; 83 }; 84 85 cpu_e2: cpu@2 { 86 compatible = "apple,icestorm"; 87 device_type = "cpu"; 88 reg = <0x0 0x2>; 89 enable-method = "spin-table"; 90 cpu-release-addr = <0 0>; /* To be filled by loader */ 91 operating-points-v2 = <&ecluster_opp>; 92 capacity-dmips-mhz = <714>; 93 performance-domains = <&cpufreq_e>; 94 next-level-cache = <&l2_cache_0>; 95 i-cache-size = <0x20000>; 96 d-cache-size = <0x10000>; 97 }; 98 99 cpu_e3: cpu@3 { 100 compatible = "apple,icestorm"; 101 device_type = "cpu"; 102 reg = <0x0 0x3>; 103 enable-method = "spin-table"; 104 cpu-release-addr = <0 0>; /* To be filled by loader */ 105 operating-points-v2 = <&ecluster_opp>; 106 capacity-dmips-mhz = <714>; 107 performance-domains = <&cpufreq_e>; 108 next-level-cache = <&l2_cache_0>; 109 i-cache-size = <0x20000>; 110 d-cache-size = <0x10000>; 111 }; 112 113 cpu_p0: cpu@10100 { 114 compatible = "apple,firestorm"; 115 device_type = "cpu"; 116 reg = <0x0 0x10100>; 117 enable-method = "spin-table"; 118 cpu-release-addr = <0 0>; /* To be filled by loader */ 119 operating-points-v2 = <&pcluster_opp>; 120 capacity-dmips-mhz = <1024>; 121 performance-domains = <&cpufreq_p>; 122 next-level-cache = <&l2_cache_1>; 123 i-cache-size = <0x30000>; 124 d-cache-size = <0x20000>; 125 }; 126 127 cpu_p1: cpu@10101 { 128 compatible = "apple,firestorm"; 129 device_type = "cpu"; 130 reg = <0x0 0x10101>; 131 enable-method = "spin-table"; 132 cpu-release-addr = <0 0>; /* To be filled by loader */ 133 operating-points-v2 = <&pcluster_opp>; 134 capacity-dmips-mhz = <1024>; 135 performance-domains = <&cpufreq_p>; 136 next-level-cache = <&l2_cache_1>; 137 i-cache-size = <0x30000>; 138 d-cache-size = <0x20000>; 139 }; 140 141 cpu_p2: cpu@10102 { 142 compatible = "apple,firestorm"; 143 device_type = "cpu"; 144 reg = <0x0 0x10102>; 145 enable-method = "spin-table"; 146 cpu-release-addr = <0 0>; /* To be filled by loader */ 147 operating-points-v2 = <&pcluster_opp>; 148 capacity-dmips-mhz = <1024>; 149 performance-domains = <&cpufreq_p>; 150 next-level-cache = <&l2_cache_1>; 151 i-cache-size = <0x30000>; 152 d-cache-size = <0x20000>; 153 }; 154 155 cpu_p3: cpu@10103 { 156 compatible = "apple,firestorm"; 157 device_type = "cpu"; 158 reg = <0x0 0x10103>; 159 enable-method = "spin-table"; 160 cpu-release-addr = <0 0>; /* To be filled by loader */ 161 operating-points-v2 = <&pcluster_opp>; 162 capacity-dmips-mhz = <1024>; 163 performance-domains = <&cpufreq_p>; 164 next-level-cache = <&l2_cache_1>; 165 i-cache-size = <0x30000>; 166 d-cache-size = <0x20000>; 167 }; 168 169 l2_cache_0: l2-cache-0 { 170 compatible = "cache"; 171 cache-level = <2>; 172 cache-unified; 173 cache-size = <0x400000>; 174 }; 175 176 l2_cache_1: l2-cache-1 { 177 compatible = "cache"; 178 cache-level = <2>; 179 cache-unified; 180 cache-size = <0xc00000>; 181 }; 182 }; 183 184 ecluster_opp: opp-table-0 { 185 compatible = "operating-points-v2"; 186 187 opp01 { 188 opp-hz = /bits/ 64 <600000000>; 189 opp-level = <1>; 190 clock-latency-ns = <7500>; 191 }; 192 opp02 { 193 opp-hz = /bits/ 64 <972000000>; 194 opp-level = <2>; 195 clock-latency-ns = <22000>; 196 }; 197 opp03 { 198 opp-hz = /bits/ 64 <1332000000>; 199 opp-level = <3>; 200 clock-latency-ns = <27000>; 201 }; 202 opp04 { 203 opp-hz = /bits/ 64 <1704000000>; 204 opp-level = <4>; 205 clock-latency-ns = <33000>; 206 }; 207 opp05 { 208 opp-hz = /bits/ 64 <2064000000>; 209 opp-level = <5>; 210 clock-latency-ns = <50000>; 211 }; 212 }; 213 214 pcluster_opp: opp-table-1 { 215 compatible = "operating-points-v2"; 216 217 opp01 { 218 opp-hz = /bits/ 64 <600000000>; 219 opp-level = <1>; 220 clock-latency-ns = <8000>; 221 }; 222 opp02 { 223 opp-hz = /bits/ 64 <828000000>; 224 opp-level = <2>; 225 clock-latency-ns = <19000>; 226 }; 227 opp03 { 228 opp-hz = /bits/ 64 <1056000000>; 229 opp-level = <3>; 230 clock-latency-ns = <21000>; 231 }; 232 opp04 { 233 opp-hz = /bits/ 64 <1284000000>; 234 opp-level = <4>; 235 clock-latency-ns = <23000>; 236 }; 237 opp05 { 238 opp-hz = /bits/ 64 <1500000000>; 239 opp-level = <5>; 240 clock-latency-ns = <24000>; 241 }; 242 opp06 { 243 opp-hz = /bits/ 64 <1728000000>; 244 opp-level = <6>; 245 clock-latency-ns = <29000>; 246 }; 247 opp07 { 248 opp-hz = /bits/ 64 <1956000000>; 249 opp-level = <7>; 250 clock-latency-ns = <31000>; 251 }; 252 opp08 { 253 opp-hz = /bits/ 64 <2184000000>; 254 opp-level = <8>; 255 clock-latency-ns = <34000>; 256 }; 257 opp09 { 258 opp-hz = /bits/ 64 <2388000000>; 259 opp-level = <9>; 260 clock-latency-ns = <36000>; 261 }; 262 opp10 { 263 opp-hz = /bits/ 64 <2592000000>; 264 opp-level = <10>; 265 clock-latency-ns = <51000>; 266 }; 267 opp11 { 268 opp-hz = /bits/ 64 <2772000000>; 269 opp-level = <11>; 270 clock-latency-ns = <54000>; 271 }; 272 opp12 { 273 opp-hz = /bits/ 64 <2988000000>; 274 opp-level = <12>; 275 clock-latency-ns = <55000>; 276 }; 277#if 0 278 /* Not available until CPU deep sleep is implemented */ 279 opp13 { 280 opp-hz = /bits/ 64 <3096000000>; 281 opp-level = <13>; 282 clock-latency-ns = <55000>; 283 turbo-mode; 284 }; 285 opp14 { 286 opp-hz = /bits/ 64 <3144000000>; 287 opp-level = <14>; 288 clock-latency-ns = <56000>; 289 turbo-mode; 290 }; 291 opp15 { 292 opp-hz = /bits/ 64 <3204000000>; 293 opp-level = <15>; 294 clock-latency-ns = <56000>; 295 turbo-mode; 296 }; 297#endif 298 }; 299 300 timer { 301 compatible = "arm,armv8-timer"; 302 interrupt-parent = <&aic>; 303 interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt"; 304 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 305 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>, 306 <AIC_FIQ AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>, 307 <AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>; 308 }; 309 310 pmu-e { 311 compatible = "apple,icestorm-pmu"; 312 interrupt-parent = <&aic>; 313 interrupts = <AIC_FIQ AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH>; 314 }; 315 316 pmu-p { 317 compatible = "apple,firestorm-pmu"; 318 interrupt-parent = <&aic>; 319 interrupts = <AIC_FIQ AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH>; 320 }; 321 322 clkref: clock-ref { 323 compatible = "fixed-clock"; 324 #clock-cells = <0>; 325 clock-frequency = <24000000>; 326 clock-output-names = "clkref"; 327 }; 328 329 clk_120m: clock-120m { 330 compatible = "fixed-clock"; 331 #clock-cells = <0>; 332 clock-frequency = <120000000>; 333 clock-output-names = "clk_120m"; 334 }; 335 336 clk_200m: clock-200m { 337 compatible = "fixed-clock"; 338 #clock-cells = <0>; 339 clock-frequency = <200000000>; 340 clock-output-names = "clk_200m"; 341 }; 342 343 /* 344 * This is a fabulated representation of the input clock 345 * to NCO since we don't know the true clock tree. 346 */ 347 nco_clkref: clock-ref-nco { 348 compatible = "fixed-clock"; 349 #clock-cells = <0>; 350 clock-output-names = "nco_ref"; 351 }; 352 353 soc { 354 compatible = "simple-bus"; 355 #address-cells = <2>; 356 #size-cells = <2>; 357 358 ranges; 359 nonposted-mmio; 360 361 cpufreq_e: performance-controller@210e20000 { 362 compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; 363 reg = <0x2 0x10e20000 0 0x1000>; 364 #performance-domain-cells = <0>; 365 }; 366 367 cpufreq_p: performance-controller@211e20000 { 368 compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; 369 reg = <0x2 0x11e20000 0 0x1000>; 370 #performance-domain-cells = <0>; 371 }; 372 373 display_dfr: display-pipe@228200000 { 374 compatible = "apple,t8103-display-pipe", "apple,h7-display-pipe"; 375 reg = <0x2 0x28200000 0x0 0xc000>, 376 <0x2 0x28400000 0x0 0x4000>; 377 reg-names = "be", "fe"; 378 power-domains = <&ps_dispdfr_fe>, <&ps_dispdfr_be>; 379 interrupt-parent = <&aic>; 380 interrupts = <AIC_IRQ 502 IRQ_TYPE_LEVEL_HIGH>, 381 <AIC_IRQ 506 IRQ_TYPE_LEVEL_HIGH>; 382 interrupt-names = "be", "fe"; 383 iommus = <&displaydfr_dart 0>; 384 status = "disabled"; 385 386 port { 387 dfr_adp_out_mipi: endpoint { 388 remote-endpoint = <&dfr_mipi_in_adp>; 389 }; 390 }; 391 }; 392 393 displaydfr_dart: iommu@228304000 { 394 compatible = "apple,t8103-dart"; 395 reg = <0x2 0x28304000 0x0 0x4000>; 396 interrupt-parent = <&aic>; 397 interrupts = <AIC_IRQ 504 IRQ_TYPE_LEVEL_HIGH>; 398 #iommu-cells = <1>; 399 power-domains = <&ps_dispdfr_fe>; 400 status = "disabled"; 401 }; 402 403 displaydfr_mipi: dsi@228600000 { 404 compatible = "apple,t8103-display-pipe-mipi", "apple,h7-display-pipe-mipi"; 405 reg = <0x2 0x28600000 0x0 0x100000>; 406 power-domains = <&ps_mipi_dsi>; 407 #address-cells = <1>; 408 #size-cells = <0>; 409 status = "disabled"; 410 411 ports { 412 #address-cells = <1>; 413 #size-cells = <0>; 414 415 dfr_mipi_in: port@0 { 416 reg = <0>; 417 #address-cells = <1>; 418 #size-cells = <0>; 419 420 dfr_mipi_in_adp: endpoint@0 { 421 reg = <0>; 422 remote-endpoint = <&dfr_adp_out_mipi>; 423 }; 424 }; 425 426 dfr_mipi_out: port@1 { 427 reg = <1>; 428 #address-cells = <1>; 429 #size-cells = <0>; 430 }; 431 }; 432 }; 433 434 sio_dart: iommu@235004000 { 435 compatible = "apple,t8103-dart"; 436 reg = <0x2 0x35004000 0x0 0x4000>; 437 interrupt-parent = <&aic>; 438 interrupts = <AIC_IRQ 635 IRQ_TYPE_LEVEL_HIGH>; 439 #iommu-cells = <1>; 440 power-domains = <&ps_sio_cpu>; 441 }; 442 443 i2c0: i2c@235010000 { 444 compatible = "apple,t8103-i2c", "apple,i2c"; 445 reg = <0x2 0x35010000 0x0 0x4000>; 446 clocks = <&clkref>; 447 interrupt-parent = <&aic>; 448 interrupts = <AIC_IRQ 627 IRQ_TYPE_LEVEL_HIGH>; 449 pinctrl-0 = <&i2c0_pins>; 450 pinctrl-names = "default"; 451 #address-cells = <0x1>; 452 #size-cells = <0x0>; 453 power-domains = <&ps_i2c0>; 454 }; 455 456 i2c1: i2c@235014000 { 457 compatible = "apple,t8103-i2c", "apple,i2c"; 458 reg = <0x2 0x35014000 0x0 0x4000>; 459 clocks = <&clkref>; 460 interrupt-parent = <&aic>; 461 interrupts = <AIC_IRQ 628 IRQ_TYPE_LEVEL_HIGH>; 462 pinctrl-0 = <&i2c1_pins>; 463 pinctrl-names = "default"; 464 #address-cells = <0x1>; 465 #size-cells = <0x0>; 466 power-domains = <&ps_i2c1>; 467 }; 468 469 i2c2: i2c@235018000 { 470 compatible = "apple,t8103-i2c", "apple,i2c"; 471 reg = <0x2 0x35018000 0x0 0x4000>; 472 clocks = <&clkref>; 473 interrupt-parent = <&aic>; 474 interrupts = <AIC_IRQ 629 IRQ_TYPE_LEVEL_HIGH>; 475 pinctrl-0 = <&i2c2_pins>; 476 pinctrl-names = "default"; 477 #address-cells = <0x1>; 478 #size-cells = <0x0>; 479 status = "disabled"; /* not used in all devices */ 480 power-domains = <&ps_i2c2>; 481 }; 482 483 i2c3: i2c@23501c000 { 484 compatible = "apple,t8103-i2c", "apple,i2c"; 485 reg = <0x2 0x3501c000 0x0 0x4000>; 486 clocks = <&clkref>; 487 interrupt-parent = <&aic>; 488 interrupts = <AIC_IRQ 630 IRQ_TYPE_LEVEL_HIGH>; 489 pinctrl-0 = <&i2c3_pins>; 490 pinctrl-names = "default"; 491 #address-cells = <0x1>; 492 #size-cells = <0x0>; 493 power-domains = <&ps_i2c3>; 494 }; 495 496 i2c4: i2c@235020000 { 497 compatible = "apple,t8103-i2c", "apple,i2c"; 498 reg = <0x2 0x35020000 0x0 0x4000>; 499 clocks = <&clkref>; 500 interrupt-parent = <&aic>; 501 interrupts = <AIC_IRQ 631 IRQ_TYPE_LEVEL_HIGH>; 502 pinctrl-0 = <&i2c4_pins>; 503 pinctrl-names = "default"; 504 #address-cells = <0x1>; 505 #size-cells = <0x0>; 506 power-domains = <&ps_i2c4>; 507 status = "disabled"; /* only used in J293 */ 508 }; 509 510 fpwm1: pwm@235044000 { 511 compatible = "apple,t8103-fpwm", "apple,s5l-fpwm"; 512 reg = <0x2 0x35044000 0x0 0x4000>; 513 power-domains = <&ps_fpwm1>; 514 clocks = <&clkref>; 515 #pwm-cells = <2>; 516 status = "disabled"; 517 }; 518 519 spi0: spi@235100000 { 520 compatible = "apple,t8103-spi", "apple,spi"; 521 reg = <0x2 0x35100000 0x0 0x4000>; 522 interrupt-parent = <&aic>; 523 interrupts = <AIC_IRQ 614 IRQ_TYPE_LEVEL_HIGH>; 524 clocks = <&clk_200m>; 525 pinctrl-0 = <&spi0_pins>; 526 pinctrl-names = "default"; 527 power-domains = <&ps_spi0>; 528 #address-cells = <1>; 529 #size-cells = <0>; 530 status = "disabled"; 531 }; 532 533 spi1: spi@235104000 { 534 compatible = "apple,t8103-spi", "apple,spi"; 535 reg = <0x2 0x35104000 0x0 0x4000>; 536 interrupt-parent = <&aic>; 537 interrupts = <AIC_IRQ 615 IRQ_TYPE_LEVEL_HIGH>; 538 clocks = <&clk_200m>; 539 pinctrl-0 = <&spi1_pins>; 540 pinctrl-names = "default"; 541 power-domains = <&ps_spi1>; 542 #address-cells = <1>; 543 #size-cells = <0>; 544 status = "disabled"; 545 }; 546 547 spi3: spi@23510c000 { 548 compatible = "apple,t8103-spi", "apple,spi"; 549 reg = <0x2 0x3510c000 0x0 0x4000>; 550 interrupt-parent = <&aic>; 551 interrupts = <AIC_IRQ 617 IRQ_TYPE_LEVEL_HIGH>; 552 clocks = <&clk_120m>; 553 pinctrl-0 = <&spi3_pins>; 554 pinctrl-names = "default"; 555 power-domains = <&ps_spi3>; 556 #address-cells = <1>; 557 #size-cells = <0>; 558 status = "disabled"; 559 }; 560 561 serial0: serial@235200000 { 562 compatible = "apple,s5l-uart"; 563 reg = <0x2 0x35200000 0x0 0x1000>; 564 reg-io-width = <4>; 565 interrupt-parent = <&aic>; 566 interrupts = <AIC_IRQ 605 IRQ_TYPE_LEVEL_HIGH>; 567 /* 568 * TODO: figure out the clocking properly, there may 569 * be a third selectable clock. 570 */ 571 clocks = <&clkref>, <&clkref>; 572 clock-names = "uart", "clk_uart_baud0"; 573 power-domains = <&ps_uart0>; 574 status = "disabled"; 575 }; 576 577 serial2: serial@235208000 { 578 compatible = "apple,s5l-uart"; 579 reg = <0x2 0x35208000 0x0 0x1000>; 580 reg-io-width = <4>; 581 interrupt-parent = <&aic>; 582 interrupts = <AIC_IRQ 607 IRQ_TYPE_LEVEL_HIGH>; 583 clocks = <&clkref>, <&clkref>; 584 clock-names = "uart", "clk_uart_baud0"; 585 power-domains = <&ps_uart2>; 586 status = "disabled"; 587 }; 588 589 admac: dma-controller@238200000 { 590 compatible = "apple,t8103-admac", "apple,admac"; 591 reg = <0x2 0x38200000 0x0 0x34000>; 592 dma-channels = <24>; 593 interrupts-extended = <0>, 594 <&aic AIC_IRQ 626 IRQ_TYPE_LEVEL_HIGH>, 595 <0>, 596 <0>; 597 #dma-cells = <1>; 598 iommus = <&sio_dart 2>; 599 power-domains = <&ps_sio_adma>; 600 resets = <&ps_audio_p>; 601 }; 602 603 mca: i2s@238400000 { 604 compatible = "apple,t8103-mca", "apple,mca"; 605 reg = <0x2 0x38400000 0x0 0x18000>, 606 <0x2 0x38300000 0x0 0x30000>; 607 608 interrupt-parent = <&aic>; 609 interrupts = <AIC_IRQ 619 IRQ_TYPE_LEVEL_HIGH>, 610 <AIC_IRQ 620 IRQ_TYPE_LEVEL_HIGH>, 611 <AIC_IRQ 621 IRQ_TYPE_LEVEL_HIGH>, 612 <AIC_IRQ 622 IRQ_TYPE_LEVEL_HIGH>, 613 <AIC_IRQ 623 IRQ_TYPE_LEVEL_HIGH>, 614 <AIC_IRQ 624 IRQ_TYPE_LEVEL_HIGH>; 615 616 resets = <&ps_audio_p>; 617 clocks = <&nco 0>, <&nco 1>, <&nco 2>, 618 <&nco 3>, <&nco 4>, <&nco 4>; 619 power-domains = <&ps_audio_p>, <&ps_mca0>, <&ps_mca1>, 620 <&ps_mca2>, <&ps_mca3>, <&ps_mca4>, <&ps_mca5>; 621 dmas = <&admac 0>, <&admac 1>, <&admac 2>, <&admac 3>, 622 <&admac 4>, <&admac 5>, <&admac 6>, <&admac 7>, 623 <&admac 8>, <&admac 9>, <&admac 10>, <&admac 11>, 624 <&admac 12>, <&admac 13>, <&admac 14>, <&admac 15>, 625 <&admac 16>, <&admac 17>, <&admac 18>, <&admac 19>, 626 <&admac 20>, <&admac 21>, <&admac 22>, <&admac 23>; 627 dma-names = "tx0a", "rx0a", "tx0b", "rx0b", 628 "tx1a", "rx1a", "tx1b", "rx1b", 629 "tx2a", "rx2a", "tx2b", "rx2b", 630 "tx3a", "rx3a", "tx3b", "rx3b", 631 "tx4a", "rx4a", "tx4b", "rx4b", 632 "tx5a", "rx5a", "tx5b", "rx5b"; 633 634 #sound-dai-cells = <1>; 635 }; 636 637 nco: clock-controller@23b044000 { 638 compatible = "apple,t8103-nco", "apple,nco"; 639 reg = <0x2 0x3b044000 0x0 0x14000>; 640 clocks = <&nco_clkref>; 641 #clock-cells = <1>; 642 }; 643 644 aic: interrupt-controller@23b100000 { 645 compatible = "apple,t8103-aic", "apple,aic"; 646 #interrupt-cells = <3>; 647 interrupt-controller; 648 reg = <0x2 0x3b100000 0x0 0x8000>; 649 power-domains = <&ps_aic>; 650 651 affinities { 652 e-core-pmu-affinity { 653 apple,fiq-index = <AIC_CPU_PMU_E>; 654 cpus = <&cpu_e0 &cpu_e1 &cpu_e2 &cpu_e3>; 655 }; 656 657 p-core-pmu-affinity { 658 apple,fiq-index = <AIC_CPU_PMU_P>; 659 cpus = <&cpu_p0 &cpu_p1 &cpu_p2 &cpu_p3>; 660 }; 661 }; 662 }; 663 664 pmgr: power-management@23b700000 { 665 compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 666 #address-cells = <1>; 667 #size-cells = <1>; 668 reg = <0x2 0x3b700000 0 0x14000>; 669 }; 670 671 pinctrl_ap: pinctrl@23c100000 { 672 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 673 reg = <0x2 0x3c100000 0x0 0x100000>; 674 power-domains = <&ps_gpio>; 675 676 gpio-controller; 677 #gpio-cells = <2>; 678 gpio-ranges = <&pinctrl_ap 0 0 212>; 679 apple,npins = <212>; 680 681 interrupt-controller; 682 #interrupt-cells = <2>; 683 interrupt-parent = <&aic>; 684 interrupts = <AIC_IRQ 190 IRQ_TYPE_LEVEL_HIGH>, 685 <AIC_IRQ 191 IRQ_TYPE_LEVEL_HIGH>, 686 <AIC_IRQ 192 IRQ_TYPE_LEVEL_HIGH>, 687 <AIC_IRQ 193 IRQ_TYPE_LEVEL_HIGH>, 688 <AIC_IRQ 194 IRQ_TYPE_LEVEL_HIGH>, 689 <AIC_IRQ 195 IRQ_TYPE_LEVEL_HIGH>, 690 <AIC_IRQ 196 IRQ_TYPE_LEVEL_HIGH>; 691 692 i2c0_pins: i2c0-pins { 693 pinmux = <APPLE_PINMUX(192, 1)>, 694 <APPLE_PINMUX(188, 1)>; 695 }; 696 697 i2c1_pins: i2c1-pins { 698 pinmux = <APPLE_PINMUX(201, 1)>, 699 <APPLE_PINMUX(199, 1)>; 700 }; 701 702 i2c2_pins: i2c2-pins { 703 pinmux = <APPLE_PINMUX(163, 1)>, 704 <APPLE_PINMUX(162, 1)>; 705 }; 706 707 i2c3_pins: i2c3-pins { 708 pinmux = <APPLE_PINMUX(73, 1)>, 709 <APPLE_PINMUX(72, 1)>; 710 }; 711 712 i2c4_pins: i2c4-pins { 713 pinmux = <APPLE_PINMUX(135, 1)>, 714 <APPLE_PINMUX(134, 1)>; 715 }; 716 717 spi0_pins: spi0-pins { 718 pinmux = <APPLE_PINMUX(67, 1)>, /* CLK */ 719 <APPLE_PINMUX(68, 1)>, /* MOSI */ 720 <APPLE_PINMUX(69, 1)>; /* MISO */ 721 }; 722 723 spi1_pins: spi1-pins { 724 pinmux = <APPLE_PINMUX(42, 1)>, 725 <APPLE_PINMUX(43, 1)>, 726 <APPLE_PINMUX(44, 1)>, 727 <APPLE_PINMUX(45, 1)>; 728 }; 729 730 spi3_pins: spi3-pins { 731 pinmux = <APPLE_PINMUX(46, 1)>, 732 <APPLE_PINMUX(47, 1)>, 733 <APPLE_PINMUX(48, 1)>, 734 <APPLE_PINMUX(49, 1)>; 735 }; 736 737 pcie_pins: pcie-pins { 738 pinmux = <APPLE_PINMUX(150, 1)>, 739 <APPLE_PINMUX(151, 1)>, 740 <APPLE_PINMUX(32, 1)>; 741 }; 742 }; 743 744 pinctrl_nub: pinctrl@23d1f0000 { 745 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 746 reg = <0x2 0x3d1f0000 0x0 0x4000>; 747 power-domains = <&ps_nub_gpio>; 748 749 gpio-controller; 750 #gpio-cells = <2>; 751 gpio-ranges = <&pinctrl_nub 0 0 23>; 752 apple,npins = <23>; 753 754 interrupt-controller; 755 #interrupt-cells = <2>; 756 interrupt-parent = <&aic>; 757 interrupts = <AIC_IRQ 330 IRQ_TYPE_LEVEL_HIGH>, 758 <AIC_IRQ 331 IRQ_TYPE_LEVEL_HIGH>, 759 <AIC_IRQ 332 IRQ_TYPE_LEVEL_HIGH>, 760 <AIC_IRQ 333 IRQ_TYPE_LEVEL_HIGH>, 761 <AIC_IRQ 334 IRQ_TYPE_LEVEL_HIGH>, 762 <AIC_IRQ 335 IRQ_TYPE_LEVEL_HIGH>, 763 <AIC_IRQ 336 IRQ_TYPE_LEVEL_HIGH>; 764 }; 765 766 pmgr_mini: power-management@23d280000 { 767 compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 768 #address-cells = <1>; 769 #size-cells = <1>; 770 reg = <0x2 0x3d280000 0 0x4000>; 771 }; 772 773 wdt: watchdog@23d2b0000 { 774 compatible = "apple,t8103-wdt", "apple,wdt"; 775 reg = <0x2 0x3d2b0000 0x0 0x4000>; 776 clocks = <&clkref>; 777 interrupt-parent = <&aic>; 778 interrupts = <AIC_IRQ 338 IRQ_TYPE_LEVEL_HIGH>; 779 }; 780 781 pinctrl_smc: pinctrl@23e820000 { 782 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 783 reg = <0x2 0x3e820000 0x0 0x4000>; 784 785 gpio-controller; 786 #gpio-cells = <2>; 787 gpio-ranges = <&pinctrl_smc 0 0 16>; 788 apple,npins = <16>; 789 790 interrupt-controller; 791 #interrupt-cells = <2>; 792 interrupt-parent = <&aic>; 793 interrupts = <AIC_IRQ 391 IRQ_TYPE_LEVEL_HIGH>, 794 <AIC_IRQ 392 IRQ_TYPE_LEVEL_HIGH>, 795 <AIC_IRQ 393 IRQ_TYPE_LEVEL_HIGH>, 796 <AIC_IRQ 394 IRQ_TYPE_LEVEL_HIGH>, 797 <AIC_IRQ 395 IRQ_TYPE_LEVEL_HIGH>, 798 <AIC_IRQ 396 IRQ_TYPE_LEVEL_HIGH>, 799 <AIC_IRQ 397 IRQ_TYPE_LEVEL_HIGH>; 800 }; 801 802 pinctrl_aop: pinctrl@24a820000 { 803 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 804 reg = <0x2 0x4a820000 0x0 0x4000>; 805 806 gpio-controller; 807 #gpio-cells = <2>; 808 gpio-ranges = <&pinctrl_aop 0 0 42>; 809 apple,npins = <42>; 810 811 interrupt-controller; 812 #interrupt-cells = <2>; 813 interrupt-parent = <&aic>; 814 interrupts = <AIC_IRQ 268 IRQ_TYPE_LEVEL_HIGH>, 815 <AIC_IRQ 269 IRQ_TYPE_LEVEL_HIGH>, 816 <AIC_IRQ 270 IRQ_TYPE_LEVEL_HIGH>, 817 <AIC_IRQ 271 IRQ_TYPE_LEVEL_HIGH>, 818 <AIC_IRQ 272 IRQ_TYPE_LEVEL_HIGH>, 819 <AIC_IRQ 273 IRQ_TYPE_LEVEL_HIGH>, 820 <AIC_IRQ 274 IRQ_TYPE_LEVEL_HIGH>; 821 }; 822 823 ans_mbox: mbox@277408000 { 824 compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4"; 825 reg = <0x2 0x77408000 0x0 0x4000>; 826 interrupt-parent = <&aic>; 827 interrupts = <AIC_IRQ 583 IRQ_TYPE_LEVEL_HIGH>, 828 <AIC_IRQ 584 IRQ_TYPE_LEVEL_HIGH>, 829 <AIC_IRQ 585 IRQ_TYPE_LEVEL_HIGH>, 830 <AIC_IRQ 586 IRQ_TYPE_LEVEL_HIGH>; 831 interrupt-names = "send-empty", "send-not-empty", 832 "recv-empty", "recv-not-empty"; 833 #mbox-cells = <0>; 834 power-domains = <&ps_ans2>; 835 }; 836 837 sart: iommu@27bc50000 { 838 compatible = "apple,t8103-sart"; 839 reg = <0x2 0x7bc50000 0x0 0x10000>; 840 power-domains = <&ps_ans2>; 841 }; 842 843 nvme@27bcc0000 { 844 compatible = "apple,t8103-nvme-ans2", "apple,nvme-ans2"; 845 reg = <0x2 0x7bcc0000 0x0 0x40000>, 846 <0x2 0x77400000 0x0 0x4000>; 847 reg-names = "nvme", "ans"; 848 interrupt-parent = <&aic>; 849 interrupts = <AIC_IRQ 590 IRQ_TYPE_LEVEL_HIGH>; 850 mboxes = <&ans_mbox>; 851 apple,sart = <&sart>; 852 power-domains = <&ps_ans2>, <&ps_apcie_st>; 853 power-domain-names = "ans", "apcie0"; 854 resets = <&ps_ans2>; 855 }; 856 857 pcie0_dart_0: iommu@681008000 { 858 compatible = "apple,t8103-dart"; 859 reg = <0x6 0x81008000 0x0 0x4000>; 860 #iommu-cells = <1>; 861 interrupt-parent = <&aic>; 862 interrupts = <AIC_IRQ 696 IRQ_TYPE_LEVEL_HIGH>; 863 power-domains = <&ps_apcie_gp>; 864 }; 865 866 pcie0_dart_1: iommu@682008000 { 867 compatible = "apple,t8103-dart"; 868 reg = <0x6 0x82008000 0x0 0x4000>; 869 #iommu-cells = <1>; 870 interrupt-parent = <&aic>; 871 interrupts = <AIC_IRQ 699 IRQ_TYPE_LEVEL_HIGH>; 872 power-domains = <&ps_apcie_gp>; 873 status = "disabled"; 874 }; 875 876 pcie0_dart_2: iommu@683008000 { 877 compatible = "apple,t8103-dart"; 878 reg = <0x6 0x83008000 0x0 0x4000>; 879 #iommu-cells = <1>; 880 interrupt-parent = <&aic>; 881 interrupts = <AIC_IRQ 702 IRQ_TYPE_LEVEL_HIGH>; 882 power-domains = <&ps_apcie_gp>; 883 status = "disabled"; 884 }; 885 886 pcie0: pcie@690000000 { 887 compatible = "apple,t8103-pcie", "apple,pcie"; 888 device_type = "pci"; 889 890 reg = <0x6 0x90000000 0x0 0x1000000>, 891 <0x6 0x80000000 0x0 0x100000>, 892 <0x6 0x81000000 0x0 0x4000>, 893 <0x6 0x82000000 0x0 0x4000>, 894 <0x6 0x83000000 0x0 0x4000>; 895 reg-names = "config", "rc", "port0", "port1", "port2"; 896 897 interrupt-parent = <&aic>; 898 interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>, 899 <AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>, 900 <AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>; 901 902 msi-controller; 903 msi-parent = <&pcie0>; 904 msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>; 905 906 907 iommu-map = <0x100 &pcie0_dart_0 1 1>, 908 <0x200 &pcie0_dart_1 1 1>, 909 <0x300 &pcie0_dart_2 1 1>; 910 iommu-map-mask = <0xff00>; 911 912 bus-range = <0 3>; 913 #address-cells = <3>; 914 #size-cells = <2>; 915 ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>, 916 <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>; 917 918 power-domains = <&ps_apcie_gp>; 919 pinctrl-0 = <&pcie_pins>; 920 pinctrl-names = "default"; 921 922 port00: pci@0,0 { 923 device_type = "pci"; 924 reg = <0x0 0x0 0x0 0x0 0x0>; 925 reset-gpios = <&pinctrl_ap 152 GPIO_ACTIVE_LOW>; 926 927 #address-cells = <3>; 928 #size-cells = <2>; 929 ranges; 930 931 interrupt-controller; 932 #interrupt-cells = <1>; 933 934 interrupt-map-mask = <0 0 0 7>; 935 interrupt-map = <0 0 0 1 &port00 0 0 0 0>, 936 <0 0 0 2 &port00 0 0 0 1>, 937 <0 0 0 3 &port00 0 0 0 2>, 938 <0 0 0 4 &port00 0 0 0 3>; 939 }; 940 941 port01: pci@1,0 { 942 device_type = "pci"; 943 reg = <0x800 0x0 0x0 0x0 0x0>; 944 reset-gpios = <&pinctrl_ap 153 GPIO_ACTIVE_LOW>; 945 946 #address-cells = <3>; 947 #size-cells = <2>; 948 ranges; 949 950 interrupt-controller; 951 #interrupt-cells = <1>; 952 953 interrupt-map-mask = <0 0 0 7>; 954 interrupt-map = <0 0 0 1 &port01 0 0 0 0>, 955 <0 0 0 2 &port01 0 0 0 1>, 956 <0 0 0 3 &port01 0 0 0 2>, 957 <0 0 0 4 &port01 0 0 0 3>; 958 status = "disabled"; 959 }; 960 961 port02: pci@2,0 { 962 device_type = "pci"; 963 reg = <0x1000 0x0 0x0 0x0 0x0>; 964 reset-gpios = <&pinctrl_ap 33 GPIO_ACTIVE_LOW>; 965 966 #address-cells = <3>; 967 #size-cells = <2>; 968 ranges; 969 970 interrupt-controller; 971 #interrupt-cells = <1>; 972 973 interrupt-map-mask = <0 0 0 7>; 974 interrupt-map = <0 0 0 1 &port02 0 0 0 0>, 975 <0 0 0 2 &port02 0 0 0 1>, 976 <0 0 0 3 &port02 0 0 0 2>, 977 <0 0 0 4 &port02 0 0 0 3>; 978 status = "disabled"; 979 }; 980 }; 981 }; 982}; 983 984#include "t8103-pmgr.dtsi" 985