1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple T8015 "A11" SoC 4 * 5 * Other names: H10, "Skye" 6 * 7 * Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org> 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/apple-aic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/pinctrl/apple.h> 14 15/ { 16 interrupt-parent = <&aic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 clkref: clock-ref { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <24000000>; 24 clock-output-names = "clkref"; 25 }; 26 27 cpus { 28 #address-cells = <2>; 29 #size-cells = <0>; 30 31 cpu-map { 32 cluster0 { 33 core0 { 34 cpu = <&cpu_e0>; 35 }; 36 core1 { 37 cpu = <&cpu_e1>; 38 }; 39 core2 { 40 cpu = <&cpu_e2>; 41 }; 42 core3 { 43 cpu = <&cpu_e3>; 44 }; 45 }; 46 47 cluster1 { 48 core0 { 49 cpu = <&cpu_p0>; 50 }; 51 core1 { 52 cpu = <&cpu_p1>; 53 }; 54 }; 55 }; 56 57 cpu_e0: cpu@0 { 58 compatible = "apple,mistral"; 59 reg = <0x0 0x0>; 60 cpu-release-addr = <0 0>; /* To be filled by loader */ 61 performance-domains = <&cpufreq_e>; 62 operating-points-v2 = <&mistral_opp>; 63 capacity-dmips-mhz = <633>; 64 enable-method = "spin-table"; 65 device_type = "cpu"; 66 }; 67 68 cpu_e1: cpu@1 { 69 compatible = "apple,mistral"; 70 reg = <0x0 0x1>; 71 cpu-release-addr = <0 0>; /* To be filled by loader */ 72 performance-domains = <&cpufreq_e>; 73 operating-points-v2 = <&mistral_opp>; 74 capacity-dmips-mhz = <633>; 75 enable-method = "spin-table"; 76 device_type = "cpu"; 77 }; 78 79 cpu_e2: cpu@2 { 80 compatible = "apple,mistral"; 81 reg = <0x0 0x2>; 82 cpu-release-addr = <0 0>; /* To be filled by loader */ 83 performance-domains = <&cpufreq_e>; 84 operating-points-v2 = <&mistral_opp>; 85 capacity-dmips-mhz = <633>; 86 enable-method = "spin-table"; 87 device_type = "cpu"; 88 }; 89 90 cpu_e3: cpu@3 { 91 compatible = "apple,mistral"; 92 reg = <0x0 0x3>; 93 cpu-release-addr = <0 0>; /* To be filled by loader */ 94 performance-domains = <&cpufreq_e>; 95 operating-points-v2 = <&mistral_opp>; 96 capacity-dmips-mhz = <633>; 97 enable-method = "spin-table"; 98 device_type = "cpu"; 99 }; 100 101 cpu_p0: cpu@10004 { 102 compatible = "apple,monsoon"; 103 reg = <0x0 0x10004>; 104 cpu-release-addr = <0 0>; /* To be filled by loader */ 105 performance-domains = <&cpufreq_p>; 106 operating-points-v2 = <&monsoon_opp>; 107 capacity-dmips-mhz = <1024>; 108 enable-method = "spin-table"; 109 device_type = "cpu"; 110 }; 111 112 cpu_p1: cpu@10005 { 113 compatible = "apple,monsoon"; 114 reg = <0x0 0x10005>; 115 cpu-release-addr = <0 0>; /* To be filled by loader */ 116 performance-domains = <&cpufreq_p>; 117 operating-points-v2 = <&monsoon_opp>; 118 capacity-dmips-mhz = <1024>; 119 enable-method = "spin-table"; 120 device_type = "cpu"; 121 }; 122 }; 123 124 mistral_opp: opp-table-0 { 125 compatible = "operating-points-v2"; 126 127 opp01 { 128 opp-hz = /bits/ 64 <300000000>; 129 opp-level = <1>; 130 clock-latency-ns = <1800>; 131 }; 132 opp02 { 133 opp-hz = /bits/ 64 <453000000>; 134 opp-level = <2>; 135 clock-latency-ns = <140000>; 136 }; 137 opp03 { 138 opp-hz = /bits/ 64 <672000000>; 139 opp-level = <3>; 140 clock-latency-ns = <105000>; 141 }; 142 opp04 { 143 opp-hz = /bits/ 64 <972000000>; 144 opp-level = <4>; 145 clock-latency-ns = <115000>; 146 }; 147 opp05 { 148 opp-hz = /bits/ 64 <1272000000>; 149 opp-level = <5>; 150 clock-latency-ns = <125000>; 151 }; 152 opp06 { 153 opp-hz = /bits/ 64 <1572000000>; 154 opp-level = <6>; 155 clock-latency-ns = <135000>; 156 }; 157#if 0 158 /* Not available until CPU deep sleep is implemented */ 159 opp07 { 160 opp-hz = /bits/ 64 <1680000000>; 161 opp-level = <7>; 162 clock-latency-ns = <135000>; 163 turbo-mode; 164 }; 165#endif 166 }; 167 168 monsoon_opp: opp-table-1 { 169 compatible = "operating-points-v2"; 170 171 opp01 { 172 opp-hz = /bits/ 64 <300000000>; 173 opp-level = <1>; 174 clock-latency-ns = <1400>; 175 }; 176 opp02 { 177 opp-hz = /bits/ 64 <453000000>; 178 opp-level = <2>; 179 clock-latency-ns = <140000>; 180 }; 181 opp03 { 182 opp-hz = /bits/ 64 <853000000>; 183 opp-level = <3>; 184 clock-latency-ns = <110000>; 185 }; 186 opp04 { 187 opp-hz = /bits/ 64 <1332000000>; 188 opp-level = <4>; 189 clock-latency-ns = <110000>; 190 }; 191 opp05 { 192 opp-hz = /bits/ 64 <1812000000>; 193 opp-level = <5>; 194 clock-latency-ns = <125000>; 195 }; 196 opp06 { 197 opp-hz = /bits/ 64 <2064000000>; 198 opp-level = <6>; 199 clock-latency-ns = <130000>; 200 }; 201 opp07 { 202 opp-hz = /bits/ 64 <2304000000>; 203 opp-level = <7>; 204 clock-latency-ns = <140000>; 205 }; 206#if 0 207 /* Not available until CPU deep sleep is implemented */ 208 opp08 { 209 opp-hz = /bits/ 64 <2376000000>; 210 opp-level = <8>; 211 clock-latency-ns = <140000>; 212 turbo-mode; 213 }; 214#endif 215 }; 216 217 soc { 218 compatible = "simple-bus"; 219 #address-cells = <2>; 220 #size-cells = <2>; 221 nonposted-mmio; 222 ranges; 223 224 cpufreq_e: performance-controller@208e20000 { 225 compatible = "apple,t8015-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; 226 reg = <0x2 0x08e20000 0 0x1000>; 227 #performance-domain-cells = <0>; 228 }; 229 230 cpufreq_p: performance-controller@208ea0000 { 231 compatible = "apple,t8015-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; 232 reg = <0x2 0x08ea0000 0 0x1000>; 233 #performance-domain-cells = <0>; 234 }; 235 236 serial0: serial@22e600000 { 237 compatible = "apple,s5l-uart"; 238 reg = <0x2 0x2e600000 0x0 0x4000>; 239 reg-io-width = <4>; 240 interrupt-parent = <&aic>; 241 interrupts = <AIC_IRQ 282 IRQ_TYPE_LEVEL_HIGH>; 242 /* Use the bootloader-enabled clocks for now. */ 243 clocks = <&clkref>, <&clkref>; 244 clock-names = "uart", "clk_uart_baud0"; 245 power-domains = <&ps_uart0>; 246 status = "disabled"; 247 }; 248 249 aic: interrupt-controller@232100000 { 250 compatible = "apple,t8015-aic", "apple,aic"; 251 reg = <0x2 0x32100000 0x0 0x8000>; 252 #interrupt-cells = <3>; 253 interrupt-controller; 254 power-domains = <&ps_aic>; 255 }; 256 257 pmgr: power-management@232000000 { 258 compatible = "apple,t8015-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 259 #address-cells = <1>; 260 #size-cells = <1>; 261 262 reg = <0x2 0x32000000 0 0x8c000>; 263 }; 264 265 dwi_bl: backlight@232200080 { 266 compatible = "apple,t8015-dwi-bl", "apple,dwi-bl"; 267 reg = <0x2 0x32200080 0x0 0x8>; 268 power-domains = <&ps_dwi>; 269 status = "disabled"; 270 }; 271 272 pinctrl_ap: pinctrl@233100000 { 273 compatible = "apple,t8015-pinctrl", "apple,pinctrl"; 274 reg = <0x2 0x33100000 0x0 0x1000>; 275 power-domains = <&ps_gpio>; 276 277 gpio-controller; 278 #gpio-cells = <2>; 279 gpio-ranges = <&pinctrl_ap 0 0 223>; 280 apple,npins = <223>; 281 282 interrupt-controller; 283 #interrupt-cells = <2>; 284 interrupt-parent = <&aic>; 285 interrupts = <AIC_IRQ 50 IRQ_TYPE_LEVEL_HIGH>, 286 <AIC_IRQ 51 IRQ_TYPE_LEVEL_HIGH>, 287 <AIC_IRQ 52 IRQ_TYPE_LEVEL_HIGH>, 288 <AIC_IRQ 53 IRQ_TYPE_LEVEL_HIGH>, 289 <AIC_IRQ 54 IRQ_TYPE_LEVEL_HIGH>, 290 <AIC_IRQ 55 IRQ_TYPE_LEVEL_HIGH>, 291 <AIC_IRQ 56 IRQ_TYPE_LEVEL_HIGH>; 292 }; 293 294 pinctrl_aop: pinctrl@2340f0000 { 295 compatible = "apple,t8015-pinctrl", "apple,pinctrl"; 296 reg = <0x2 0x340f0000 0x0 0x4000>; 297 298 gpio-controller; 299 #gpio-cells = <2>; 300 gpio-ranges = <&pinctrl_aop 0 0 49>; 301 apple,npins = <49>; 302 303 interrupt-controller; 304 #interrupt-cells = <2>; 305 interrupt-parent = <&aic>; 306 interrupts = <AIC_IRQ 135 IRQ_TYPE_LEVEL_HIGH>, 307 <AIC_IRQ 136 IRQ_TYPE_LEVEL_HIGH>, 308 <AIC_IRQ 137 IRQ_TYPE_LEVEL_HIGH>, 309 <AIC_IRQ 138 IRQ_TYPE_LEVEL_HIGH>, 310 <AIC_IRQ 139 IRQ_TYPE_LEVEL_HIGH>, 311 <AIC_IRQ 140 IRQ_TYPE_LEVEL_HIGH>, 312 <AIC_IRQ 141 IRQ_TYPE_LEVEL_HIGH>; 313 }; 314 315 pinctrl_nub: pinctrl@2351f0000 { 316 compatible = "apple,t8015-pinctrl", "apple,pinctrl"; 317 reg = <0x2 0x351f0000 0x0 0x4000>; 318 319 gpio-controller; 320 #gpio-cells = <2>; 321 gpio-ranges = <&pinctrl_nub 0 0 8>; 322 apple,npins = <8>; 323 324 interrupt-controller; 325 #interrupt-cells = <2>; 326 interrupt-parent = <&aic>; 327 interrupts = <AIC_IRQ 168 IRQ_TYPE_LEVEL_HIGH>, 328 <AIC_IRQ 169 IRQ_TYPE_LEVEL_HIGH>, 329 <AIC_IRQ 170 IRQ_TYPE_LEVEL_HIGH>; 330 }; 331 332 pmgr_mini: power-management@235200000 { 333 compatible = "apple,t8015-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 334 #address-cells = <1>; 335 #size-cells = <1>; 336 337 reg = <0x2 0x35200000 0 0x84000>; 338 }; 339 340 wdt: watchdog@2352b0000 { 341 compatible = "apple,t8015-wdt", "apple,wdt"; 342 reg = <0x2 0x352b0000 0x0 0x4000>; 343 clocks = <&clkref>; 344 interrupt-parent = <&aic>; 345 interrupts = <AIC_IRQ 172 IRQ_TYPE_LEVEL_HIGH>; 346 }; 347 348 pinctrl_smc: pinctrl@236024000 { 349 compatible = "apple,t8015-pinctrl", "apple,pinctrl"; 350 reg = <0x2 0x36024000 0x0 0x4000>; 351 352 gpio-controller; 353 #gpio-cells = <2>; 354 gpio-ranges = <&pinctrl_smc 0 0 6>; 355 apple,npins = <6>; 356 357 interrupt-controller; 358 #interrupt-cells = <2>; 359 interrupt-parent = <&aic>; 360 interrupts = <AIC_IRQ 199 IRQ_TYPE_LEVEL_HIGH>, 361 <AIC_IRQ 200 IRQ_TYPE_LEVEL_HIGH>, 362 <AIC_IRQ 201 IRQ_TYPE_LEVEL_HIGH>, 363 <AIC_IRQ 202 IRQ_TYPE_LEVEL_HIGH>, 364 <AIC_IRQ 203 IRQ_TYPE_LEVEL_HIGH>, 365 <AIC_IRQ 204 IRQ_TYPE_LEVEL_HIGH>, 366 <AIC_IRQ 205 IRQ_TYPE_LEVEL_HIGH>; 367 /* 368 * SMC is not yet supported and accessing this pinctrl while SMC is 369 * suspended results in a hang. 370 */ 371 status = "disabled"; 372 }; 373 }; 374 375 timer { 376 compatible = "arm,armv8-timer"; 377 interrupt-parent = <&aic>; 378 interrupt-names = "phys", "virt"; 379 /* Note that A11 doesn't actually have a hypervisor (EL2 is not implemented). */ 380 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 381 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; 382 }; 383}; 384 385#include "t8015-pmgr.dtsi" 386