Searched +full:max +full:- +full:frequency (Results 1 – 25 of 53) sorted by relevance
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1 /* SPDX-License-Identifier: MIT */3 * arch-x86/cpuid.h30 * EAX: Largest Xen-information leaf. All leaves up to an including @EAX32 * EBX-EDX: "XenVMMXenVMM" signature, allowing positive identification43 * EBX-EDX: Reserved (currently all zeroes).50 * EBX: Base address of Xen-specific MSRs.61 * Sub-leaf 0: EAX: bit 0: emulated tsc66 * ECX: guest tsc frequency in kHz68 * Sub-leaf 1: EAX: tsc offset low part70 * ECX: multiplicator for tsc->ns conversion[all …]
2 * Alpha specific proc functions for linux-user4 * SPDX-License-Identifier: GPL-2.0-or-later18 p = object_class_get_name(OBJECT_CLASS(env_cpu(cpu_env)->cc)); in open_cpuinfo()19 q = strchr(p, '-'); in open_cpuinfo()20 t = q - p; in open_cpuinfo()28 cpu_mask = -1; in open_cpuinfo()30 cpu_mask = (1UL << num_cpus) - 1; in open_cpuinfo()44 "cycle frequency [Hz]\t: 250000000\n" in open_cpuinfo()45 "timer frequency [Hz]\t: 250.00\n" in open_cpuinfo()48 "max. addr. space #\t: 255\n" in open_cpuinfo()[all …]
4 * Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>11 /dts-v1/;14 #address-cells = <2>;15 #size-cells = <1>;18 dcr-parent = <&{/cpus/cpu@0}>;28 #address-cells = <1>;29 #size-cells = <0>;35 clock-frequency = <0>; /* Filled in by U-Boot */36 timebase-frequency = <0>; /* Filled in by U-Boot */37 i-cache-line-size = <32>;[all …]
5 * SPDX-License-Identifier: GPL-2.0+8 /dts-v1/;11 #address-cells = <0x01>;12 #size-cells = <0x01>;23 stdout-path = "/plb/serial@84000000";27 #address-cells = <0x01>;28 #size-cells = <0x00>;32 clock-frequency = <0x3b9aca0>;33 compatible = "xlnx,microblaze-7.10.d";34 d-cache-baseaddr = <0x90000000>;[all …]
5 * SPDX-License-Identifier: GPL-2.0+8 /dts-v1/;11 #address-cells = < 0x01 >;12 #size-cells = < 0x01 >;22 ethernet0 = "/axi/axi-ethernet@82780000";28 stdout-path = "/axi/serial@83e00000";32 #address-cells = < 0x01 >;34 #size-cells = < 0x00 >;37 clock-frequency = < 0xbebc200 >;38 compatible = "xlnx,microblaze-8.10.a";[all …]
4 # SPDX-License-Identifier: BSD-3-Clause93 # We special-case None here to avoid a double-failure for CPUs without a _PSS114 …testsuite.test("_PSS must list Pstates in descending order of frequency", frequencies == sorted(fr…122 """Execute and verify frequency for each Pstate in the _PSS"""162 # Detecting Turbo frequency requires at least 2 pstates163 # since turbo frequency = max non-turbo frequency + 1170 while (time.time() - start < 2):175 # Abort the test if no cpu frequency is not available189 …testsuite.test("P{}: Turbo measured frequency {} >= expected {} MHz".format(n, aperf, pstate.core_…191 …testsuite.test("P{}: measured frequency {} MHz == expected {} MHz".format(n, aperf, pstate.core_fr…[all …]
165 255, /* Max possible value. */173 4, /* Max possible value. */185 65535, /* Max possible value. */198 65535, /* Max possible value. */204 ptrdiff_t diff = module - pwm_module_list; in pwm_module_index()214 ptrdiff_t diff = pwm - pwm_list; in pwm_index()229 response = qtest_qmp(qts, "{ 'execute': 'qom-get'," in pwm_qom_get()271 response = qtest_qmp(qts, "{ 'execute': 'qom-set'," in mft_qom_set()357 duty = MAX_DUTY - duty; in pwm_compute_duty()365 return qtest_readl(qts, td->module->base_addr + offset); in pwm_read()[all …]
8 * Based on MMC controller for Samsung S5PC1xx-based board emulation197 FIELD(SDHC_HOSTCTL2, V18_ENA, 3, 1); /* UHS-I only */198 FIELD(SDHC_HOSTCTL2, DRIVER_STRENGTH, 4, 2); /* UHS-I only */199 FIELD(SDHC_HOSTCTL2, EXECUTE_TUNING, 6, 1); /* UHS-I only */200 FIELD(SDHC_HOSTCTL2, SAMPLING_CLKSEL, 7, 1); /* UHS-I only */296 * - 3.3v and 1.8v voltages297 * - SDMA/ADMA1/ADMA2298 * - high-speed299 * max host controller R/W buffers size: 512B300 * max clock frequency for SDclock: 52 MHz[all …]
2 * qdist.c - QEMU helpers for handling frequency distributions of data.7 * See the COPYING file in the top-level directory.21 dist->entries = g_new(struct qdist_entry, 1); in qdist_init()22 dist->size = 1; in qdist_init()23 dist->n = 0; in qdist_init()28 g_free(dist->entries); in qdist_destroy()36 return -1; in qdist_cmp_double()46 return qdist_cmp_double(a->x, b->x); in qdist_cmp()53 if (dist->n) { in qdist_add()57 entry = bsearch(&e, dist->entries, dist->n, sizeof(e), qdist_cmp); in qdist_add()[all …]
1 /* SPDX-License-Identifier: MIT */3 * fbif.h -- Xen virtual frame buffer device12 /* Out events (frontend -> backend) */22 * Capable frontend sets feature-update in xenstore.23 * Backend requests it by setting request-update in xenstore.38 * Capable backend sets feature-resize in xenstore.62 /* In events (backend -> frontend) */71 * refresh. Frontends that keep the framebuffer constantly up-to-date74 * those have been requested), then use the update frequency to guide133 * framebuffer with a max resolution of 12,800x10,240. Should[all …]
4 * Copyright (c) 2017-2020 Subbaraya Sundeep <sundeep.lkml@gmail.com>28 #include "system/address-spaces.h"29 #include "hw/char/serial-mm.h"30 #include "hw/arm/msf2-soc.h"32 #include "hw/qdev-clock.h"48 * eSRAM max size is 80k without SECDED(Single error correction and66 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); in m2sxxx_soc_initfn()68 object_initialize_child(obj, "sysreg", &s->sysreg, TYPE_MSF2_SYSREG); in m2sxxx_soc_initfn()70 object_initialize_child(obj, "timer", &s->timer, TYPE_MSS_TIMER); in m2sxxx_soc_initfn()73 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_MSS_SPI); in m2sxxx_soc_initfn()[all …]
24 #include "qemu/error-report.h"39 #include "hw/ide/ide-bus.h"40 #include "hw/ide/ahci-sysbus.h"44 #include "hw/pci-host/gpex.h"45 #include "hw/qdev-properties.h"53 #include "target/arm/cpu-qom.h"64 * Generic timer frequency in Hz (which drives both the CPU generic timers65 * and the SBSA watchdog-timer). Older (<2.11) versions of the TF-A firmware68 * Starting with Armv8.6 CPU 1GHz timer frequency is mandated.110 #define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref")[all …]
4 * Copyright (c) 2018-2021 BALATON Zoltan17 #include "hw/or-irq.h"18 #include "hw/pci-host/mv64361.h"22 #include "hw/qdev-properties.h"28 #include "hw/fw-path-provider.h"31 #include "qemu/error-report.h"34 #include "system/address-spaces.h"35 #include "qom/qom-qobject.h"55 #define H_PRIVILEGE -3 /* Caller not privileged */56 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */[all …]
34 …int64_t tce, unsigned perm, unsigned pgsize) "liobn=0x%"PRIx64" 0x%"PRIx64" -> 0x%"PRIx64" perm=%u…40 …uint32_t pgmask) "buid=0x%"PRIx64" addr=0x%"PRIx32", %u windows available, max window size=0x%"PRI…124 ppc_decr_store(uint32_t nr_bits, uint64_t decr, uint64_t value) "%d-bit 0x%016" PRIx64 " => 0x%016"…134 ppc40x_set_tb_clk(uint32_t value) "new frequency %" PRIu32135 ppc40x_timers_init(uint32_t value) "frequency %" PRIu32143 ppc_dcr_read(uint32_t addr, uint32_t val) "DRCN[0x%x] -> 0x%x"144 ppc_dcr_write(uint32_t addr, uint32_t val) "DRCN[0x%x] <- 0x%x"
4 * Copyright (c) 2015-2017, IBM Corporation.25 #include "hw/qdev-properties.h"61 occ->occmisc = val; in pnv_occ_set_misc()64 * OCCMISC IRQ bit triggers the interrupt on a 0->1 edge, but not clear in pnv_occ_set_misc()65 * how that is handled in PSI so it is level-triggered here, which is not in pnv_occ_set_misc()68 qemu_set_irq(occ->psi_irq, !!(val & OCCMISC_PSI_IRQ)); in pnv_occ_set_misc()73 pnv_occ_set_misc(occ, occ->occmisc | OCCMISC_PSI_IRQ | OCCMISC_IRQ_SHMEM); in pnv_occ_raise_msg_irq()85 val = occ->occmisc; in pnv_occ_power8_xscom_read()102 pnv_occ_set_misc(occ, occ->occmisc & val); in pnv_occ_power8_xscom_write()105 pnv_occ_set_misc(occ, occ->occmisc | val); in pnv_occ_power8_xscom_write()[all …]
4 * Copyright (c) 2003-2007 Jocelyn Mayer36 #include "qemu/error-report.h"42 #include "hw/qdev-properties.h"74 cpu_ppc_tb_reset(&cpu->env); in ppc_prep_reset()83 return (k->read)(nvram, addr); in nvram_read()89 (k->write)(nvram, addr, val); in nvram_write()127 uint32_t max) in NVRAM_set_string() argument131 for (i = 0; i < max && str[i] != '\0'; i++) { in NVRAM_set_string()135 nvram_write(nvram, addr + max - 1, '\0'); in NVRAM_set_string()195 pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR, in PPC_NVRAM_set_params()[all …]
2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu15 * 5) OTP (One-Time Programmable) memory with stored serial number39 #include "qemu/error-report.h"65 /* CLINT timebase frequency */99 uint64_t mem_size = ms->ram_size; in create_fdt()111 "sifive,plic-1.0.0", "riscv,plic0" in create_fdt()114 fdt = ms->fdt = create_device_tree(&s->fdt_size); in create_fdt()122 "sifive,hifive-unleashed-a00"); in create_fdt()123 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); in create_fdt()[all …]
6 * @exp10: exponent of 10, a multiple of 3 between -18 and 18 inclusive.35 * * if @str fits in the buffer, pstrcpy() does not zero-fill the37 * * if @str is too long, pstrcpy() will copy the first @buf_size-165 * @buf must already contain a NUL-terminated string, or the95 * Test whether @str starts with the case-insensitive prefix @val.100 * Returns: true if @str starts with case-insensitive prefix @val,133 * so now points to a NUL-terminated string corresponding to the177 * @freq_hz: frequency to stringify179 * Return human readable string for frequency @freq_hz.202 * three different cachelines. In qemu-img usage, we find that in buffer_is_zero_sample3()[all …]
... WARNING: %s is too long (%d - max: %d) - truncated Root Path * ...
4 * Copyright (C) 2006-2008 Qumranet Technologies11 * See the COPYING file in the top-level directory.16 #include "qapi/qapi-events-run-state.h"28 #include "standard-headers/asm-x86/kvm_para.h"29 #include "hw/xen/interface/arch-x86/cpuid.h"32 #include "host-cpu.h"39 #include "../confidential-guest.h"42 #include "xen-emu.h"44 #include "hyperv-proto.h"47 #include "qemu/host-utils.h"[all …]
3 ** File: fmopl.c -- software implementation of FM sound generator41 /* -------------------- for debug --------------------- */49 /* -------------------- preliminary define section --------------------- */54 #define DELTAT_MIXING_LEVEL (1) /* DELTA-T ADPCM MIXING LEVEL */56 #define FREQ_BITS 24 /* frequency turn */59 #define FREQ_RATE (1<<(FREQ_BITS-20))63 #define OPL_OUTSB (TL_BITS+3-16) /* OPL output final shift 16bit */65 #define OPL_MINOUT (-0x8000<<OPL_OUTSB)67 /* -------------------- quality selection --------------------- */91 #define VIB_SHIFT (32-9)[all …]
1 /* SPDX-License-Identifier: BSD-3-Clause */8 #include "standard-headers/linux/virtio_types.h"132 /* 0 ... virtio_snd_config::jacks - 1 */172 /* 0 ... virtio_snd_config::streams - 1 */279 /* 0 ... virtio_snd_config::streams - 1 */297 /* 0 ... virtio_snd_config::chmaps - 1 */311 VIRTIO_SND_CHMAP_LFE, /* low frequency (LFE) */362 /* 0 ... virtio_snd_config::controls - 1 */406 /* index for an element with a non-unique name */417 uint32_t max; member[all …]
5 * - http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf6 * - Chapter 19 UART Controller7 * - Appendix B for Register details27 #include "chardev/char-fe.h"28 #include "chardev/char-serial.h"34 #include "hw/qdev-clock.h"35 #include "hw/qdev-properties-system.h"127 s->r[R_SR] = 0; in uart_update_status()129 s->r[R_SR] |= s->rx_count == CADENCE_UART_RX_FIFO_SIZE ? UART_SR_INTR_RFUL in uart_update_status()131 s->r[R_SR] |= !s->rx_count ? UART_SR_INTR_REMPTY : 0; in uart_update_status()[all …]
15 #include "qemu/error-report.h"57 /* YMMH format is the same as XMM, but for bits 128-255 */187 cpu_get_fp80(&tmp->tmp_mant, &tmp->tmp_exp, tmp->parent->d); in fpreg_pre_save()196 tmp->parent->d = cpu_set_fp80(tmp->tmp_mant, tmp->tmp_exp); in fpreg_post_load()222 CPUX86State *env = &cpu->env; in cpu_pre_save()224 env->v_tpr = env->int_ctl & V_TPR_MASK; in cpu_pre_save()226 env->fpus_vmstate = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11; in cpu_pre_save()227 env->fptag_vmstate = 0; in cpu_pre_save()229 env->fptag_vmstate |= ((!env->fptags[i]) << i); in cpu_pre_save()232 env->fpregs_format_vmstate = 0; in cpu_pre_save()[all …]
1 /* SPDX-License-Identifier: LGPL-2.1-or-later */15 #include "exec/cpu-common.h" /* for qemu_ram_get_fd() */16 #include "qemu/defer-call.h"18 #include "qemu/error-report.h"21 #include "system/block-backend.h"24 #include "block/block-io.h"38 * libblkio is not thread-safe so this lock protects ->blkio and39 * ->blkioq.43 struct blkioq *blkioq; /* make this multi-queue in the future... */55 * Protects ->bounce_pool, ->bounce_bufs, ->bounce_available.[all …]