Lines Matching +full:max +full:- +full:frequency
15 #include "qemu/error-report.h"
57 /* YMMH format is the same as XMM, but for bits 128-255 */
187 cpu_get_fp80(&tmp->tmp_mant, &tmp->tmp_exp, tmp->parent->d); in fpreg_pre_save()
196 tmp->parent->d = cpu_set_fp80(tmp->tmp_mant, tmp->tmp_exp); in fpreg_post_load()
222 CPUX86State *env = &cpu->env; in cpu_pre_save()
224 env->v_tpr = env->int_ctl & V_TPR_MASK; in cpu_pre_save()
226 env->fpus_vmstate = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11; in cpu_pre_save()
227 env->fptag_vmstate = 0; in cpu_pre_save()
229 env->fptag_vmstate |= ((!env->fptags[i]) << i); in cpu_pre_save()
232 env->fpregs_format_vmstate = 0; in cpu_pre_save()
241 if (!(env->cr[0] & CR0_PE_MASK) && in cpu_pre_save()
242 (env->segs[R_CS].flags >> DESC_DPL_SHIFT & 3) != 0) { in cpu_pre_save()
243 env->segs[R_CS].flags &= ~(env->segs[R_CS].flags & DESC_DPL_MASK); in cpu_pre_save()
244 env->segs[R_DS].flags &= ~(env->segs[R_DS].flags & DESC_DPL_MASK); in cpu_pre_save()
245 env->segs[R_ES].flags &= ~(env->segs[R_ES].flags & DESC_DPL_MASK); in cpu_pre_save()
246 env->segs[R_FS].flags &= ~(env->segs[R_FS].flags & DESC_DPL_MASK); in cpu_pre_save()
247 env->segs[R_GS].flags &= ~(env->segs[R_GS].flags & DESC_DPL_MASK); in cpu_pre_save()
248 env->segs[R_SS].flags &= ~(env->segs[R_SS].flags & DESC_DPL_MASK); in cpu_pre_save()
256 * 1) We must be able to extract vCPU nested-state from KVM. in cpu_pre_save()
258 * 2) In case vCPU is running in guest-mode and it has a pending exception, in cpu_pre_save()
265 (!env->nested_state || in cpu_pre_save()
266 (!kvm_has_exception_payload() && (env->hflags & HF_GUEST_MASK) && in cpu_pre_save()
267 env->exception_injected))) { in cpu_pre_save()
271 return -EINVAL; in cpu_pre_save()
288 * or vCPU is not in guest-mode, it is not important to in cpu_pre_save()
292 * In order to preserve better backwards-compatible migration, in cpu_pre_save()
297 if (env->exception_pending && !(env->hflags & HF_GUEST_MASK)) { in cpu_pre_save()
298 env->exception_pending = 0; in cpu_pre_save()
299 env->exception_injected = 1; in cpu_pre_save()
301 if (env->exception_has_payload) { in cpu_pre_save()
302 if (env->exception_nr == EXCP01_DB) { in cpu_pre_save()
303 env->dr[6] = env->exception_payload; in cpu_pre_save()
304 } else if (env->exception_nr == EXCP0E_PAGE) { in cpu_pre_save()
305 env->cr[2] = env->exception_payload; in cpu_pre_save()
317 CPUX86State *env = &cpu->env; in cpu_post_load()
320 if (env->tsc_khz && env->user_tsc_khz && in cpu_post_load()
321 env->tsc_khz != env->user_tsc_khz) { in cpu_post_load()
322 error_report("Mismatch between user-specified TSC frequency and " in cpu_post_load()
323 "migrated TSC frequency"); in cpu_post_load()
324 return -EINVAL; in cpu_post_load()
327 if (env->fpregs_format_vmstate) { in cpu_post_load()
328 error_report("Unsupported old non-softfloat CPU state"); in cpu_post_load()
329 return -EINVAL; in cpu_post_load()
339 if (!(env->cr[0] & CR0_PE_MASK) && in cpu_post_load()
340 (env->segs[R_CS].flags >> DESC_DPL_SHIFT & 3) != 0) { in cpu_post_load()
341 env->segs[R_CS].flags &= ~(env->segs[R_CS].flags & DESC_DPL_MASK); in cpu_post_load()
342 env->segs[R_DS].flags &= ~(env->segs[R_DS].flags & DESC_DPL_MASK); in cpu_post_load()
343 env->segs[R_ES].flags &= ~(env->segs[R_ES].flags & DESC_DPL_MASK); in cpu_post_load()
344 env->segs[R_FS].flags &= ~(env->segs[R_FS].flags & DESC_DPL_MASK); in cpu_post_load()
345 env->segs[R_GS].flags &= ~(env->segs[R_GS].flags & DESC_DPL_MASK); in cpu_post_load()
346 env->segs[R_SS].flags &= ~(env->segs[R_SS].flags & DESC_DPL_MASK); in cpu_post_load()
354 env->hflags &= ~HF_CPL_MASK; in cpu_post_load()
355 env->hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; in cpu_post_load()
358 if ((env->hflags & HF_GUEST_MASK) && in cpu_post_load()
359 (!env->nested_state || in cpu_post_load()
360 !(env->nested_state->flags & KVM_STATE_NESTED_GUEST_MODE))) { in cpu_post_load()
361 error_report("vCPU set in guest-mode inconsistent with " in cpu_post_load()
363 return -EINVAL; in cpu_post_load()
379 if ((env->exception_nr != -1) && in cpu_post_load()
380 !env->exception_pending && !env->exception_injected) { in cpu_post_load()
381 env->exception_injected = 1; in cpu_post_load()
384 env->fpstt = (env->fpus_vmstate >> 11) & 7; in cpu_post_load()
385 env->fpus = env->fpus_vmstate & ~0x3800; in cpu_post_load()
386 env->fptag_vmstate ^= 0xff; in cpu_post_load()
388 env->fptags[i] = (env->fptag_vmstate >> i) & 1; in cpu_post_load()
399 let the helper re-enable them. */ in cpu_post_load()
400 dr7 = env->dr[7]; in cpu_post_load()
401 env->dr[7] = dr7 & ~(DR7_GLOBAL_BP_MASK | DR7_LOCAL_BP_MASK); in cpu_post_load()
412 return cpu->env.async_pf_en_msr != 0; in async_pf_msr_needed()
419 return cpu->env.async_pf_int_msr != 0; in async_pf_int_msr_needed()
426 return cpu->env.pv_eoi_en_msr != 0; in pv_eoi_msr_needed()
433 return cpu->env.steal_time_msr != 0; in steal_time_msr_needed()
439 CPUX86State *env = &cpu->env; in exception_info_needed()
442 * It is important to save exception-info only in case in exception_info_needed()
448 return env->exception_pending && (env->hflags & HF_GUEST_MASK); in exception_info_needed()
470 return cpu->env.poll_control_msr != 1; in poll_control_msr_needed()
531 CPUX86State *env = &cpu->env; in fpop_ip_dp_needed()
533 return env->fpop != 0 || env->fpip != 0 || env->fpdp != 0; in fpop_ip_dp_needed()
552 CPUX86State *env = &cpu->env; in tsc_adjust_needed()
554 return env->tsc_adjust != 0; in tsc_adjust_needed()
571 CPUX86State *env = &cpu->env; in msr_smi_count_needed()
573 return cpu->migrate_smi_count && env->msr_smi_count != 0; in msr_smi_count_needed()
590 CPUX86State *env = &cpu->env; in tscdeadline_needed()
592 return env->tsc_deadline != 0; in tscdeadline_needed()
609 CPUX86State *env = &cpu->env; in misc_enable_needed()
611 return env->msr_ia32_misc_enable != MSR_IA32_MISC_ENABLE_DEFAULT; in misc_enable_needed()
617 CPUX86State *env = &cpu->env; in feature_control_needed()
619 return env->msr_ia32_feature_control != 0; in feature_control_needed()
647 CPUX86State *env = &cpu->env; in pmu_enable_needed()
650 if (env->msr_fixed_ctr_ctrl || env->msr_global_ctrl || in pmu_enable_needed()
651 env->msr_global_status || env->msr_global_ovf_ctrl) { in pmu_enable_needed()
655 if (env->msr_fixed_counters[i]) { in pmu_enable_needed()
660 if (env->msr_gp_counters[i] || env->msr_gp_evtsel[i]) { in pmu_enable_needed()
688 CPUX86State *env = &cpu->env; in mpx_needed()
692 if (env->bnd_regs[i].lb || env->bnd_regs[i].ub) { in mpx_needed()
697 if (env->bndcs_regs.cfgu || env->bndcs_regs.sts) { in mpx_needed()
701 return !!env->msr_bndcfgs; in mpx_needed()
721 CPUX86State *env = &cpu->env; in hyperv_hypercall_enable_needed()
723 return env->msr_hv_hypercall != 0 || env->msr_hv_guest_os_id != 0; in hyperv_hypercall_enable_needed()
741 CPUX86State *env = &cpu->env; in hyperv_vapic_enable_needed()
743 return env->msr_hv_vapic != 0; in hyperv_vapic_enable_needed()
760 CPUX86State *env = &cpu->env; in hyperv_time_enable_needed()
762 return env->msr_hv_tsc != 0; in hyperv_time_enable_needed()
779 CPUX86State *env = &cpu->env; in hyperv_crash_enable_needed()
783 if (env->msr_hv_crash_params[i]) { in hyperv_crash_enable_needed()
804 CPUX86State *env = &cpu->env; in hyperv_runtime_enable_needed()
810 return env->msr_hv_runtime != 0; in hyperv_runtime_enable_needed()
827 CPUX86State *env = &cpu->env; in hyperv_synic_enable_needed()
830 if (env->msr_hv_synic_control != 0 || in hyperv_synic_enable_needed()
831 env->msr_hv_synic_evt_page != 0 || in hyperv_synic_enable_needed()
832 env->msr_hv_synic_msg_page != 0) { in hyperv_synic_enable_needed()
836 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) { in hyperv_synic_enable_needed()
837 if (env->msr_hv_synic_sint[i] != 0) { in hyperv_synic_enable_needed()
870 CPUX86State *env = &cpu->env; in hyperv_stimer_enable_needed()
873 for (i = 0; i < ARRAY_SIZE(env->msr_hv_stimer_config); i++) { in hyperv_stimer_enable_needed()
874 if (env->msr_hv_stimer_config[i] || env->msr_hv_stimer_count[i]) { in hyperv_stimer_enable_needed()
897 CPUX86State *env = &cpu->env; in hyperv_reenlightenment_enable_needed()
899 return env->msr_hv_reenlightenment_control != 0 || in hyperv_reenlightenment_enable_needed()
900 env->msr_hv_tsc_emulation_control != 0 || in hyperv_reenlightenment_enable_needed()
901 env->msr_hv_tsc_emulation_status != 0; in hyperv_reenlightenment_enable_needed()
907 CPUX86State *env = &cpu->env; in hyperv_reenlightenment_post_load()
910 * KVM doesn't fully support re-enlightenment notifications so we need to in hyperv_reenlightenment_post_load()
911 * make sure TSC frequency doesn't change upon migration. in hyperv_reenlightenment_post_load()
913 if ((env->msr_hv_reenlightenment_control & HV_REENLIGHTENMENT_ENABLE_BIT) && in hyperv_reenlightenment_post_load()
914 !env->user_tsc_khz) { in hyperv_reenlightenment_post_load()
915 error_report("Guest enabled re-enlightenment notifications, " in hyperv_reenlightenment_post_load()
916 "'tsc-frequency=' has to be specified"); in hyperv_reenlightenment_post_load()
917 return -EINVAL; in hyperv_reenlightenment_post_load()
940 CPUX86State *env = &cpu->env; in avx512_needed()
944 if (env->opmask_regs[i]) { in avx512_needed()
950 #define ENV_XMM(reg, field) (env->xmm_regs[reg].ZMM_Q(field)) in avx512_needed()
986 CPUX86State *env = &cpu->env; in xss_needed()
988 return env->xss != 0; in xss_needed()
1005 CPUX86State *env = &cpu->env; in umwait_needed()
1007 return env->umwait != 0; in umwait_needed()
1024 CPUX86State *env = &cpu->env; in pkru_needed()
1026 return env->pkru != 0; in pkru_needed()
1043 CPUX86State *env = &cpu->env; in pkrs_needed()
1045 return env->pkrs != 0; in pkrs_needed()
1062 CPUX86State *env = &cpu->env; in tsc_khz_needed()
1064 return env->tsc_khz; in tsc_khz_needed()
1083 return (nested_state->size > in vmx_vmcs12_needed()
1103 return (nested_state->size > in vmx_shadow_vmcs12_needed()
1124 return (nested_state->format == KVM_STATE_NESTED_FORMAT_VMX && in vmx_nested_state_needed()
1125 nested_state->hdr.vmx.vmxon_pa != -1ull); in vmx_nested_state_needed()
1155 return (nested_state->format == KVM_STATE_NESTED_FORMAT_SVM && in svm_nested_state_needed()
1156 nested_state->size > offsetof(struct kvm_nested_state, data)); in svm_nested_state_needed()
1176 CPUX86State *env = &cpu->env; in nested_state_needed()
1178 return (env->nested_state && in nested_state_needed()
1179 (vmx_nested_state_needed(env->nested_state) || in nested_state_needed()
1180 svm_nested_state_needed(env->nested_state))); in nested_state_needed()
1186 CPUX86State *env = &cpu->env; in nested_state_post_load()
1187 struct kvm_nested_state *nested_state = env->nested_state; in nested_state_post_load()
1198 return -EINVAL; in nested_state_post_load()
1204 * than the max size that our kernel support in nested_state_post_load()
1206 if (nested_state->size < min_nested_state_len) { in nested_state_post_load()
1209 nested_state->size, min_nested_state_len); in nested_state_post_load()
1210 return -EINVAL; in nested_state_post_load()
1212 if (nested_state->size > max_nested_state_len) { in nested_state_post_load()
1214 "nested_state->size=%d, max=%d", in nested_state_post_load()
1215 nested_state->size, max_nested_state_len); in nested_state_post_load()
1216 return -EINVAL; in nested_state_post_load()
1220 if ((nested_state->format != KVM_STATE_NESTED_FORMAT_VMX) && in nested_state_post_load()
1221 (nested_state->format != KVM_STATE_NESTED_FORMAT_SVM)) { in nested_state_post_load()
1223 nested_state->format); in nested_state_post_load()
1224 return -EINVAL; in nested_state_post_load()
1288 CPUX86State *env = &cpu->env; in mcg_ext_ctl_needed()
1289 return cpu->enable_lmce && env->mcg_ext_ctl; in mcg_ext_ctl_needed()
1306 CPUX86State *env = &cpu->env; in spec_ctrl_needed()
1308 return env->spec_ctrl != 0; in spec_ctrl_needed()
1326 CPUX86State *env = &cpu->env; in amd_tsc_scale_msr_needed()
1328 return (env->features[FEAT_SVM] & CPUID_SVM_TSCSCALE); in amd_tsc_scale_msr_needed()
1346 CPUX86State *env = &cpu->env; in intel_pt_enable_needed()
1349 if (env->msr_rtit_ctrl || env->msr_rtit_status || in intel_pt_enable_needed()
1350 env->msr_rtit_output_base || env->msr_rtit_output_mask || in intel_pt_enable_needed()
1351 env->msr_rtit_cr3_match) { in intel_pt_enable_needed()
1356 if (env->msr_rtit_addrs[i]) { in intel_pt_enable_needed()
1383 CPUX86State *env = &cpu->env; in virt_ssbd_needed()
1385 return env->virt_ssbd != 0; in virt_ssbd_needed()
1402 CPUX86State *env = &cpu->env; in svm_npt_needed()
1404 return !!(env->hflags2 & HF2_NPT_MASK); in svm_npt_needed()
1422 CPUX86State *env = &cpu->env; in svm_guest_needed()
1424 return tcg_enabled() && env->int_ctl; in svm_guest_needed()
1442 CPUX86State *env = &cpu->env; in intel_efer32_needed()
1444 return env->efer != 0; in intel_efer32_needed()
1462 CPUX86State *env = &cpu->env; in msr_tsx_ctrl_needed()
1464 return env->features[FEAT_ARCH_CAPABILITIES] & ARCH_CAP_TSX_CTRL_MSR; in msr_tsx_ctrl_needed()
1481 CPUX86State *env = &cpu->env; in intel_sgx_msrs_needed()
1483 return !!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_SGX_LC); in intel_sgx_msrs_needed()
1500 CPUX86State *env = &cpu->env; in pdptrs_needed()
1501 return env->pdptrs_valid; in pdptrs_needed()
1507 CPUX86State *env = &cpu->env; in pdptrs_post_load()
1508 env->pdptrs_valid = true; in pdptrs_post_load()
1528 CPUX86State *env = &cpu->env; in xfd_msrs_needed()
1530 return !!(env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD); in xfd_msrs_needed()
1548 CPUX86State *env = &cpu->env; in msr_hwcr_needed()
1550 return env->msr_hwcr != 0; in msr_hwcr_needed()
1568 CPUX86State *env = &cpu->env; in intel_fred_msrs_needed()
1570 return !!(env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED); in intel_fred_msrs_needed()
1595 CPUX86State *env = &cpu->env; in amx_xtile_needed()
1597 return !!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE); in amx_xtile_needed()
1616 CPUX86State *env = &cpu->env; in arch_lbr_needed()
1618 return !!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR); in arch_lbr_needed()
1637 CPUX86State *env = &cpu->env; in triple_fault_needed()
1639 return env->triple_fault_pending; in triple_fault_needed()
1720 /* KVM-related states */