Lines Matching +full:max +full:- +full:frequency
5 * - http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
6 * - Chapter 19 UART Controller
7 * - Appendix B for Register details
27 #include "chardev/char-fe.h"
28 #include "chardev/char-serial.h"
34 #include "hw/qdev-clock.h"
35 #include "hw/qdev-properties-system.h"
127 s->r[R_SR] = 0; in uart_update_status()
129 s->r[R_SR] |= s->rx_count == CADENCE_UART_RX_FIFO_SIZE ? UART_SR_INTR_RFUL in uart_update_status()
131 s->r[R_SR] |= !s->rx_count ? UART_SR_INTR_REMPTY : 0; in uart_update_status()
132 s->r[R_SR] |= s->rx_count >= s->r[R_RTRIG] ? UART_SR_INTR_RTRIG : 0; in uart_update_status()
134 s->r[R_SR] |= s->tx_count == CADENCE_UART_TX_FIFO_SIZE ? UART_SR_INTR_TFUL in uart_update_status()
136 s->r[R_SR] |= !s->tx_count ? UART_SR_INTR_TEMPTY : 0; in uart_update_status()
137 s->r[R_SR] |= s->tx_count >= s->r[R_TTRIG] ? UART_SR_TTRIG : 0; in uart_update_status()
139 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK; in uart_update_status()
140 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0; in uart_update_status()
141 qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR])); in uart_update_status()
148 if (s->r[R_RTOR]) { in fifo_trigger_update()
149 s->r[R_CISR] |= UART_INTR_TIMEOUT; in fifo_trigger_update()
156 s->rx_wpos = 0; in uart_rx_reset()
157 s->rx_count = 0; in uart_rx_reset()
158 qemu_chr_fe_accept_input(&s->chr); in uart_rx_reset()
163 s->tx_count = 0; in uart_tx_reset()
170 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK, in uart_send_breaks()
178 input_clk = clock_get_hz(s->refclk); in uart_parameters_setup()
180 baud_rate = (s->r[R_MR] & UART_MR_CLKS) ? input_clk / 8 : input_clk; in uart_parameters_setup()
181 baud_rate /= (s->r[R_BRGR] * (s->r[R_BDIV] + 1)); in uart_parameters_setup()
188 switch (s->r[R_MR] & UART_MR_PAR) { in uart_parameters_setup()
202 switch (s->r[R_MR] & UART_MR_CHRL) { in uart_parameters_setup()
214 switch (s->r[R_MR] & UART_MR_NBSTOP) { in uart_parameters_setup()
226 * Avoid division-by-zero below. in uart_parameters_setup()
231 s->char_tx_time = (NANOSECONDS_PER_SECOND / ssp.speed) * packet_size; in uart_parameters_setup()
232 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); in uart_parameters_setup()
242 if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) { in uart_can_receive()
248 ret = MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE); in uart_can_receive()
249 ch_mode = s->r[R_MR] & UART_MR_CHMODE; in uart_can_receive()
252 ret = MIN(ret, CADENCE_UART_RX_FIFO_SIZE - s->rx_count); in uart_can_receive()
255 ret = MIN(ret, CADENCE_UART_TX_FIFO_SIZE - s->tx_count); in uart_can_receive()
262 if (s->r[R_CR] & UART_CR_TXRST) { in uart_ctrl_update()
266 if (s->r[R_CR] & UART_CR_RXRST) { in uart_ctrl_update()
270 s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST); in uart_ctrl_update()
272 if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) { in uart_ctrl_update()
283 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { in uart_write_rx_fifo()
287 if (s->rx_count == CADENCE_UART_RX_FIFO_SIZE) { in uart_write_rx_fifo()
288 s->r[R_CISR] |= UART_INTR_ROVR; in uart_write_rx_fifo()
291 s->rx_fifo[s->rx_wpos] = buf[i]; in uart_write_rx_fifo()
292 s->rx_wpos = (s->rx_wpos + 1) % CADENCE_UART_RX_FIFO_SIZE; in uart_write_rx_fifo()
293 s->rx_count++; in uart_write_rx_fifo()
295 timer_mod(s->fifo_trigger_handle, new_rx_time + in uart_write_rx_fifo()
296 (s->char_tx_time * 4)); in uart_write_rx_fifo()
307 /* instant drain the fifo when there's no back-end */ in cadence_uart_xmit()
308 if (!qemu_chr_fe_backend_connected(&s->chr)) { in cadence_uart_xmit()
309 s->tx_count = 0; in cadence_uart_xmit()
313 if (!s->tx_count) { in cadence_uart_xmit()
317 ret = qemu_chr_fe_write(&s->chr, s->tx_fifo, s->tx_count); in cadence_uart_xmit()
320 s->tx_count -= ret; in cadence_uart_xmit()
321 memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_count); in cadence_uart_xmit()
324 if (s->tx_count) { in cadence_uart_xmit()
325 guint r = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, in cadence_uart_xmit()
328 s->tx_count = 0; in cadence_uart_xmit()
340 if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) { in uart_write_tx_fifo()
344 if (size > CADENCE_UART_TX_FIFO_SIZE - s->tx_count) { in uart_write_tx_fifo()
345 size = CADENCE_UART_TX_FIFO_SIZE - s->tx_count; in uart_write_tx_fifo()
352 s->r[R_CISR] |= UART_INTR_ROVR; in uart_write_tx_fifo()
355 memcpy(s->tx_fifo + s->tx_count, buf, size); in uart_write_tx_fifo()
356 s->tx_count += size; in uart_write_tx_fifo()
364 uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE; in uart_receive()
380 if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) { in uart_event()
395 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { in uart_read_rx_fifo()
399 if (s->rx_count) { in uart_read_rx_fifo()
400 uint32_t rx_rpos = (CADENCE_UART_RX_FIFO_SIZE + s->rx_wpos - in uart_read_rx_fifo()
401 s->rx_count) % CADENCE_UART_RX_FIFO_SIZE; in uart_read_rx_fifo()
402 *c = s->rx_fifo[rx_rpos]; in uart_read_rx_fifo()
403 s->rx_count--; in uart_read_rx_fifo()
405 qemu_chr_fe_accept_input(&s->chr); in uart_read_rx_fifo()
419 if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) { in uart_write()
432 s->r[R_IMR] |= value; in uart_write()
435 s->r[R_IMR] &= ~value; in uart_write()
440 s->r[R_CISR] &= ~value; in uart_write()
443 switch (s->r[R_MR] & UART_MR_CHMODE) { in uart_write()
455 s->r[offset] = value; in uart_write()
461 s->r[offset] = value; in uart_write()
465 s->r[offset] = value; in uart_write()
488 if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) { in uart_read()
501 c = s->r[offset]; in uart_read()
519 s->r[R_CR] = 0x00000128; in cadence_uart_reset_init()
520 s->r[R_IMR] = 0; in cadence_uart_reset_init()
521 s->r[R_CISR] = 0; in cadence_uart_reset_init()
522 s->r[R_RTRIG] = 0x00000020; in cadence_uart_reset_init()
523 s->r[R_BRGR] = 0x0000028B; in cadence_uart_reset_init()
524 s->r[R_BDIV] = 0x0000000F; in cadence_uart_reset_init()
525 s->r[R_TTRIG] = 0x00000020; in cadence_uart_reset_init()
542 s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL, in cadence_uart_realize()
545 qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive, in cadence_uart_realize()
562 memory_region_init_io(&s->iomem, obj, &uart_ops, s, "uart", 0x1000); in cadence_uart_init()
563 sysbus_init_mmio(sbd, &s->iomem); in cadence_uart_init()
564 sysbus_init_irq(sbd, &s->irq); in cadence_uart_init()
566 s->refclk = qdev_init_clock_in(DEVICE(obj), "refclk", in cadence_uart_init()
568 /* initialize the frequency in case the clock remains unconnected */ in cadence_uart_init()
569 clock_set_hz(s->refclk, UART_DEFAULT_REF_CLK); in cadence_uart_init()
571 s->char_tx_time = (NANOSECONDS_PER_SECOND / 9600) * 10; in cadence_uart_init()
578 /* the frequency will be overridden if the refclk field is present */ in cadence_uart_pre_load()
579 clock_set_hz(s->refclk, UART_DEFAULT_REF_CLK); in cadence_uart_pre_load()
588 if (s->r[R_BRGR] < 1 || s->r[R_BRGR] & ~0xFFFF || in cadence_uart_post_load()
589 s->r[R_BDIV] <= 3 || s->r[R_BDIV] & ~0xFF) { in cadence_uart_post_load()
629 dc->realize = cadence_uart_realize; in cadence_uart_class_init()
630 dc->vmsd = &vmstate_cadence_uart; in cadence_uart_class_init()
631 rc->phases.enter = cadence_uart_reset_init; in cadence_uart_class_init()
632 rc->phases.hold = cadence_uart_reset_hold; in cadence_uart_class_init()