Lines Matching +full:max +full:- +full:frequency
4 * Copyright (c) 2015-2017, IBM Corporation.
25 #include "hw/qdev-properties.h"
61 occ->occmisc = val; in pnv_occ_set_misc()
64 * OCCMISC IRQ bit triggers the interrupt on a 0->1 edge, but not clear in pnv_occ_set_misc()
65 * how that is handled in PSI so it is level-triggered here, which is not in pnv_occ_set_misc()
68 qemu_set_irq(occ->psi_irq, !!(val & OCCMISC_PSI_IRQ)); in pnv_occ_set_misc()
73 pnv_occ_set_misc(occ, occ->occmisc | OCCMISC_PSI_IRQ | OCCMISC_IRQ_SHMEM); in pnv_occ_raise_msg_irq()
85 val = occ->occmisc; in pnv_occ_power8_xscom_read()
102 pnv_occ_set_misc(occ, occ->occmisc & val); in pnv_occ_power8_xscom_write()
105 pnv_occ_set_misc(occ, occ->occmisc | val); in pnv_occ_power8_xscom_write()
121 * occ-sensor sanity check that asserts the sensor in pnv_occ_common_area_read()
180 dc->desc = "PowerNV OCC Controller (POWER8)"; in pnv_occ_power8_class_init()
181 poc->opal_shared_memory_offset = P8_HOMER_OPAL_DATA_OFFSET; in pnv_occ_power8_class_init()
182 poc->opal_shared_memory_version = 0x02; in pnv_occ_power8_class_init()
183 poc->xscom_size = PNV_XSCOM_OCC_SIZE; in pnv_occ_power8_class_init()
184 poc->xscom_ops = &pnv_occ_power8_xscom_ops; in pnv_occ_power8_class_init()
208 val = occ->occmisc; in pnv_occ_power9_xscom_read()
228 pnv_occ_set_misc(occ, occ->occmisc | val); in pnv_occ_power9_xscom_write()
254 dc->desc = "PowerNV OCC Controller (POWER9)"; in pnv_occ_power9_class_init()
255 poc->opal_shared_memory_offset = P9_HOMER_OPAL_DATA_OFFSET; in pnv_occ_power9_class_init()
256 poc->opal_shared_memory_version = 0x90; in pnv_occ_power9_class_init()
257 poc->xscom_size = PNV9_XSCOM_OCC_SIZE; in pnv_occ_power9_class_init()
258 poc->xscom_ops = &pnv_occ_power9_xscom_ops; in pnv_occ_power9_class_init()
259 assert(!dc->user_creatable); in pnv_occ_power9_class_init()
274 dc->desc = "PowerNV OCC Controller (POWER10)"; in pnv_occ_power10_class_init()
275 poc->opal_shared_memory_offset = P9_HOMER_OPAL_DATA_OFFSET; in pnv_occ_power10_class_init()
276 poc->opal_shared_memory_version = 0xA0; in pnv_occ_power10_class_init()
277 poc->xscom_size = PNV9_XSCOM_OCC_SIZE; in pnv_occ_power10_class_init()
278 poc->xscom_ops = &pnv_occ_power9_xscom_ops; in pnv_occ_power10_class_init()
279 assert(!dc->user_creatable); in pnv_occ_power10_class_init()
300 timer_mod(&occ->state_machine_timer, next); in occ_state_machine_timer()
308 PnvHomer *homer = occ->homer; in pnv_occ_realize()
316 occ->occmisc = 0; in pnv_occ_realize()
319 pnv_xscom_region_init(&occ->xscom_regs, OBJECT(dev), poc->xscom_ops, in pnv_occ_realize()
320 occ, "xscom-occ", poc->xscom_size); in pnv_occ_realize()
323 memory_region_init_io(&occ->sram_regs, OBJECT(dev), &pnv_occ_sram_ops, in pnv_occ_realize()
324 occ, "occ-common-area", in pnv_occ_realize()
327 qdev_init_gpio_out(dev, &occ->psi_irq, 1); in pnv_occ_realize()
329 timer_init_ms(&occ->state_machine_timer, QEMU_CLOCK_VIRTUAL, in pnv_occ_realize()
331 timer_mod(&occ->state_machine_timer, OCC_POLL_MS); in pnv_occ_realize()
342 dc->realize = pnv_occ_realize; in pnv_occ_class_init()
344 dc->user_creatable = false; in pnv_occ_class_init()
368 * - tab to space conversion
369 * - Type conversions u8->uint8_t s8->int8_t __be16->uint16_t etc
370 * - __packed -> QEMU_PACKED
392 * OCC-OPAL Shared Memory Region
395 * https://github.com/open-power/docs/blob/master/occ/OCC_OpenPwr_FW_Interfaces.pdf
398 * - 0x01, 0x02 : P8
399 * https://github.com/open-power/occ/blob/master_p8/src/occ/proc/proc_pstate.h
401 * - 0x90 : P9
402 * https://github.com/open-power/occ/blob/master/src/occ_405/proc/proc_pstate.h
403 * In 0x90 the data is separated into :-
404 * -- Static Data (struct occ_pstate_table): Data is written once by OCC
405 * -- Dynamic Data (struct occ_dynamic_data): Data is updated at runtime
407 * struct occ_pstate_table - Pstate table layout
410 * @v2.throttle: Reason for limiting the max pstate
417 * @v#.pstates: Pstate-id and frequency list from Pmax to Pmin
418 * @v#.pstates.id: Pstate-id
419 * @v#.pstates.flags: Pstate-flag(reserved)
422 * @v#.pstates.freq_khz: Frequency in KHz
423 * @v#.core_max[1..N]: Max pstate with N active cores
492 * OPAL-OCC Command Response Interface
494 * OPAL-OCC Command Buffer
496 * ---------------------------------------------------------------------
500 * ---------------------------------------------------------------------
501 * | ….OPAL Command Data up to max of Cmd Data Length 4090 bytes |
503 * ---------------------------------------------------------------------
507 * -----------------------------------------------------------------
510 * -----------------------------------------------------------------
513 * -----------------------------------------------------------------
515 * struct opal_command_buffer - Defines the layout of OPAL command buffer
533 * OPAL-OCC Response Buffer
535 * ---------------------------------------------------------------------
539 * ---------------------------------------------------------------------
540 * | ….OPAL Response Data up to max of Rsp Data Length 8698 bytes |
542 * ---------------------------------------------------------------------
546 * -----------------------------------------------------------------
549 * -----------------------------------------------------------------
552 * -----------------------------------------------------------------
554 * struct occ_response_buffer - Defines the layout of OCC response buffer
573 * OCC-OPAL Shared Memory Interface Dynamic Data Vx90
575 * struct occ_dynamic_data - Contains runtime attributes
582 * @cpu_throttle: Reason for limiting the max pstate
651 PnvHomer *homer = occ->homer; in occ_write_static_data()
652 hwaddr static_addr = homer->base + poc->opal_shared_memory_offset; in occ_write_static_data()
659 error_setg(errp, "OCC: cannot write OCC-OPAL static data"); in occ_write_static_data()
671 PnvHomer *homer = occ->homer; in occ_read_dynamic_data()
672 hwaddr static_addr = homer->base + poc->opal_shared_memory_offset; in occ_read_dynamic_data()
680 error_setg(errp, "OCC: cannot read OCC-OPAL dynamic data"); in occ_read_dynamic_data()
692 PnvHomer *homer = occ->homer; in occ_write_dynamic_data()
693 hwaddr static_addr = homer->base + poc->opal_shared_memory_offset; in occ_write_dynamic_data()
701 error_setg(errp, "OCC: cannot write OCC-OPAL dynamic data"); in occ_write_dynamic_data()
713 struct opal_command_buffer *cmd = &dynamic_data->cmd; in occ_opal_send_response()
714 struct occ_response_buffer *rsp = &dynamic_data->rsp; in occ_opal_send_response()
716 rsp->request_id = cmd->request_id; in occ_opal_send_response()
717 rsp->cmd = cmd->cmd; in occ_opal_send_response()
718 rsp->status = status; in occ_opal_send_response()
719 rsp->data_size = cpu_to_be16(datalen); in occ_opal_send_response()
721 memcpy(rsp->data, data, datalen); in occ_opal_send_response()
727 rsp->flag = OCC_FLAG_RSP_READY; in occ_opal_send_response()
728 cmd->flag = 0; in occ_opal_send_response()
742 struct opal_command_buffer *cmd = &dynamic_data->cmd; in occ_opal_process_command()
743 struct occ_response_buffer *rsp = &dynamic_data->rsp; in occ_opal_process_command()
745 if (rsp->flag == 0) { in occ_opal_process_command()
746 /* Spend one "tick" in the in-progress state */ in occ_opal_process_command()
747 rsp->flag = OCC_FLAG_CMD_IN_PROGRESS; in occ_opal_process_command()
749 } else if (rsp->flag != OCC_FLAG_CMD_IN_PROGRESS) { in occ_opal_process_command()
755 switch (cmd->cmd) { in occ_opal_process_command()
758 if (be16_to_cpu(cmd->data_size) != 2) { in occ_opal_process_command()
761 (uint8_t *)&dynamic_data->cur_pwr_cap, in occ_opal_process_command()
764 data = be16_to_cpu(*(uint16_t *)cmd->data); in occ_opal_process_command()
766 dynamic_data->pwr_cap_type = 0x00; /* none */ in occ_opal_process_command()
769 dynamic_data->pwr_cap_type = 0x02; /* user set in-band */ in occ_opal_process_command()
776 dynamic_data->cur_pwr_cap = cpu_to_be16(data); in occ_opal_process_command()
779 (uint8_t *)&dynamic_data->cur_pwr_cap, 2); in occ_opal_process_command()
812 PnvHomer *homer = occ->homer; in occ_init_homer_memory()
813 PnvChip *chip = homer->chip; in occ_init_homer_memory()
820 static_data.version = poc->opal_shared_memory_version; in occ_init_homer_memory()
821 switch (poc->opal_shared_memory_version) { in occ_init_homer_memory()
824 static_data.v2.pstate_min = -2; in occ_init_homer_memory()
825 static_data.v2.pstate_nom = -1; in occ_init_homer_memory()
826 static_data.v2.pstate_turbo = -1; in occ_init_homer_memory()
830 static_data.v2.pstates[1].id = -1; in occ_init_homer_memory()
832 static_data.v2.pstates[2].id = -2; in occ_init_homer_memory()
834 for (i = 0; i < chip->nr_cores; i++) { in occ_init_homer_memory()
839 if (chip->chip_id == 0) { in occ_init_homer_memory()
854 for (i = 0; i < chip->nr_cores; i++) { in occ_init_homer_memory()
859 if (chip->chip_id == 0) { in occ_init_homer_memory()
885 for (i = 0; i < chip->nr_cores; i++) { in occ_init_homer_memory()
903 switch (poc->opal_shared_memory_version) { in occ_init_homer_memory()