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/linux-5.10/Documentation/devicetree/bindings/media/i2c/
Dimx219.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sony 1/4.0-Inch 8Mpixel CMOS Digital Image Sensor
10 - Dave Stevenson <dave.stevenson@raspberrypi.com>
12 description: |-
13 The Sony imx219 is a 1/4.0-inch CMOS active pixel digital image sensor
16 Image data is sent through MIPI CSI-2, which is configured as either 2 or
30 VDIG-supply:
34 VANA-supply:
[all …]
Dtc358743.txt1 * Toshiba TC358743 HDMI-RX to MIPI CSI2-TX Bridge
3 The Toshiba TC358743 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts
4 a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C.
8 - compatible: value should be "toshiba,tc358743"
9 - clocks, clock-names: should contain a phandle link to the reference clock
14 - reset-gpios: gpio phandle GPIO connected to the reset pin
15 - interrupts: GPIO connected to the interrupt pin
16 - data-lanes: should be <1 2 3 4> for four-lane operation,
17 or <1 2> for two-lane operation
18 - clock-lanes: should be <0>
[all …]
Dov8856.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Dongchun Zhu <dongchun.zhu@mediatek.com>
13 description: |-
14 The Omnivision OV8856 is a high performance, 1/4-inch, 8 megapixel, CMOS
15 image sensor that delivers 3264x2448 at 30fps. It provides full-frame,
16 sub-sampled, and windowed 10-bit MIPI images in various formats via the
18 through I2C and two-wire SCCB. The sensor output is available via CSI-2
19 serial data output (up to 4-lane).
[all …]
/linux-5.10/arch/mips/cavium-octeon/executive/
Dcvmx-helper-errata.c7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
31 * contains functions called by cvmx-helper to workaround known
40 #include <asm/octeon/cvmx-helper-jtag.h>
43 * Due to errata G-720, the 2nd order CDR circuit on CN52XX pass
51 int lane; in __cvmx_helper_errata_qlm_disable_2nd_order_cdr() local
53 /* We need to load all four lanes of the QLM, a total of 1072 bits */ in __cvmx_helper_errata_qlm_disable_2nd_order_cdr()
54 for (lane = 0; lane < 4; lane++) { in __cvmx_helper_errata_qlm_disable_2nd_order_cdr()
56 * Each lane has 268 bits. We need to set in __cvmx_helper_errata_qlm_disable_2nd_order_cdr()
[all …]
/linux-5.10/Documentation/devicetree/bindings/display/bridge/
Dps8640.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Boichat <drinkcat@chromium.org>
11 - Enric Balletbo i Serra <enric.balletbo@collabora.com>
14 The PS8640 is a low power MIPI-to-eDP video format converter supporting
16 device accepts a single channel of MIPI DSI v1.1, with up to four lanes
17 plus clock, at a transmission rate up to 1.5Gbit/sec per lane. The
19 3.24Gbit/sec per lane.
29 powerdown-gpios:
[all …]
/linux-5.10/Documentation/devicetree/bindings/phy/
Dti,phy-j721e-wiz.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
19 power-domains:
24 description: clock-specifier to represent input to the WIZ
[all …]
Dxlnx,zynqmp-psgtr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/xlnx,zynqmp-psgtr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
14 GTR provides four lanes and is used by USB, SATA, PCIE, Display port and
18 "#phy-cells":
23 - description: The GTR lane
26 - description: The PHY type
28 - PHY_TYPE_DP
[all …]
/linux-5.10/Documentation/devicetree/bindings/pci/
Dti-pci.txt4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
10 - phys : list of PHY specifiers (used by generic PHY framework)
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
15 - num-lanes as specified in ../designware-pcie.txt
[all …]
Dmvebu-pci.txt5 - compatible: one of the following values:
6 marvell,armada-370-pcie
7 marvell,armada-xp-pcie
8 marvell,dove-pcie
9 marvell,kirkwood-pcie
10 - #address-cells, set to <3>
11 - #size-cells, set to <2>
12 - #interrupt-cells, set to <1>
13 - bus-range: PCI bus numbers covered
14 - device_type, set to "pci"
[all …]
Drockchip-pcie-host.txt4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
8 - compatible: Should contain "rockchip,rk3399-pcie"
9 - reg: Two register ranges as listed in the reg-names property
10 - reg-names: Must include the following names
11 - "axi-base"
12 - "apb-base"
13 - clocks: Must contain an entry for each entry in clock-names.
14 See ../clocks/clock-bindings.txt for details.
[all …]
/linux-5.10/drivers/nvdimm/
Dbtt.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (c) 2014-2015, Intel Corporation.
49 * A log group represents one log 'lane', and consists of four log entries.
50 * Two of the four entries are valid entries, and the remaining two are
60 * +-----------------+-----------------+
64 * +-----------------------------------+
68 * +-----------------+-----------------+
71 * +-----------------+-----------------+
75 * +-----------------------------------+
79 * +-----------------+-----------------+
[all …]
Dbtt.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2014-2015, Intel Corporation.
18 #include <linux/backing-dev.h>
29 return &arena->nd_btt->dev; in to_dev()
34 return offset + nd_btt->initial_offset; in adjust_initial_offset()
40 struct nd_btt *nd_btt = arena->nd_btt; in arena_read_bytes()
41 struct nd_namespace_common *ndns = nd_btt->ndns; in arena_read_bytes()
51 struct nd_btt *nd_btt = arena->nd_btt; in arena_write_bytes()
52 struct nd_namespace_common *ndns = nd_btt->ndns; in arena_write_bytes()
68 dev_WARN_ONCE(to_dev(arena), !IS_ALIGNED(arena->infooff, 512), in btt_info_write()
[all …]
/linux-5.10/drivers/gpu/drm/bridge/
Dtc358764.c1 // SPDX-License-Identifier: GPL-2.0
28 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
34 #define PPI_LANEENABLE 0x0134 /* Enables each lane */
36 #define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */
37 #define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */
38 #define PPI_D2S_CLRSIPOCOUNT 0x016C /* Assertion timer for Lane 2 */
39 #define PPI_D3S_CLRSIPOCOUNT 0x0170 /* Assertion timer for Lane 3 */
43 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
44 #define DSI_LANEENABLE 0x0210 /* Enables each lane */
125 #define SYS_RST_I2CS BIT(0) /* Reset I2C-Slave controller */
[all …]
/linux-5.10/drivers/gpu/drm/i915/display/
Dintel_dpio_phy.c2 * Copyright © 2014-2016 Intel Corporation
39 * IOSF-SB port.
42 * houses a common lane part which contains the PLL and other common
43 * logic. CH0 common lane also contains the IOSF-SB logic for the
53 * each spline is made up of one Physical Access Coding Sub-Layer
55 * and four TX lanes. The TX lanes are used as DP lanes or TMDS
58 * Additionally the PHY also contains an AUX lane with AUX blocks
64 * Generally on VLV/CHV the common lane corresponds to the pipe and
97 * ---------------------------------
100 * |---------------|---------------| Display PHY
[all …]
/linux-5.10/drivers/pci/controller/
Dpcie-rockchip.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Wenrui Li <wenrui.li@rock-chips.com>
23 #include "pcie-rockchip.h"
27 struct device *dev = rockchip->dev; in rockchip_pcie_parse_dt()
29 struct device_node *node = dev->of_node; in rockchip_pcie_parse_dt()
33 if (rockchip->is_rc) { in rockchip_pcie_parse_dt()
36 "axi-base"); in rockchip_pcie_parse_dt()
37 rockchip->reg_base = devm_pci_remap_cfg_resource(dev, regs); in rockchip_pcie_parse_dt()
38 if (IS_ERR(rockchip->reg_base)) in rockchip_pcie_parse_dt()
[all …]
/linux-5.10/arch/arm/boot/dts/
Darmada-xp-synology-ds414.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
12 * were delivered with an older version of u-boot that left internal
17 * installing it from u-boot prompt) or adjust the Devive Tree
21 /dts-v1/;
23 #include <dt-bindings/input/input.h>
24 #include <dt-bindings/gpio/gpio.h>
25 #include "armada-xp-mv78230.dtsi"
29 compatible = "synology,ds414", "marvell,armadaxp-mv78230",
30 "marvell,armadaxp", "marvell,armada-370-xp";
[all …]
/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dst,stm32-fmc2-ebi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 asynchronous static devices (such as PSNOR, PSRAM or other memory-mapped
14 - to translate AXI transactions into the appropriate external device
16 - to meet the access time requirements of the external devices
22 - Christophe Kerello <christophe.kerello@st.com>
26 const: st,stm32mp1-fmc2-ebi
37 "#address-cells":
[all …]
/linux-5.10/include/drm/
Ddrm_mipi_dsi.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2012-2013, Samsung Electronics, Co., Ltd.
24 * struct mipi_dsi_msg - read/write DSI buffer
49 * struct mipi_dsi_packet - represents a MIPI DSI packet in protocol format
51 * @header: the four bytes that make up the header (Data ID, Word Count or
67 * struct mipi_dsi_host_ops - DSI bus operations
94 * struct mipi_dsi_host - DSI host device
119 /* enable hsync-end packets in vsync-pulse and v-porch area */
121 /* disable hfront-porch area */
123 /* disable hback-porch area */
[all …]
Ddrm_dp_helper.h43 * MST: Multistream Transport - part of DP 1.2a
54 /* bits per component for non-RAW */
181 # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */
372 * 0x80-0x8f describe downstream port capabilities, but there are two layouts
375 * four bytes wide, starting with the one byte from the base info. As of
450 /* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */
885 /* 0-5 sink count */
1061 /* Link Training (LT)-tunable PHY Repeaters */
1117 /* peer device type - DP 1.2a Table 2-92 */
1124 /* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */
[all …]
/linux-5.10/drivers/edac/
Dppc4xx_edac.c1 // SPDX-License-Identifier: GPL-2.0-only
29 * - Support for registered- and non-registered DDR1 and DDR2 memory.
30 * - 32-bit or 16-bit memory interface with optional ECC.
34 * - 4-bit SEC/DED
35 * - Aligned-nibble error detect
36 * - Bypass mode
38 * - Two (2) memory banks/ranks.
39 * - Up to 1 GiB per bank/rank in 32-bit mode and up to 512 MiB per
40 * bank/rank in 16-bit mode.
44 * - 64-bit or 32-bit memory interface with optional ECC.
[all …]
/linux-5.10/arch/powerpc/sysdev/
Dfsl_rio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * - fixed maintenance access routines, check for aligned access
11 * - Added Port-Write message handling
12 * - Added Machine Check exception handling
24 #include <linux/dma-mapping.h>
39 #undef DEBUG_PW /* Port-Write debugging */
78 "3: li %1,-1\n" \
84 : "b" (addr), "i" (-EFAULT), "0" (err))
105 entry = search_exception_tables(regs->nip); in fsl_rio_mcheck_exception()
107 pr_debug("RIO: %s - MC Exception handled\n", in fsl_rio_mcheck_exception()
[all …]
/linux-5.10/include/uapi/misc/
Dxilinx_sdfec.h1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
3 * Xilinx SD-FEC
26 (XSDFEC_LDPC_SC_TABLE_ADDR_HIGH - XSDFEC_LDPC_SC_TABLE_ADDR_BASE)
28 (XSDFEC_LDPC_LA_TABLE_ADDR_HIGH - XSDFEC_LDPC_LA_TABLE_ADDR_BASE)
30 (XSDFEC_LDPC_QC_TABLE_ADDR_HIGH - XSDFEC_LDPC_QC_TABLE_ADDR_BASE)
33 * enum xsdfec_code - Code Type.
47 * enum xsdfec_order - Order
49 * @XSDFEC_OUT_OF_ORDER: Out-of-order execution of blocks.
60 * enum xsdfec_turbo_alg - Turbo Algorithm Type.
61 * @XSDFEC_MAX_SCALE: Max Log-Map algorithm with extrinsic scaling. When
[all …]
/linux-5.10/drivers/thunderbolt/
Dtb_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Thunderbolt driver - Port/Switch config area registers
6 * ports. Every port contains up to four config regions (HOPS, PORT, SWITCH,
65 * struct tb_cap_extended_short - Switch extended short capability
80 * struct tb_cap_extended_long - Switch extended long capability
98 * struct tb_cap_any - Structure capable of hold every capability
293 /* Lane adapter registers */
/linux-5.10/arch/mips/pci/
Dpcie-octeon.c17 #include <asm/octeon/cvmx-npei-defs.h>
18 #include <asm/octeon/cvmx-pciercx-defs.h>
19 #include <asm/octeon/cvmx-pescx-defs.h>
20 #include <asm/octeon/cvmx-pexp-defs.h>
21 #include <asm/octeon/cvmx-pemx-defs.h>
22 #include <asm/octeon/cvmx-dpi-defs.h>
23 #include <asm/octeon/cvmx-sli-defs.h>
24 #include <asm/octeon/cvmx-sriox-defs.h>
25 #include <asm/octeon/cvmx-helper-errata.h>
26 #include <asm/octeon/pci-octeon.h>
[all …]
/linux-5.10/drivers/media/i2c/
Dimx274.c1 // SPDX-License-Identifier: GPL-2.0
3 * imx274.c - IMX274 CMOS Image Sensor driver
23 #include <linux/v4l2-mediabus.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-device.h>
28 #include <media/v4l2-subdev.h>
48 #define IMX274_GAIN_SHIFT_MASK ((1 << IMX274_GAIN_SHIFT) - 1)
58 / (2048 - IMX274_GAIN_REG_MAX))
76 * register SHR is limited to (SVR value + 1) x VMAX value - 4
163 * Adjustment (CSI-2)" in the datasheet)
[all …]

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