1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2018 Samsung Electronics Co., Ltd
4 *
5 * Authors:
6 * Andrzej Hajda <a.hajda@samsung.com>
7 * Maciej Purski <m.purski@samsung.com>
8 */
9
10 #include <linux/delay.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/module.h>
13 #include <linux/of_graph.h>
14 #include <linux/regulator/consumer.h>
15
16 #include <video/mipi_display.h>
17
18 #include <drm/drm_atomic_helper.h>
19 #include <drm/drm_bridge.h>
20 #include <drm/drm_crtc.h>
21 #include <drm/drm_fb_helper.h>
22 #include <drm/drm_mipi_dsi.h>
23 #include <drm/drm_of.h>
24 #include <drm/drm_panel.h>
25 #include <drm/drm_print.h>
26 #include <drm/drm_probe_helper.h>
27
28 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
29 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
30
31 /* PPI layer registers */
32 #define PPI_STARTPPI 0x0104 /* START control bit */
33 #define PPI_LPTXTIMECNT 0x0114 /* LPTX timing signal */
34 #define PPI_LANEENABLE 0x0134 /* Enables each lane */
35 #define PPI_TX_RX_TA 0x013C /* BTA timing parameters */
36 #define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */
37 #define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */
38 #define PPI_D2S_CLRSIPOCOUNT 0x016C /* Assertion timer for Lane 2 */
39 #define PPI_D3S_CLRSIPOCOUNT 0x0170 /* Assertion timer for Lane 3 */
40 #define PPI_START_FUNCTION 1
41
42 /* DSI layer registers */
43 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
44 #define DSI_LANEENABLE 0x0210 /* Enables each lane */
45 #define DSI_RX_START 1
46
47 /* Video path registers */
48 #define VP_CTRL 0x0450 /* Video Path Control */
49 #define VP_CTRL_MSF(v) FLD_VAL(v, 0, 0) /* Magic square in RGB666 */
50 #define VP_CTRL_VTGEN(v) FLD_VAL(v, 4, 4) /* Use chip clock for timing */
51 #define VP_CTRL_EVTMODE(v) FLD_VAL(v, 5, 5) /* Event mode */
52 #define VP_CTRL_RGB888(v) FLD_VAL(v, 8, 8) /* RGB888 mode */
53 #define VP_CTRL_VSDELAY(v) FLD_VAL(v, 31, 20) /* VSYNC delay */
54 #define VP_CTRL_HSPOL BIT(17) /* Polarity of HSYNC signal */
55 #define VP_CTRL_DEPOL BIT(18) /* Polarity of DE signal */
56 #define VP_CTRL_VSPOL BIT(19) /* Polarity of VSYNC signal */
57 #define VP_HTIM1 0x0454 /* Horizontal Timing Control 1 */
58 #define VP_HTIM1_HBP(v) FLD_VAL(v, 24, 16)
59 #define VP_HTIM1_HSYNC(v) FLD_VAL(v, 8, 0)
60 #define VP_HTIM2 0x0458 /* Horizontal Timing Control 2 */
61 #define VP_HTIM2_HFP(v) FLD_VAL(v, 24, 16)
62 #define VP_HTIM2_HACT(v) FLD_VAL(v, 10, 0)
63 #define VP_VTIM1 0x045C /* Vertical Timing Control 1 */
64 #define VP_VTIM1_VBP(v) FLD_VAL(v, 23, 16)
65 #define VP_VTIM1_VSYNC(v) FLD_VAL(v, 7, 0)
66 #define VP_VTIM2 0x0460 /* Vertical Timing Control 2 */
67 #define VP_VTIM2_VFP(v) FLD_VAL(v, 23, 16)
68 #define VP_VTIM2_VACT(v) FLD_VAL(v, 10, 0)
69 #define VP_VFUEN 0x0464 /* Video Frame Timing Update Enable */
70
71 /* LVDS registers */
72 #define LV_MX0003 0x0480 /* Mux input bit 0 to 3 */
73 #define LV_MX0407 0x0484 /* Mux input bit 4 to 7 */
74 #define LV_MX0811 0x0488 /* Mux input bit 8 to 11 */
75 #define LV_MX1215 0x048C /* Mux input bit 12 to 15 */
76 #define LV_MX1619 0x0490 /* Mux input bit 16 to 19 */
77 #define LV_MX2023 0x0494 /* Mux input bit 20 to 23 */
78 #define LV_MX2427 0x0498 /* Mux input bit 24 to 27 */
79 #define LV_MX(b0, b1, b2, b3) (FLD_VAL(b0, 4, 0) | FLD_VAL(b1, 12, 8) | \
80 FLD_VAL(b2, 20, 16) | FLD_VAL(b3, 28, 24))
81
82 /* Input bit numbers used in mux registers */
83 enum {
84 LVI_R0,
85 LVI_R1,
86 LVI_R2,
87 LVI_R3,
88 LVI_R4,
89 LVI_R5,
90 LVI_R6,
91 LVI_R7,
92 LVI_G0,
93 LVI_G1,
94 LVI_G2,
95 LVI_G3,
96 LVI_G4,
97 LVI_G5,
98 LVI_G6,
99 LVI_G7,
100 LVI_B0,
101 LVI_B1,
102 LVI_B2,
103 LVI_B3,
104 LVI_B4,
105 LVI_B5,
106 LVI_B6,
107 LVI_B7,
108 LVI_HS,
109 LVI_VS,
110 LVI_DE,
111 LVI_L0
112 };
113
114 #define LV_CFG 0x049C /* LVDS Configuration */
115 #define LV_PHY0 0x04A0 /* LVDS PHY 0 */
116 #define LV_PHY0_RST(v) FLD_VAL(v, 22, 22) /* PHY reset */
117 #define LV_PHY0_IS(v) FLD_VAL(v, 15, 14)
118 #define LV_PHY0_ND(v) FLD_VAL(v, 4, 0) /* Frequency range select */
119 #define LV_PHY0_PRBS_ON(v) FLD_VAL(v, 20, 16) /* Clock/Data Flag pins */
120
121 /* System registers */
122 #define SYS_RST 0x0504 /* System Reset */
123 #define SYS_ID 0x0580 /* System ID */
124
125 #define SYS_RST_I2CS BIT(0) /* Reset I2C-Slave controller */
126 #define SYS_RST_I2CM BIT(1) /* Reset I2C-Master controller */
127 #define SYS_RST_LCD BIT(2) /* Reset LCD controller */
128 #define SYS_RST_BM BIT(3) /* Reset Bus Management controller */
129 #define SYS_RST_DSIRX BIT(4) /* Reset DSI-RX and App controller */
130 #define SYS_RST_REG BIT(5) /* Reset Register module */
131
132 #define LPX_PERIOD 2
133 #define TTA_SURE 3
134 #define TTA_GET 0x20000
135
136 /* Lane enable PPI and DSI register bits */
137 #define LANEENABLE_CLEN BIT(0)
138 #define LANEENABLE_L0EN BIT(1)
139 #define LANEENABLE_L1EN BIT(2)
140 #define LANEENABLE_L2EN BIT(3)
141 #define LANEENABLE_L3EN BIT(4)
142
143 /* LVCFG fields */
144 #define LV_CFG_LVEN BIT(0)
145 #define LV_CFG_LVDLINK BIT(1)
146 #define LV_CFG_CLKPOL1 BIT(2)
147 #define LV_CFG_CLKPOL2 BIT(3)
148
149 static const char * const tc358764_supplies[] = {
150 "vddc", "vddio", "vddlvds"
151 };
152
153 struct tc358764 {
154 struct device *dev;
155 struct drm_bridge bridge;
156 struct regulator_bulk_data supplies[ARRAY_SIZE(tc358764_supplies)];
157 struct gpio_desc *gpio_reset;
158 struct drm_bridge *panel_bridge;
159 int error;
160 };
161
tc358764_clear_error(struct tc358764 * ctx)162 static int tc358764_clear_error(struct tc358764 *ctx)
163 {
164 int ret = ctx->error;
165
166 ctx->error = 0;
167 return ret;
168 }
169
tc358764_read(struct tc358764 * ctx,u16 addr,u32 * val)170 static void tc358764_read(struct tc358764 *ctx, u16 addr, u32 *val)
171 {
172 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
173 ssize_t ret;
174
175 if (ctx->error)
176 return;
177
178 cpu_to_le16s(&addr);
179 ret = mipi_dsi_generic_read(dsi, &addr, sizeof(addr), val, sizeof(*val));
180 if (ret >= 0)
181 le32_to_cpus(val);
182
183 dev_dbg(ctx->dev, "read: %d, addr: %d\n", addr, *val);
184 }
185
tc358764_write(struct tc358764 * ctx,u16 addr,u32 val)186 static void tc358764_write(struct tc358764 *ctx, u16 addr, u32 val)
187 {
188 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
189 ssize_t ret;
190 u8 data[6];
191
192 if (ctx->error)
193 return;
194
195 data[0] = addr;
196 data[1] = addr >> 8;
197 data[2] = val;
198 data[3] = val >> 8;
199 data[4] = val >> 16;
200 data[5] = val >> 24;
201
202 ret = mipi_dsi_generic_write(dsi, data, sizeof(data));
203 if (ret < 0)
204 ctx->error = ret;
205 }
206
bridge_to_tc358764(struct drm_bridge * bridge)207 static inline struct tc358764 *bridge_to_tc358764(struct drm_bridge *bridge)
208 {
209 return container_of(bridge, struct tc358764, bridge);
210 }
211
tc358764_init(struct tc358764 * ctx)212 static int tc358764_init(struct tc358764 *ctx)
213 {
214 u32 v = 0;
215
216 tc358764_read(ctx, SYS_ID, &v);
217 if (ctx->error)
218 return tc358764_clear_error(ctx);
219 dev_info(ctx->dev, "ID: %#x\n", v);
220
221 /* configure PPI counters */
222 tc358764_write(ctx, PPI_TX_RX_TA, TTA_GET | TTA_SURE);
223 tc358764_write(ctx, PPI_LPTXTIMECNT, LPX_PERIOD);
224 tc358764_write(ctx, PPI_D0S_CLRSIPOCOUNT, 5);
225 tc358764_write(ctx, PPI_D1S_CLRSIPOCOUNT, 5);
226 tc358764_write(ctx, PPI_D2S_CLRSIPOCOUNT, 5);
227 tc358764_write(ctx, PPI_D3S_CLRSIPOCOUNT, 5);
228
229 /* enable four data lanes and clock lane */
230 tc358764_write(ctx, PPI_LANEENABLE, LANEENABLE_L3EN | LANEENABLE_L2EN |
231 LANEENABLE_L1EN | LANEENABLE_L0EN | LANEENABLE_CLEN);
232 tc358764_write(ctx, DSI_LANEENABLE, LANEENABLE_L3EN | LANEENABLE_L2EN |
233 LANEENABLE_L1EN | LANEENABLE_L0EN | LANEENABLE_CLEN);
234
235 /* start */
236 tc358764_write(ctx, PPI_STARTPPI, PPI_START_FUNCTION);
237 tc358764_write(ctx, DSI_STARTDSI, DSI_RX_START);
238
239 /* configure video path */
240 tc358764_write(ctx, VP_CTRL, VP_CTRL_VSDELAY(15) | VP_CTRL_RGB888(1) |
241 VP_CTRL_EVTMODE(1) | VP_CTRL_HSPOL | VP_CTRL_VSPOL);
242
243 /* reset PHY */
244 tc358764_write(ctx, LV_PHY0, LV_PHY0_RST(1) |
245 LV_PHY0_PRBS_ON(4) | LV_PHY0_IS(2) | LV_PHY0_ND(6));
246 tc358764_write(ctx, LV_PHY0, LV_PHY0_PRBS_ON(4) | LV_PHY0_IS(2) |
247 LV_PHY0_ND(6));
248
249 /* reset bridge */
250 tc358764_write(ctx, SYS_RST, SYS_RST_LCD);
251
252 /* set bit order */
253 tc358764_write(ctx, LV_MX0003, LV_MX(LVI_R0, LVI_R1, LVI_R2, LVI_R3));
254 tc358764_write(ctx, LV_MX0407, LV_MX(LVI_R4, LVI_R7, LVI_R5, LVI_G0));
255 tc358764_write(ctx, LV_MX0811, LV_MX(LVI_G1, LVI_G2, LVI_G6, LVI_G7));
256 tc358764_write(ctx, LV_MX1215, LV_MX(LVI_G3, LVI_G4, LVI_G5, LVI_B0));
257 tc358764_write(ctx, LV_MX1619, LV_MX(LVI_B6, LVI_B7, LVI_B1, LVI_B2));
258 tc358764_write(ctx, LV_MX2023, LV_MX(LVI_B3, LVI_B4, LVI_B5, LVI_L0));
259 tc358764_write(ctx, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_R6));
260 tc358764_write(ctx, LV_CFG, LV_CFG_CLKPOL2 | LV_CFG_CLKPOL1 |
261 LV_CFG_LVEN);
262
263 return tc358764_clear_error(ctx);
264 }
265
tc358764_reset(struct tc358764 * ctx)266 static void tc358764_reset(struct tc358764 *ctx)
267 {
268 gpiod_set_value(ctx->gpio_reset, 1);
269 usleep_range(1000, 2000);
270 gpiod_set_value(ctx->gpio_reset, 0);
271 usleep_range(1000, 2000);
272 }
273
tc358764_post_disable(struct drm_bridge * bridge)274 static void tc358764_post_disable(struct drm_bridge *bridge)
275 {
276 struct tc358764 *ctx = bridge_to_tc358764(bridge);
277 int ret;
278
279 tc358764_reset(ctx);
280 usleep_range(10000, 15000);
281 ret = regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
282 if (ret < 0)
283 dev_err(ctx->dev, "error disabling regulators (%d)\n", ret);
284 }
285
tc358764_pre_enable(struct drm_bridge * bridge)286 static void tc358764_pre_enable(struct drm_bridge *bridge)
287 {
288 struct tc358764 *ctx = bridge_to_tc358764(bridge);
289 int ret;
290
291 ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
292 if (ret < 0)
293 dev_err(ctx->dev, "error enabling regulators (%d)\n", ret);
294 usleep_range(10000, 15000);
295 tc358764_reset(ctx);
296 ret = tc358764_init(ctx);
297 if (ret < 0)
298 dev_err(ctx->dev, "error initializing bridge (%d)\n", ret);
299 }
300
tc358764_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)301 static int tc358764_attach(struct drm_bridge *bridge,
302 enum drm_bridge_attach_flags flags)
303 {
304 struct tc358764 *ctx = bridge_to_tc358764(bridge);
305
306 return drm_bridge_attach(bridge->encoder, ctx->panel_bridge,
307 bridge, flags);
308 }
309
310 static const struct drm_bridge_funcs tc358764_bridge_funcs = {
311 .post_disable = tc358764_post_disable,
312 .pre_enable = tc358764_pre_enable,
313 .attach = tc358764_attach,
314 };
315
tc358764_parse_dt(struct tc358764 * ctx)316 static int tc358764_parse_dt(struct tc358764 *ctx)
317 {
318 struct drm_bridge *panel_bridge;
319 struct device *dev = ctx->dev;
320 struct drm_panel *panel;
321 int ret;
322
323 ctx->gpio_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
324 if (IS_ERR(ctx->gpio_reset)) {
325 dev_err(dev, "no reset GPIO pin provided\n");
326 return PTR_ERR(ctx->gpio_reset);
327 }
328
329 ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, NULL);
330 if (ret)
331 return ret;
332
333 panel_bridge = devm_drm_panel_bridge_add(dev, panel);
334 if (IS_ERR(panel_bridge))
335 return PTR_ERR(panel_bridge);
336
337 ctx->panel_bridge = panel_bridge;
338 return 0;
339 }
340
tc358764_configure_regulators(struct tc358764 * ctx)341 static int tc358764_configure_regulators(struct tc358764 *ctx)
342 {
343 int i, ret;
344
345 for (i = 0; i < ARRAY_SIZE(ctx->supplies); ++i)
346 ctx->supplies[i].supply = tc358764_supplies[i];
347
348 ret = devm_regulator_bulk_get(ctx->dev, ARRAY_SIZE(ctx->supplies),
349 ctx->supplies);
350 if (ret < 0)
351 dev_err(ctx->dev, "failed to get regulators: %d\n", ret);
352
353 return ret;
354 }
355
tc358764_probe(struct mipi_dsi_device * dsi)356 static int tc358764_probe(struct mipi_dsi_device *dsi)
357 {
358 struct device *dev = &dsi->dev;
359 struct tc358764 *ctx;
360 int ret;
361
362 ctx = devm_kzalloc(dev, sizeof(struct tc358764), GFP_KERNEL);
363 if (!ctx)
364 return -ENOMEM;
365
366 mipi_dsi_set_drvdata(dsi, ctx);
367
368 ctx->dev = dev;
369
370 dsi->lanes = 4;
371 dsi->format = MIPI_DSI_FMT_RGB888;
372 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST
373 | MIPI_DSI_MODE_VIDEO_AUTO_VERT | MIPI_DSI_MODE_LPM;
374
375 ret = tc358764_parse_dt(ctx);
376 if (ret < 0)
377 return ret;
378
379 ret = tc358764_configure_regulators(ctx);
380 if (ret < 0)
381 return ret;
382
383 ctx->bridge.funcs = &tc358764_bridge_funcs;
384 ctx->bridge.type = DRM_MODE_CONNECTOR_LVDS;
385 ctx->bridge.of_node = dev->of_node;
386
387 drm_bridge_add(&ctx->bridge);
388
389 ret = mipi_dsi_attach(dsi);
390 if (ret < 0) {
391 drm_bridge_remove(&ctx->bridge);
392 dev_err(dev, "failed to attach dsi\n");
393 }
394
395 return ret;
396 }
397
tc358764_remove(struct mipi_dsi_device * dsi)398 static int tc358764_remove(struct mipi_dsi_device *dsi)
399 {
400 struct tc358764 *ctx = mipi_dsi_get_drvdata(dsi);
401
402 mipi_dsi_detach(dsi);
403 drm_bridge_remove(&ctx->bridge);
404
405 return 0;
406 }
407
408 static const struct of_device_id tc358764_of_match[] = {
409 { .compatible = "toshiba,tc358764" },
410 { }
411 };
412 MODULE_DEVICE_TABLE(of, tc358764_of_match);
413
414 static struct mipi_dsi_driver tc358764_driver = {
415 .probe = tc358764_probe,
416 .remove = tc358764_remove,
417 .driver = {
418 .name = "tc358764",
419 .owner = THIS_MODULE,
420 .of_match_table = tc358764_of_match,
421 },
422 };
423 module_mipi_dsi_driver(tc358764_driver);
424
425 MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>");
426 MODULE_AUTHOR("Maciej Purski <m.purski@samsung.com>");
427 MODULE_DESCRIPTION("MIPI-DSI based Driver for TC358764 DSI/LVDS Bridge");
428 MODULE_LICENSE("GPL v2");
429