Lines Matching +full:four +full:- +full:lane
1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * - fixed maintenance access routines, check for aligned access
11 * - Added Port-Write message handling
12 * - Added Machine Check exception handling
24 #include <linux/dma-mapping.h>
39 #undef DEBUG_PW /* Port-Write debugging */
78 "3: li %1,-1\n" \
84 : "b" (addr), "i" (-EFAULT), "0" (err))
105 entry = search_exception_tables(regs->nip); in fsl_rio_mcheck_exception()
107 pr_debug("RIO: %s - MC Exception handled\n", in fsl_rio_mcheck_exception()
111 regs->msr |= MSR_RI; in fsl_rio_mcheck_exception()
112 regs->nip = extable_fixup(entry); in fsl_rio_mcheck_exception()
123 * fsl_local_config_read - Generate a MPC85xx local config space read
131 * success or %-EINVAL on failure.
136 struct rio_priv *priv = mport->priv; in fsl_local_config_read()
139 *data = in_be32(priv->regs_win + offset); in fsl_local_config_read()
145 * fsl_local_config_write - Generate a MPC85xx local config space write
153 * success or %-EINVAL on failure.
158 struct rio_priv *priv = mport->priv; in fsl_local_config_write()
162 out_be32(priv->regs_win + offset, data); in fsl_local_config_write()
168 * fsl_rio_config_read - Generate a MPC85xx read maintenance transaction
178 * success or %-EINVAL on failure.
184 struct rio_priv *priv = mport->priv; in fsl_rio_config_read()
196 if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len)) in fsl_rio_config_read()
197 return -EINVAL; in fsl_rio_config_read()
201 out_be32(&priv->maint_atmu_regs->rowtar, in fsl_rio_config_read()
203 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10)); in fsl_rio_config_read()
205 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1)); in fsl_rio_config_read()
218 return -EINVAL; in fsl_rio_config_read()
233 * fsl_rio_config_write - Generate a MPC85xx write maintenance transaction
243 * success or %-EINVAL on failure.
249 struct rio_priv *priv = mport->priv; in fsl_rio_config_write()
261 if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len)) in fsl_rio_config_write()
262 return -EINVAL; in fsl_rio_config_write()
266 out_be32(&priv->maint_atmu_regs->rowtar, in fsl_rio_config_write()
268 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10)); in fsl_rio_config_write()
270 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1)); in fsl_rio_config_write()
282 ret = -EINVAL; in fsl_rio_config_write()
295 out_be32(&priv->inb_atmu_regs[i].riwar, 0); in fsl_rio_inbound_mem_init()
301 struct rio_priv *priv = mport->priv; in fsl_map_inb_mem()
308 if ((size & (size - 1)) != 0 || size > 0x400000000ULL) in fsl_map_inb_mem()
309 return -EINVAL; in fsl_map_inb_mem()
315 if (lstart & (base_size - 1)) in fsl_map_inb_mem()
316 return -EINVAL; in fsl_map_inb_mem()
317 if (rstart & (base_size - 1)) in fsl_map_inb_mem()
318 return -EINVAL; in fsl_map_inb_mem()
322 riwar = in_be32(&priv->inb_atmu_regs[i].riwar); in fsl_map_inb_mem()
325 win_start = ((u64)(in_be32(&priv->inb_atmu_regs[i].riwbar) & RIWBAR_BADD_MASK)) in fsl_map_inb_mem()
327 win_end = win_start + ((1 << ((riwar & RIWAR_SIZE_MASK) + 1)) - 1); in fsl_map_inb_mem()
329 return -EINVAL; in fsl_map_inb_mem()
334 riwar = in_be32(&priv->inb_atmu_regs[i].riwar); in fsl_map_inb_mem()
339 return -ENOMEM; in fsl_map_inb_mem()
341 out_be32(&priv->inb_atmu_regs[i].riwtar, lstart >> RIWTAR_TRAD_VAL_SHIFT); in fsl_map_inb_mem()
342 out_be32(&priv->inb_atmu_regs[i].riwbar, rstart >> RIWBAR_BADD_VAL_SHIFT); in fsl_map_inb_mem()
343 out_be32(&priv->inb_atmu_regs[i].riwar, RIWAR_ENABLE | RIWAR_TGINT_LOCAL | in fsl_map_inb_mem()
344 RIWAR_RDTYP_SNOOP | RIWAR_WRTYP_SNOOP | (base_size_log - 1)); in fsl_map_inb_mem()
352 struct rio_priv *priv = mport->priv; in fsl_unmap_inb_mem()
359 riwar = in_be32(&priv->inb_atmu_regs[i].riwar); in fsl_unmap_inb_mem()
363 riwtar = in_be32(&priv->inb_atmu_regs[i].riwtar); in fsl_unmap_inb_mem()
366 out_be32(&priv->inb_atmu_regs[i].riwar, riwar & ~RIWAR_ENABLE); in fsl_unmap_inb_mem()
407 str = "Single-lane 0"; in fsl_rio_info()
410 str = "Single-lane 2"; in fsl_rio_info()
413 str = "Four-lane"; in fsl_rio_info()
423 dev_info(dev, "Output port operating in 8-bit mode\n"); in fsl_rio_info()
425 dev_info(dev, "Input port operating in 8-bit mode\n"); in fsl_rio_info()
430 * fsl_rio_setup - Setup Freescale PowerPC RapidIO interface
434 * master port with system-specific info, and registers the
455 if (!dev->dev.of_node) { in fsl_rio_setup()
456 dev_err(&dev->dev, "Device OF-Node is NULL"); in fsl_rio_setup()
457 return -ENODEV; in fsl_rio_setup()
460 rc = of_address_to_resource(dev->dev.of_node, 0, ®s); in fsl_rio_setup()
462 dev_err(&dev->dev, "Can't get %pOF property 'reg'\n", in fsl_rio_setup()
463 dev->dev.of_node); in fsl_rio_setup()
464 return -EFAULT; in fsl_rio_setup()
466 dev_info(&dev->dev, "Of-device full name %pOF\n", in fsl_rio_setup()
467 dev->dev.of_node); in fsl_rio_setup()
468 dev_info(&dev->dev, "Regs: %pR\n", ®s); in fsl_rio_setup()
472 dev_err(&dev->dev, "Unable to map rio register window\n"); in fsl_rio_setup()
473 rc = -ENOMEM; in fsl_rio_setup()
479 rc = -ENOMEM; in fsl_rio_setup()
482 ops->lcread = fsl_local_config_read; in fsl_rio_setup()
483 ops->lcwrite = fsl_local_config_write; in fsl_rio_setup()
484 ops->cread = fsl_rio_config_read; in fsl_rio_setup()
485 ops->cwrite = fsl_rio_config_write; in fsl_rio_setup()
486 ops->dsend = fsl_rio_doorbell_send; in fsl_rio_setup()
487 ops->pwenable = fsl_rio_pw_enable; in fsl_rio_setup()
488 ops->open_outb_mbox = fsl_open_outb_mbox; in fsl_rio_setup()
489 ops->open_inb_mbox = fsl_open_inb_mbox; in fsl_rio_setup()
490 ops->close_outb_mbox = fsl_close_outb_mbox; in fsl_rio_setup()
491 ops->close_inb_mbox = fsl_close_inb_mbox; in fsl_rio_setup()
492 ops->add_outb_message = fsl_add_outb_message; in fsl_rio_setup()
493 ops->add_inb_buffer = fsl_add_inb_buffer; in fsl_rio_setup()
494 ops->get_inb_message = fsl_get_inb_message; in fsl_rio_setup()
495 ops->map_inb = fsl_map_inb_mem; in fsl_rio_setup()
496 ops->unmap_inb = fsl_unmap_inb_mem; in fsl_rio_setup()
498 rmu_node = of_parse_phandle(dev->dev.of_node, "fsl,srio-rmu-handle", 0); in fsl_rio_setup()
500 dev_err(&dev->dev, "No valid fsl,srio-rmu-handle property\n"); in fsl_rio_setup()
501 rc = -ENOENT; in fsl_rio_setup()
506 dev_err(&dev->dev, "Can't get %pOF property 'reg'\n", in fsl_rio_setup()
512 dev_err(&dev->dev, "Unable to map rmu register window\n"); in fsl_rio_setup()
513 rc = -ENOMEM; in fsl_rio_setup()
516 for_each_compatible_node(np, NULL, "fsl,srio-msg-unit") { in fsl_rio_setup()
522 np = of_find_compatible_node(NULL, NULL, "fsl,srio-dbell-unit"); in fsl_rio_setup()
524 dev_err(&dev->dev, "No fsl,srio-dbell-unit node\n"); in fsl_rio_setup()
525 rc = -ENODEV; in fsl_rio_setup()
530 dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_dbell'\n"); in fsl_rio_setup()
531 rc = -ENOMEM; in fsl_rio_setup()
534 dbell->dev = &dev->dev; in fsl_rio_setup()
535 dbell->bellirq = irq_of_parse_and_map(np, 1); in fsl_rio_setup()
536 dev_info(&dev->dev, "bellirq: %d\n", dbell->bellirq); in fsl_rio_setup()
543 rc = -ENOMEM; in fsl_rio_setup()
547 dbell->dbell_regs = (struct rio_dbell_regs *)(rmu_regs_win + in fsl_rio_setup()
551 np = of_find_compatible_node(NULL, NULL, "fsl,srio-port-write-unit"); in fsl_rio_setup()
553 dev_err(&dev->dev, "No fsl,srio-port-write-unit node\n"); in fsl_rio_setup()
554 rc = -ENODEV; in fsl_rio_setup()
559 dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_pw'\n"); in fsl_rio_setup()
560 rc = -ENOMEM; in fsl_rio_setup()
563 pw->dev = &dev->dev; in fsl_rio_setup()
564 pw->pwirq = irq_of_parse_and_map(np, 0); in fsl_rio_setup()
565 dev_info(&dev->dev, "pwirq: %d\n", pw->pwirq); in fsl_rio_setup()
571 rc = -ENOMEM; in fsl_rio_setup()
575 pw->pw_regs = (struct rio_pw_regs *)(rmu_regs_win + (u32)range_start); in fsl_rio_setup()
578 for_each_child_of_node(dev->dev.of_node, np) { in fsl_rio_setup()
579 port_index = of_get_property(np, "cell-index", NULL); in fsl_rio_setup()
581 dev_err(&dev->dev, "Can't get %pOF property 'cell-index'\n", in fsl_rio_setup()
588 dev_err(&dev->dev, "Can't get %pOF property 'ranges'\n", in fsl_rio_setup()
594 cell = of_get_property(np, "#address-cells", NULL); in fsl_rio_setup()
600 cell = of_get_property(np, "#size-cells", NULL); in fsl_rio_setup()
610 dev_info(&dev->dev, "%pOF: LAW start 0x%016llx, size 0x%016llx.\n", in fsl_rio_setup()
623 i = *port_index - 1; in fsl_rio_setup()
624 port->index = (unsigned char)i; in fsl_rio_setup()
628 dev_err(&dev->dev, "Can't alloc memory for 'priv'\n"); in fsl_rio_setup()
633 INIT_LIST_HEAD(&port->dbells); in fsl_rio_setup()
634 port->iores.start = range_start; in fsl_rio_setup()
635 port->iores.end = port->iores.start + range_size - 1; in fsl_rio_setup()
636 port->iores.flags = IORESOURCE_MEM; in fsl_rio_setup()
637 port->iores.name = "rio_io_win"; in fsl_rio_setup()
639 if (request_resource(&iomem_resource, &port->iores) < 0) { in fsl_rio_setup()
640 dev_err(&dev->dev, "RIO: Error requesting master port region" in fsl_rio_setup()
641 " 0x%016llx-0x%016llx\n", in fsl_rio_setup()
642 (u64)port->iores.start, (u64)port->iores.end); in fsl_rio_setup()
647 sprintf(port->name, "RIO mport %d", i); in fsl_rio_setup()
649 priv->dev = &dev->dev; in fsl_rio_setup()
650 port->dev.parent = &dev->dev; in fsl_rio_setup()
651 port->ops = ops; in fsl_rio_setup()
652 port->priv = priv; in fsl_rio_setup()
653 port->phys_efptr = 0x100; in fsl_rio_setup()
654 port->phys_rmap = 1; in fsl_rio_setup()
655 priv->regs_win = rio_regs_win; in fsl_rio_setup()
657 ccsr = in_be32(priv->regs_win + RIO_CCSR + i*0x20); in fsl_rio_setup()
660 if (in_be32((priv->regs_win + RIO_ESCSR + i*0x20)) & 1) { in fsl_rio_setup()
661 dev_err(&dev->dev, "Port %d is not ready. " in fsl_rio_setup()
664 out_be32(priv->regs_win in fsl_rio_setup()
666 /* Set 1x lane */ in fsl_rio_setup()
667 setbits32(priv->regs_win in fsl_rio_setup()
670 setbits32(priv->regs_win in fsl_rio_setup()
673 if (in_be32((priv->regs_win in fsl_rio_setup()
675 dev_err(&dev->dev, in fsl_rio_setup()
677 release_resource(&port->iores); in fsl_rio_setup()
682 dev_info(&dev->dev, "Port %d restart success!\n", i); in fsl_rio_setup()
684 fsl_rio_info(&dev->dev, ccsr); in fsl_rio_setup()
686 port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR)) in fsl_rio_setup()
688 dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n", in fsl_rio_setup()
689 port->sys_size ? 65536 : 256); in fsl_rio_setup()
691 if (port->host_deviceid >= 0) in fsl_rio_setup()
692 out_be32(priv->regs_win + RIO_GCCSR, RIO_PORT_GEN_HOST | in fsl_rio_setup()
695 out_be32(priv->regs_win + RIO_GCCSR, in fsl_rio_setup()
698 priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win in fsl_rio_setup()
702 priv->maint_atmu_regs = priv->atmu_regs + 1; in fsl_rio_setup()
703 priv->inb_atmu_regs = (struct rio_inb_atmu_regs __iomem *) in fsl_rio_setup()
704 (priv->regs_win + in fsl_rio_setup()
709 out_be32((priv->regs_win + RIO_ISR_AACR + i*0x80), in fsl_rio_setup()
713 out_be32(&priv->maint_atmu_regs->rowbar, in fsl_rio_setup()
714 port->iores.start >> 12); in fsl_rio_setup()
715 out_be32(&priv->maint_atmu_regs->rowar, in fsl_rio_setup()
716 0x80077000 | (ilog2(RIO_MAINT_WIN_SIZE) - 1)); in fsl_rio_setup()
718 priv->maint_win = ioremap(port->iores.start, in fsl_rio_setup()
726 dbell->mport[i] = port; in fsl_rio_setup()
727 pw->mport[i] = port; in fsl_rio_setup()
730 release_resource(&port->iores); in fsl_rio_setup()
739 rc = -ENOLINK; in fsl_rio_setup()
765 /* The probe function for RapidIO peer-to-peer network.
769 printk(KERN_INFO "Setting up RapidIO peer-to-peer network %pOF\n", in fsl_of_rio_rpn_probe()
770 dev->dev.of_node); in fsl_of_rio_rpn_probe()
784 .name = "fsl-of-rio",