Lines Matching +full:four +full:- +full:lane
2 * Copyright © 2014-2016 Intel Corporation
39 * IOSF-SB port.
42 * houses a common lane part which contains the PLL and other common
43 * logic. CH0 common lane also contains the IOSF-SB logic for the
53 * each spline is made up of one Physical Access Coding Sub-Layer
55 * and four TX lanes. The TX lanes are used as DP lanes or TMDS
58 * Additionally the PHY also contains an AUX lane with AUX blocks
64 * Generally on VLV/CHV the common lane corresponds to the pipe and
97 * ---------------------------------
100 * |---------------|---------------| Display PHY
102 * |-------|-------|-------|-------|
104 * ---------------------------------
106 * ---------------------------------
109 * -----------------
112 * |---------------| Display PHY
114 * |-------|-------|
116 * -----------------
118 * -----------------
122 * struct bxt_ddi_phy_info - Hold info for a broxton DDI phy
131 * @rcomp_phy: If -1, indicates this phy has its own rcomp resistor.
173 .rcomp_phy = -1,
195 .rcomp_phy = -1,
248 if (port == phy_info->channel[DPIO_CH0].port) { in bxt_port_to_phy_channel()
254 if (phy_info->dual_channel && in bxt_port_to_phy_channel()
255 port == phy_info->channel[DPIO_CH1].port) { in bxt_port_to_phy_channel()
262 drm_WARN(&dev_priv->drm, 1, "PHY not found for PORT %c", in bxt_port_to_phy_channel()
280 * can read only lane registers and we pick lanes 0/1 for that. in bxt_ddi_phy_set_signal_level()
297 drm_err(&dev_priv->drm, in bxt_ddi_phy_set_signal_level()
319 if (!(intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask)) in bxt_ddi_phy_is_enabled()
324 drm_dbg(&dev_priv->drm, in bxt_ddi_phy_is_enabled()
331 drm_dbg(&dev_priv->drm, in bxt_ddi_phy_is_enabled()
352 drm_err(&dev_priv->drm, "timeout waiting for PHY%d GRC\n", in bxt_phy_wait_grc_done()
366 if (phy_info->rcomp_phy != -1) in _bxt_ddi_phy_init()
367 dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy); in _bxt_ddi_phy_init()
370 drm_dbg(&dev_priv->drm, "DDI PHY %d already enabled, " in _bxt_ddi_phy_init()
375 drm_dbg(&dev_priv->drm, in _bxt_ddi_phy_init()
381 val |= phy_info->pwron_mask; in _bxt_ddi_phy_init()
392 if (intel_wait_for_register_fw(&dev_priv->uncore, in _bxt_ddi_phy_init()
397 drm_err(&dev_priv->drm, "timeout during PHY%d power on\n", in _bxt_ddi_phy_init()
417 if (phy_info->dual_channel) { in _bxt_ddi_phy_init()
423 if (phy_info->rcomp_phy != -1) { in _bxt_ddi_phy_init()
426 bxt_phy_wait_grc_done(dev_priv, phy_info->rcomp_phy); in _bxt_ddi_phy_init()
433 val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, in _bxt_ddi_phy_init()
434 phy_info->rcomp_phy); in _bxt_ddi_phy_init()
445 if (phy_info->reset_delay) in _bxt_ddi_phy_init()
446 udelay(phy_info->reset_delay); in _bxt_ddi_phy_init()
465 val &= ~phy_info->pwron_mask; in bxt_ddi_phy_uninit()
473 enum dpio_phy rcomp_phy = phy_info->rcomp_phy; in bxt_ddi_phy_init()
476 lockdep_assert_held(&dev_priv->power_domains.lock); in bxt_ddi_phy_init()
479 if (rcomp_phy != -1) in bxt_ddi_phy_init()
512 drm_dbg(&dev_priv->drm, "DDI PHY %d reg %pV [%08x] state mismatch: " in __phy_reg_verify_state()
553 if (phy_info->dual_channel) in bxt_ddi_phy_verify_state()
558 if (phy_info->rcomp_phy != -1) { in bxt_ddi_phy_verify_state()
559 u32 grc_code = dev_priv->bxt_phy_grc; in bxt_ddi_phy_verify_state()
598 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in bxt_ddi_phy_set_lane_optim_mask()
599 enum port port = encoder->port; in bxt_ddi_phy_set_lane_optim_mask()
602 int lane; in bxt_ddi_phy_set_lane_optim_mask() local
606 for (lane = 0; lane < 4; lane++) { in bxt_ddi_phy_set_lane_optim_mask()
608 BXT_PORT_TX_DW14_LN(phy, ch, lane)); in bxt_ddi_phy_set_lane_optim_mask()
615 if (lane_lat_optim_mask & BIT(lane)) in bxt_ddi_phy_set_lane_optim_mask()
618 intel_de_write(dev_priv, BXT_PORT_TX_DW14_LN(phy, ch, lane), in bxt_ddi_phy_set_lane_optim_mask()
626 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in bxt_ddi_phy_get_lane_lat_optim_mask()
627 enum port port = encoder->port; in bxt_ddi_phy_get_lane_lat_optim_mask()
630 int lane; in bxt_ddi_phy_get_lane_lat_optim_mask() local
636 for (lane = 0; lane < 4; lane++) { in bxt_ddi_phy_get_lane_lat_optim_mask()
638 BXT_PORT_TX_DW14_LN(phy, ch, lane)); in bxt_ddi_phy_get_lane_lat_optim_mask()
641 mask |= BIT(lane); in bxt_ddi_phy_get_lane_lat_optim_mask()
652 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in chv_set_phy_signal_level()
654 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); in chv_set_phy_signal_level()
656 enum pipe pipe = intel_crtc->pipe; in chv_set_phy_signal_level()
669 if (intel_crtc->config->lane_count > 2) { in chv_set_phy_signal_level()
682 if (intel_crtc->config->lane_count > 2) { in chv_set_phy_signal_level()
690 for (i = 0; i < intel_crtc->config->lane_count; i++) { in chv_set_phy_signal_level()
698 for (i = 0; i < intel_crtc->config->lane_count; i++) { in chv_set_phy_signal_level()
721 for (i = 0; i < intel_crtc->config->lane_count; i++) { in chv_set_phy_signal_level()
735 if (intel_crtc->config->lane_count > 2) { in chv_set_phy_signal_level()
748 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in chv_data_lane_soft_reset()
750 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in chv_data_lane_soft_reset()
751 enum pipe pipe = crtc->pipe; in chv_data_lane_soft_reset()
761 if (crtc_state->lane_count > 2) { in chv_data_lane_soft_reset()
778 if (crtc_state->lane_count > 2) { in chv_data_lane_soft_reset()
793 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in chv_phy_pre_pll_enable()
794 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in chv_phy_pre_pll_enable()
796 enum pipe pipe = crtc->pipe; in chv_phy_pre_pll_enable()
798 intel_dp_unused_lane_mask(crtc_state->lane_count); in chv_phy_pre_pll_enable()
802 * Must trick the second common lane into life. in chv_phy_pre_pll_enable()
806 dig_port->release_cl2_override = in chv_phy_pre_pll_enable()
813 /* Assert data lane reset */ in chv_phy_pre_pll_enable()
844 if (crtc_state->lane_count > 2) { in chv_phy_pre_pll_enable()
874 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in chv_phy_pre_encoder_enable()
875 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in chv_phy_pre_encoder_enable()
877 enum pipe pipe = crtc->pipe; in chv_phy_pre_encoder_enable()
888 if (crtc_state->lane_count > 2) { in chv_phy_pre_encoder_enable()
894 /* Program Tx lane latency optimal setting*/ in chv_phy_pre_encoder_enable()
895 for (i = 0; i < crtc_state->lane_count; i++) { in chv_phy_pre_encoder_enable()
897 if (crtc_state->lane_count == 1) in chv_phy_pre_encoder_enable()
905 /* Data lane stagger programming */ in chv_phy_pre_encoder_enable()
906 if (crtc_state->port_clock > 270000) in chv_phy_pre_encoder_enable()
908 else if (crtc_state->port_clock > 135000) in chv_phy_pre_encoder_enable()
910 else if (crtc_state->port_clock > 67500) in chv_phy_pre_encoder_enable()
912 else if (crtc_state->port_clock > 33750) in chv_phy_pre_encoder_enable()
921 if (crtc_state->lane_count > 2) { in chv_phy_pre_encoder_enable()
934 if (crtc_state->lane_count > 2) { in chv_phy_pre_encoder_enable()
943 /* Deassert data lane reset */ in chv_phy_pre_encoder_enable()
952 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in chv_phy_release_cl2_override()
954 if (dig_port->release_cl2_override) { in chv_phy_release_cl2_override()
956 dig_port->release_cl2_override = false; in chv_phy_release_cl2_override()
963 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in chv_phy_post_pll_disable()
964 enum pipe pipe = to_intel_crtc(old_crtc_state->uapi.crtc)->pipe; in chv_phy_post_pll_disable()
984 * lane so that chv_powergate_phy_ch() will power in chv_phy_post_pll_disable()
998 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_set_phy_signal_level()
999 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); in vlv_set_phy_signal_level()
1002 enum pipe pipe = intel_crtc->pipe; in vlv_set_phy_signal_level()
1026 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_phy_pre_pll_enable()
1027 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_phy_pre_pll_enable()
1029 enum pipe pipe = crtc->pipe; in vlv_phy_pre_pll_enable()
1031 /* Program Tx lane resets to default */ in vlv_phy_pre_pll_enable()
1043 /* Fix up inter-pair skew failure */ in vlv_phy_pre_pll_enable()
1056 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_phy_pre_encoder_enable()
1057 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_phy_pre_encoder_enable()
1059 enum pipe pipe = crtc->pipe; in vlv_phy_pre_encoder_enable()
1074 /* Program lane clock */ in vlv_phy_pre_encoder_enable()
1085 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_phy_reset_lanes()
1086 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); in vlv_phy_reset_lanes()
1088 enum pipe pipe = crtc->pipe; in vlv_phy_reset_lanes()