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/linux-5.10/Documentation/devicetree/bindings/net/
Dsmsc911x.txt1 * Smart Mixed-Signal Connectivity (SMSC) LAN911x/912x Controller
4 - compatible : Should be "smsc,lan<model>", "smsc,lan9115"
5 - reg : Address and length of the io space for SMSC LAN
6 - interrupts : one or two interrupt specifiers
7 - The first interrupt is the SMSC LAN interrupt line
8 - The second interrupt (if present) is the PME (power
11 - phy-mode : See ethernet.txt file in the same directory
14 - reg-shift : Specify the quantity to shift the register offsets by
15 - reg-io-width : Specify the size (in bytes) of the IO accesses that
18 - smsc,irq-active-high : Indicates the IRQ polarity is active-high
[all …]
/linux-5.10/Documentation/networking/device_drivers/ethernet/davicom/
Ddm9000.rst1 .. SPDX-License-Identifier: GPL-2.0
9 Ben Dooks <ben@simtec.co.uk> <ben-linux@fluff.org>
13 ------------
15 This file describes how to use the DM9000 platform-device based network driver
25 ----------------------------
37 An example from arch/arm/mach-s3c2410/mach-bast.c is::
91 -------------
94 device, whether or not an external PHY is attached to the device and
113 The chip is connected to an external PHY.
122 Switch to using the simpler PHY polling method which does not
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/linux-5.10/arch/arm/mach-omap2/
Domap_phy_internal.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * This file configures the internal USB PHY in OMAP4430. Used
6 * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com
28 * omap4430_phy_power_down: disable MUSB PHY during early init
30 * OMAP4 MUSB PHY module is enabled by default on reset, but this will
44 return -ENOMEM; in omap4430_phy_power_down()
47 /* Power down the phy */ in omap4430_phy_power_down()
79 * Start the on-chip PHY and its PLL. in am35x_musb_phy_power()
88 pr_info("Waiting for PHY clock good...\n"); in am35x_musb_phy_power()
94 pr_err("musb PHY clock good timed out\n"); in am35x_musb_phy_power()
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/linux-5.10/arch/mips/include/asm/mach-bcm63xx/
Dbcm63xx_dev_enet.h1 /* SPDX-License-Identifier: GPL-2.0 */
21 /* or fill phy info to use an external one */
26 /* if has_phy, use autonegotiated pause parameters or force
50 /* DMA engine has internal SRAM */
68 #define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */
69 #define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */
98 /* DMA engine has internal SRAM */
/linux-5.10/drivers/net/phy/
Dbcm7xxx.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Broadcom BCM7xxx internal transceivers support.
5 * Copyright (C) 2014-2017 Broadcom
9 #include <linux/phy.h>
11 #include "bcm-phy-lib.h"
17 /* Broadcom BCM7xxx internal PHY registers */
54 /* AFE_RXCONFIG_2, set rCal offset for HT=0 code and LT=-2 code */ in bcm7xxx_28nm_d0_afe_config_init()
69 /* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal in bcm7xxx_28nm_d0_afe_config_init()
74 /* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */ in bcm7xxx_28nm_d0_afe_config_init()
97 /* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal in bcm7xxx_28nm_e0_plus_afe_config_init()
[all …]
Dbroadcom.c1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/net/phy/broadcom.c
13 #include "bcm-phy-lib.h"
15 #include <linux/phy.h>
20 ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
23 ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
25 MODULE_DESCRIPTION("Broadcom PHY driver");
37 if (phydev->dev_flags & PHY_BRCM_EN_MASTER_MODE) { in bcm54210e_config_init()
53 if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) { in bcm54612e_config_init()
71 /* handling PHY's internal RX clock delay */ in bcm54xx_config_clock_delay()
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Dmicrel.c1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/net/phy/micrel.c
9 * Copyright (c) 2010-2013 Micrel, Inc.
25 #include <linux/phy.h>
52 /* PHY Control 1 */
55 /* PHY Control 2 / PHY Control (if no PHY Control 1) */
58 /* bitmap of PHY register to set interrupt mode */
160 const struct kszphy_type *type = phydev->drv->driver_data; in kszphy_config_intr()
164 if (type && type->interrupt_level_mask) in kszphy_config_intr()
165 mask = type->interrupt_level_mask; in kszphy_config_intr()
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Ddp83867.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Driver for the Texas Instruments DP83867 PHY
12 #include <linux/phy.h>
18 #include <dt-bindings/net/ti-dp83867.h>
98 /* PHY CTRL bits */
123 /* PHY STS bits */
183 struct net_device *ndev = phydev->attached_dev; in dp83867_set_wol()
190 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST | in dp83867_set_wol()
195 if (wol->wolopts & WAKE_MAGIC) { in dp83867_set_wol()
196 mac = (u8 *)ndev->dev_addr; in dp83867_set_wol()
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/linux-5.10/drivers/net/ethernet/intel/ixgbe/
Dixgbe_x550.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
17 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_get_invariants_X550_x()
18 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_get_invariants_X550_x() local
19 struct ixgbe_link_info *link = &hw->link; in ixgbe_get_invariants_X550_x()
24 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) in ixgbe_get_invariants_X550_x()
25 phy->ops.set_phy_power = NULL; in ixgbe_get_invariants_X550_x()
27 link->addr = IXGBE_CS4227; in ixgbe_get_invariants_X550_x()
34 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_get_invariants_X550_x_fw() local
39 phy->ops.set_phy_power = NULL; in ixgbe_get_invariants_X550_x_fw()
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/linux-5.10/drivers/phy/
Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
11 * The first PLL clock macro is used for internal reference clock. The second
12 * PLL clock macro is used to generate the clock for the PHY. This driver
13 * configures the first PLL CMU, the second PLL CMU, and programs the PHY to
15 * required if internal clock is enabled.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
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/linux-5.10/arch/arm/boot/dts/
Ds3c6410-smdk6410.dts1 // SPDX-License-Identifier: GPL-2.0
11 /dts-v1/;
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
31 fin_pll: oscillator-0 {
32 compatible = "fixed-clock";
33 clock-frequency = <12000000>;
34 clock-output-names = "fin_pll";
35 #clock-cells = <0>;
38 xusbxti: oscillator-1 {
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Dexynos5410-smdk5410.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/irq.h>
22 stdout-path = "serial2:115200n8";
26 compatible = "fixed-clock";
27 clock-frequency = <24000000>;
28 clock-output-names = "fin_pll";
29 #clock-cells = <0>;
32 pmic_ap_clk: pmic-ap-clk {
34 compatible = "fixed-clock";
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Dstm32mp157c-lxa-mc1.dts1 /* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */
3 * Copyright (C) 2020 STMicroelectronics - All Rights Reserved
7 /dts-v1/;
10 #include "stm32mp15xx-osd32.dtsi"
11 #include "stm32mp15xxac-pinctrl.dtsi"
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/pwm/pwm.h>
17 model = "Linux Automation MC-1 board";
18 compatible = "lxa,stm32mp157c-mc1", "st,stm32mp157";
28 compatible = "pwm-backlight";
[all …]
/linux-5.10/Documentation/networking/device_drivers/ethernet/stmicro/
Dstmmac.rst1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
33 (and older) and DesignWare(R) Cores Ethernet Quality-of-Service version 4.0
35 DesignWare(R) Cores XGMAC - 10G Ethernet MAC and DesignWare(R) Cores
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/linux-5.10/drivers/mmc/host/
Dsdhci-xenon.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Date: 2016-8-24
21 #include "sdhci-pltfm.h"
22 #include "sdhci-xenon.h"
41 dev_err(mmc_dev(host->mmc), "Internal clock never stabilised.\n"); in xenon_enable_internal_clk()
42 return -ETIMEDOUT; in xenon_enable_internal_clk()
50 /* Set SDCLK-off-while-idle */
91 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; in xenon_enable_sdhc()
93 * Force to clear BUS_TEST to in xenon_enable_sdhc()
96 host->mmc->caps &= ~MMC_CAP_BUS_WIDTH_TEST; in xenon_enable_sdhc()
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/linux-5.10/drivers/net/ethernet/marvell/
Dsky2.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 /* Yukon-2 */
32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
44 PCI_FORCE_PEX_L1 = 1<<5, /* Force to PEX L1 */
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/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dexynos-srom.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/exynos-srom.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
19 - const: samsung,exynos4210-srom
24 "#address-cells":
27 "#size-cells":
33 <bank-number> 0 <parent address of bank> <size>
37 "^.*@[0-3],[a-f0-9]+$":
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/linux-5.10/drivers/net/ethernet/intel/e1000e/
Dmac.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
7 * e1000e_get_bus_info_pcie - Get PCIe bus information
16 struct e1000_mac_info *mac = &hw->mac; in e1000e_get_bus_info_pcie()
17 struct e1000_bus_info *bus = &hw->bus; in e1000e_get_bus_info_pcie()
18 struct e1000_adapter *adapter = hw->adapter; in e1000e_get_bus_info_pcie()
21 cap_offset = adapter->pdev->pcie_cap; in e1000e_get_bus_info_pcie()
23 bus->width = e1000_bus_width_unknown; in e1000e_get_bus_info_pcie()
25 pci_read_config_word(adapter->pdev, in e1000e_get_bus_info_pcie()
28 bus->width = (enum e1000_bus_width)((pcie_link_status & in e1000e_get_bus_info_pcie()
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/linux-5.10/drivers/net/dsa/
Dbcm_sf2.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <linux/phy.h>
41 for (port = 0; port < ARRAY_SIZE(priv->port_sts); port++) { in bcm_sf2_num_active_ports()
44 if (priv->port_sts[port].enabled) in bcm_sf2_num_active_ports()
65 if (ports_active == 0 || !priv->clk_mdiv) in bcm_sf2_recalc_clock()
74 new_rate = rate_table[ports_active - 1]; in bcm_sf2_recalc_clock()
75 clk_set_rate(priv->clk_mdiv, new_rate); in bcm_sf2_recalc_clock()
108 if (priv->type == BCM7445_DEVICE_ID) in bcm_sf2_imp_setup()
113 /* Force link status for IMP port */ in bcm_sf2_imp_setup()
130 priv->port_sts[port].enabled = true; in bcm_sf2_imp_setup()
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/linux-5.10/Documentation/devicetree/bindings/mmc/
Darasan,sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Adrian Hunter <adrian.hunter@intel.com>
13 - $ref: "mmc-controller.yaml#"
14 - if:
18 const: arasan,sdhci-5.1
21 - phys
22 - phy-names
23 - if:
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/linux-5.10/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-sun8i.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer
11 #include <linux/mdio-mux.h>
17 #include <linux/phy.h>
26 /* General notes on dwmac-sun8i:
31 /* struct emac_variant - Describe dwmac-sun8i hardware variant
37 * @soc_has_internal_phy: Does the MAC embed an internal PHY
59 /* struct sunxi_priv_data - hold all sunxi private data
61 * @ephy_clk: reference to the optional EPHY clock for the internal PHY
63 * @rst_ephy: reference to the optional EPHY reset for the internal PHY
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/linux-5.10/Documentation/ABI/testing/
Dsysfs-class-uwb_rc4 Contact: linux-usb@vger.kernel.org
9 Familiarity with the ECMA-368 'High Rate Ultra
10 Wideband MAC and PHY Specification' is assumed.
24 Contact: linux-usb@vger.kernel.org
31 Contact: linux-usb@vger.kernel.org
37 to force a specific channel to be used when beaconing,
38 or, if <channel> is -1, to prohibit beaconing. If
43 Reading returns the currently active channel, or -1 if
49 Contact: linux-usb@vger.kernel.org
52 The application-specific information element (ASIE)
[all …]
/linux-5.10/drivers/net/ethernet/intel/e1000/
De1000_hw.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
88 * e1000_set_phy_type - Set the phy type member in the hw struct.
93 if (hw->mac_type == e1000_undefined) in e1000_set_phy_type()
94 return -E1000_ERR_PHY_TYPE; in e1000_set_phy_type()
96 switch (hw->phy_id) { in e1000_set_phy_type()
102 hw->phy_type = e1000_phy_m88; in e1000_set_phy_type()
105 if (hw->mac_type == e1000_82541 || in e1000_set_phy_type()
106 hw->mac_type == e1000_82541_rev_2 || in e1000_set_phy_type()
107 hw->mac_type == e1000_82547 || in e1000_set_phy_type()
[all …]
/linux-5.10/drivers/usb/dwc2/
Dcore.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * core.c - DesignWare HS OTG Controller common routines
5 * Copyright (C) 2004-2013 Synopsys, Inc.
16 * 3. The names of the above-listed copyright holders may not be used
48 #include <linux/dma-mapping.h>
61 * dwc2_backup_global_registers() - Backup global controller registers.
71 dev_dbg(hsotg->dev, "%s\n", __func__); in dwc2_backup_global_registers()
74 gr = &hsotg->gr_backup; in dwc2_backup_global_registers()
76 gr->gotgctl = dwc2_readl(hsotg, GOTGCTL); in dwc2_backup_global_registers()
77 gr->gintmsk = dwc2_readl(hsotg, GINTMSK); in dwc2_backup_global_registers()
[all …]
/linux-5.10/drivers/net/ethernet/intel/igc/
Digc_defines.h1 /* SPDX-License-Identifier: GPL-2.0 */
47 /* Loop limit on how long we wait for auto-negotiation to complete */
91 #define IGC_CTRL_PHY_RST 0x80000000 /* PHY Reset */
92 #define IGC_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
93 #define IGC_CTRL_FRCSPD 0x00000800 /* Force Speed */
94 #define IGC_CTRL_FRCDPX 0x00001000 /* Force Duplex */
125 /* 1000BASE-T Control Register */
130 /* 1000BASE-T Status Register */
134 /* PHY GPY 211 registers */
195 /* 1Gbps and 2.5Gbps half duplex is not supported, nor spec-compliant. */
[all …]

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