intel/igc/igc_defines.h

1 /* SPDX-License-Identifier: GPL-2.0 */
47 /* Loop limit on how long we wait for auto-negotiation to complete */
91 #define IGC_CTRL_PHY_RST	0x80000000  /* PHY Reset */
92 #define IGC_CTRL_SLU		0x00000040  /* Set link up (Force Link) */
93 #define IGC_CTRL_FRCSPD		0x00000800  /* Force Speed */
94 #define IGC_CTRL_FRCDPX		0x00001000  /* Force Duplex */
125 /* 1000BASE-T Control Register */
130 /* 1000BASE-T Status Register */
134 /* PHY GPY 211 registers */
195 /* 1Gbps and 2.5Gbps half duplex is not supported, nor spec-compliant. */
244 #define IGC_QVECTOR_MASK	0x7FFC		/* Q-vector mask */
286 #define IGC_TCTL_RTLC		0x01000000 /* Re-transmit on late collision */
298 #define IGC_MANC_BLK_PHY_RST_ON_IDE	0x00040000 /* Block phy resets */
356 #define IGC_DTXMXPKTSZ_DEFAULT	0x98 /* 9728-byte Jumbo frames */
382 #define IGC_TSYNCRXCTL_RXSYNSIG		0x00000400  /* Sample RX tstamp in PHY sop */
406 #define IGC_TSYNCTXCTL_TXSYNSIG			0x00000020  /* Sample TX tstamp in PHY sop */
420 /* GPY211 - I225 defines */
433 #define IGC_MANC_SMBUS_EN	0x00000001 /* SMBus Enabled - RO */
434 #define IGC_MANC_ASF_EN		0x00000002 /* ASF Enabled - RO */
436 /* PHY */
438 #define MAX_PHY_REG_ADDRESS	0x1F  /* 5 bit address bus (0-0x1F) */
441 /* PHY Control Register */
447 #define MII_CR_RESET		0x8000  /* 0 = normal, 1 = PHY reset */
452 /* PHY Status Register */
455 #define IGC_PHY_RST_COMP	0x0100 /* Internal PHY reset completion */
457 /* PHY 1000 MII Register/Bit Definitions */
458 /* PHY Registers defined by IEEE */
461 #define PHY_ID1			0x02 /* Phy Id Reg (word 1) */
462 #define PHY_ID2			0x03 /* Phy Id Reg (word 2) */
465 #define PHY_1000T_CTRL		0x09 /* 1000Base-T Control Reg */
466 #define PHY_1000T_STATUS	0x0A /* 1000Base-T Status Reg */
468 /* Bit definitions for valid PHY IDs. I = Integrated E = External */
483 #define IGC_N0_QUEUE		-1
514 /* Minimum time for 100BASE-T where no data will be transmit following move out