1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Broadcom Starfighter 2 DSA switch driver
4 *
5 * Copyright (C) 2014, Broadcom Corporation
6 */
7
8 #include <linux/list.h>
9 #include <linux/module.h>
10 #include <linux/netdevice.h>
11 #include <linux/interrupt.h>
12 #include <linux/platform_device.h>
13 #include <linux/phy.h>
14 #include <linux/phy_fixed.h>
15 #include <linux/phylink.h>
16 #include <linux/mii.h>
17 #include <linux/clk.h>
18 #include <linux/of.h>
19 #include <linux/of_irq.h>
20 #include <linux/of_address.h>
21 #include <linux/of_net.h>
22 #include <linux/of_mdio.h>
23 #include <net/dsa.h>
24 #include <linux/ethtool.h>
25 #include <linux/if_bridge.h>
26 #include <linux/brcmphy.h>
27 #include <linux/etherdevice.h>
28 #include <linux/platform_data/b53.h>
29
30 #include "bcm_sf2.h"
31 #include "bcm_sf2_regs.h"
32 #include "b53/b53_priv.h"
33 #include "b53/b53_regs.h"
34
35 /* Return the number of active ports, not counting the IMP (CPU) port */
bcm_sf2_num_active_ports(struct dsa_switch * ds)36 static unsigned int bcm_sf2_num_active_ports(struct dsa_switch *ds)
37 {
38 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
39 unsigned int port, count = 0;
40
41 for (port = 0; port < ARRAY_SIZE(priv->port_sts); port++) {
42 if (dsa_is_cpu_port(ds, port))
43 continue;
44 if (priv->port_sts[port].enabled)
45 count++;
46 }
47
48 return count;
49 }
50
bcm_sf2_recalc_clock(struct dsa_switch * ds)51 static void bcm_sf2_recalc_clock(struct dsa_switch *ds)
52 {
53 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
54 unsigned long new_rate;
55 unsigned int ports_active;
56 /* Frequenty in Mhz */
57 static const unsigned long rate_table[] = {
58 59220000,
59 60820000,
60 62500000,
61 62500000,
62 };
63
64 ports_active = bcm_sf2_num_active_ports(ds);
65 if (ports_active == 0 || !priv->clk_mdiv)
66 return;
67
68 /* If we overflow our table, just use the recommended operational
69 * frequency
70 */
71 if (ports_active > ARRAY_SIZE(rate_table))
72 new_rate = 90000000;
73 else
74 new_rate = rate_table[ports_active - 1];
75 clk_set_rate(priv->clk_mdiv, new_rate);
76 }
77
bcm_sf2_imp_setup(struct dsa_switch * ds,int port)78 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
79 {
80 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
81 unsigned int i;
82 u32 reg, offset;
83
84 /* Enable the port memories */
85 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
86 reg &= ~P_TXQ_PSM_VDD(port);
87 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
88
89 /* Enable forwarding */
90 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
91
92 /* Enable IMP port in dumb mode */
93 reg = core_readl(priv, CORE_SWITCH_CTRL);
94 reg |= MII_DUMB_FWDG_EN;
95 core_writel(priv, reg, CORE_SWITCH_CTRL);
96
97 /* Configure Traffic Class to QoS mapping, allow each priority to map
98 * to a different queue number
99 */
100 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
101 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
102 reg |= i << (PRT_TO_QID_SHIFT * i);
103 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
104
105 b53_brcm_hdr_setup(ds, port);
106
107 if (port == 8) {
108 if (priv->type == BCM7445_DEVICE_ID)
109 offset = CORE_STS_OVERRIDE_IMP;
110 else
111 offset = CORE_STS_OVERRIDE_IMP2;
112
113 /* Force link status for IMP port */
114 reg = core_readl(priv, offset);
115 reg |= (MII_SW_OR | LINK_STS);
116 reg &= ~GMII_SPEED_UP_2G;
117 core_writel(priv, reg, offset);
118
119 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
120 reg = core_readl(priv, CORE_IMP_CTL);
121 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
122 reg &= ~(RX_DIS | TX_DIS);
123 core_writel(priv, reg, CORE_IMP_CTL);
124 } else {
125 reg = core_readl(priv, CORE_G_PCTL_PORT(port));
126 reg &= ~(RX_DIS | TX_DIS);
127 core_writel(priv, reg, CORE_G_PCTL_PORT(port));
128 }
129
130 priv->port_sts[port].enabled = true;
131 }
132
bcm_sf2_gphy_enable_set(struct dsa_switch * ds,bool enable)133 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
134 {
135 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
136 u32 reg;
137
138 reg = reg_readl(priv, REG_SPHY_CNTRL);
139 if (enable) {
140 reg |= PHY_RESET;
141 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS);
142 reg_writel(priv, reg, REG_SPHY_CNTRL);
143 udelay(21);
144 reg = reg_readl(priv, REG_SPHY_CNTRL);
145 reg &= ~PHY_RESET;
146 } else {
147 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
148 reg_writel(priv, reg, REG_SPHY_CNTRL);
149 mdelay(1);
150 reg |= CK25_DIS;
151 }
152 reg_writel(priv, reg, REG_SPHY_CNTRL);
153
154 /* Use PHY-driven LED signaling */
155 if (!enable) {
156 reg = reg_readl(priv, REG_LED_CNTRL(0));
157 reg |= SPDLNK_SRC_SEL;
158 reg_writel(priv, reg, REG_LED_CNTRL(0));
159 }
160 }
161
bcm_sf2_port_intr_enable(struct bcm_sf2_priv * priv,int port)162 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
163 int port)
164 {
165 unsigned int off;
166
167 switch (port) {
168 case 7:
169 off = P7_IRQ_OFF;
170 break;
171 case 0:
172 /* Port 0 interrupts are located on the first bank */
173 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
174 return;
175 default:
176 off = P_IRQ_OFF(port);
177 break;
178 }
179
180 intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
181 }
182
bcm_sf2_port_intr_disable(struct bcm_sf2_priv * priv,int port)183 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
184 int port)
185 {
186 unsigned int off;
187
188 switch (port) {
189 case 7:
190 off = P7_IRQ_OFF;
191 break;
192 case 0:
193 /* Port 0 interrupts are located on the first bank */
194 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
195 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
196 return;
197 default:
198 off = P_IRQ_OFF(port);
199 break;
200 }
201
202 intrl2_1_mask_set(priv, P_IRQ_MASK(off));
203 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
204 }
205
bcm_sf2_port_setup(struct dsa_switch * ds,int port,struct phy_device * phy)206 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
207 struct phy_device *phy)
208 {
209 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
210 unsigned int i;
211 u32 reg;
212
213 if (!dsa_is_user_port(ds, port))
214 return 0;
215
216 priv->port_sts[port].enabled = true;
217
218 bcm_sf2_recalc_clock(ds);
219
220 /* Clear the memory power down */
221 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
222 reg &= ~P_TXQ_PSM_VDD(port);
223 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
224
225 /* Enable learning */
226 reg = core_readl(priv, CORE_DIS_LEARN);
227 reg &= ~BIT(port);
228 core_writel(priv, reg, CORE_DIS_LEARN);
229
230 /* Enable Broadcom tags for that port if requested */
231 if (priv->brcm_tag_mask & BIT(port)) {
232 b53_brcm_hdr_setup(ds, port);
233
234 /* Disable learning on ASP port */
235 if (port == 7) {
236 reg = core_readl(priv, CORE_DIS_LEARN);
237 reg |= BIT(port);
238 core_writel(priv, reg, CORE_DIS_LEARN);
239 }
240 }
241
242 /* Configure Traffic Class to QoS mapping, allow each priority to map
243 * to a different queue number
244 */
245 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
246 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
247 reg |= i << (PRT_TO_QID_SHIFT * i);
248 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
249
250 /* Re-enable the GPHY and re-apply workarounds */
251 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
252 bcm_sf2_gphy_enable_set(ds, true);
253 if (phy) {
254 /* if phy_stop() has been called before, phy
255 * will be in halted state, and phy_start()
256 * will call resume.
257 *
258 * the resume path does not configure back
259 * autoneg settings, and since we hard reset
260 * the phy manually here, we need to reset the
261 * state machine also.
262 */
263 phy->state = PHY_READY;
264 phy_init_hw(phy);
265 }
266 }
267
268 /* Enable MoCA port interrupts to get notified */
269 if (port == priv->moca_port)
270 bcm_sf2_port_intr_enable(priv, port);
271
272 /* Set per-queue pause threshold to 32 */
273 core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port));
274
275 /* Set ACB threshold to 24 */
276 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) {
277 reg = acb_readl(priv, ACB_QUEUE_CFG(port *
278 SF2_NUM_EGRESS_QUEUES + i));
279 reg &= ~XOFF_THRESHOLD_MASK;
280 reg |= 24;
281 acb_writel(priv, reg, ACB_QUEUE_CFG(port *
282 SF2_NUM_EGRESS_QUEUES + i));
283 }
284
285 return b53_enable_port(ds, port, phy);
286 }
287
bcm_sf2_port_disable(struct dsa_switch * ds,int port)288 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port)
289 {
290 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
291 u32 reg;
292
293 /* Disable learning while in WoL mode */
294 if (priv->wol_ports_mask & (1 << port)) {
295 reg = core_readl(priv, CORE_DIS_LEARN);
296 reg |= BIT(port);
297 core_writel(priv, reg, CORE_DIS_LEARN);
298 return;
299 }
300
301 if (port == priv->moca_port)
302 bcm_sf2_port_intr_disable(priv, port);
303
304 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
305 bcm_sf2_gphy_enable_set(ds, false);
306
307 b53_disable_port(ds, port);
308
309 /* Power down the port memory */
310 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
311 reg |= P_TXQ_PSM_VDD(port);
312 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
313
314 priv->port_sts[port].enabled = false;
315
316 bcm_sf2_recalc_clock(ds);
317 }
318
319
bcm_sf2_sw_indir_rw(struct bcm_sf2_priv * priv,int op,int addr,int regnum,u16 val)320 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr,
321 int regnum, u16 val)
322 {
323 int ret = 0;
324 u32 reg;
325
326 reg = reg_readl(priv, REG_SWITCH_CNTRL);
327 reg |= MDIO_MASTER_SEL;
328 reg_writel(priv, reg, REG_SWITCH_CNTRL);
329
330 /* Page << 8 | offset */
331 reg = 0x70;
332 reg <<= 2;
333 core_writel(priv, addr, reg);
334
335 /* Page << 8 | offset */
336 reg = 0x80 << 8 | regnum << 1;
337 reg <<= 2;
338
339 if (op)
340 ret = core_readl(priv, reg);
341 else
342 core_writel(priv, val, reg);
343
344 reg = reg_readl(priv, REG_SWITCH_CNTRL);
345 reg &= ~MDIO_MASTER_SEL;
346 reg_writel(priv, reg, REG_SWITCH_CNTRL);
347
348 return ret & 0xffff;
349 }
350
bcm_sf2_sw_mdio_read(struct mii_bus * bus,int addr,int regnum)351 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
352 {
353 struct bcm_sf2_priv *priv = bus->priv;
354
355 /* Intercept reads from Broadcom pseudo-PHY address, else, send
356 * them to our master MDIO bus controller
357 */
358 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
359 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0);
360 else
361 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum);
362 }
363
bcm_sf2_sw_mdio_write(struct mii_bus * bus,int addr,int regnum,u16 val)364 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
365 u16 val)
366 {
367 struct bcm_sf2_priv *priv = bus->priv;
368
369 /* Intercept writes to the Broadcom pseudo-PHY address, else,
370 * send them to our master MDIO bus controller
371 */
372 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
373 return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val);
374 else
375 return mdiobus_write_nested(priv->master_mii_bus, addr,
376 regnum, val);
377 }
378
bcm_sf2_switch_0_isr(int irq,void * dev_id)379 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
380 {
381 struct dsa_switch *ds = dev_id;
382 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
383
384 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
385 ~priv->irq0_mask;
386 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
387
388 return IRQ_HANDLED;
389 }
390
bcm_sf2_switch_1_isr(int irq,void * dev_id)391 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
392 {
393 struct dsa_switch *ds = dev_id;
394 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
395
396 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
397 ~priv->irq1_mask;
398 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
399
400 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) {
401 priv->port_sts[7].link = true;
402 dsa_port_phylink_mac_change(ds, 7, true);
403 }
404 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) {
405 priv->port_sts[7].link = false;
406 dsa_port_phylink_mac_change(ds, 7, false);
407 }
408
409 return IRQ_HANDLED;
410 }
411
bcm_sf2_sw_rst(struct bcm_sf2_priv * priv)412 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
413 {
414 unsigned int timeout = 1000;
415 u32 reg;
416 int ret;
417
418 /* The watchdog reset does not work on 7278, we need to hit the
419 * "external" reset line through the reset controller.
420 */
421 if (priv->type == BCM7278_DEVICE_ID && !IS_ERR(priv->rcdev)) {
422 ret = reset_control_assert(priv->rcdev);
423 if (ret)
424 return ret;
425
426 return reset_control_deassert(priv->rcdev);
427 }
428
429 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
430 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
431 core_writel(priv, reg, CORE_WATCHDOG_CTRL);
432
433 do {
434 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
435 if (!(reg & SOFTWARE_RESET))
436 break;
437
438 usleep_range(1000, 2000);
439 } while (timeout-- > 0);
440
441 if (timeout == 0)
442 return -ETIMEDOUT;
443
444 return 0;
445 }
446
bcm_sf2_intr_disable(struct bcm_sf2_priv * priv)447 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
448 {
449 intrl2_0_mask_set(priv, 0xffffffff);
450 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
451 intrl2_1_mask_set(priv, 0xffffffff);
452 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
453 }
454
bcm_sf2_identify_ports(struct bcm_sf2_priv * priv,struct device_node * dn)455 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
456 struct device_node *dn)
457 {
458 struct device_node *port;
459 unsigned int port_num;
460 struct property *prop;
461 phy_interface_t mode;
462 int err;
463
464 priv->moca_port = -1;
465
466 for_each_available_child_of_node(dn, port) {
467 if (of_property_read_u32(port, "reg", &port_num))
468 continue;
469
470 /* Internal PHYs get assigned a specific 'phy-mode' property
471 * value: "internal" to help flag them before MDIO probing
472 * has completed, since they might be turned off at that
473 * time
474 */
475 err = of_get_phy_mode(port, &mode);
476 if (err)
477 continue;
478
479 if (mode == PHY_INTERFACE_MODE_INTERNAL)
480 priv->int_phy_mask |= 1 << port_num;
481
482 if (mode == PHY_INTERFACE_MODE_MOCA)
483 priv->moca_port = port_num;
484
485 if (of_property_read_bool(port, "brcm,use-bcm-hdr"))
486 priv->brcm_tag_mask |= 1 << port_num;
487
488 /* Ensure that port 5 is not picked up as a DSA CPU port
489 * flavour but a regular port instead. We should be using
490 * devlink to be able to set the port flavour.
491 */
492 if (port_num == 5 && priv->type == BCM7278_DEVICE_ID) {
493 prop = of_find_property(port, "ethernet", NULL);
494 if (prop)
495 of_remove_property(port, prop);
496 }
497 }
498 }
499
bcm_sf2_mdio_register(struct dsa_switch * ds)500 static int bcm_sf2_mdio_register(struct dsa_switch *ds)
501 {
502 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
503 struct device_node *dn, *child;
504 struct phy_device *phydev;
505 struct property *prop;
506 static int index;
507 int err, reg;
508
509 /* Find our integrated MDIO bus node */
510 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
511 priv->master_mii_bus = of_mdio_find_bus(dn);
512 if (!priv->master_mii_bus)
513 return -EPROBE_DEFER;
514
515 get_device(&priv->master_mii_bus->dev);
516 priv->master_mii_dn = dn;
517
518 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev);
519 if (!priv->slave_mii_bus)
520 return -ENOMEM;
521
522 priv->slave_mii_bus->priv = priv;
523 priv->slave_mii_bus->name = "sf2 slave mii";
524 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read;
525 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write;
526 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d",
527 index++);
528 priv->slave_mii_bus->dev.of_node = dn;
529
530 /* Include the pseudo-PHY address to divert reads towards our
531 * workaround. This is only required for 7445D0, since 7445E0
532 * disconnects the internal switch pseudo-PHY such that we can use the
533 * regular SWITCH_MDIO master controller instead.
534 *
535 * Here we flag the pseudo PHY as needing special treatment and would
536 * otherwise make all other PHY read/writes go to the master MDIO bus
537 * controller that comes with this switch backed by the "mdio-unimac"
538 * driver.
539 */
540 if (of_machine_is_compatible("brcm,bcm7445d0"))
541 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR) | (1 << 0);
542 else
543 priv->indir_phy_mask = 0;
544
545 ds->phys_mii_mask = priv->indir_phy_mask;
546 ds->slave_mii_bus = priv->slave_mii_bus;
547 priv->slave_mii_bus->parent = ds->dev->parent;
548 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask;
549
550 /* We need to make sure that of_phy_connect() will not work by
551 * removing the 'phandle' and 'linux,phandle' properties and
552 * unregister the existing PHY device that was already registered.
553 */
554 for_each_available_child_of_node(dn, child) {
555 if (of_property_read_u32(child, "reg", ®) ||
556 reg >= PHY_MAX_ADDR)
557 continue;
558
559 if (!(priv->indir_phy_mask & BIT(reg)))
560 continue;
561
562 prop = of_find_property(child, "phandle", NULL);
563 if (prop)
564 of_remove_property(child, prop);
565
566 prop = of_find_property(child, "linux,phandle", NULL);
567 if (prop)
568 of_remove_property(child, prop);
569
570 phydev = of_phy_find_device(child);
571 if (phydev)
572 phy_device_remove(phydev);
573 }
574
575 err = mdiobus_register(priv->slave_mii_bus);
576 if (err && dn)
577 of_node_put(dn);
578
579 return err;
580 }
581
bcm_sf2_mdio_unregister(struct bcm_sf2_priv * priv)582 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv)
583 {
584 mdiobus_unregister(priv->slave_mii_bus);
585 of_node_put(priv->master_mii_dn);
586 }
587
bcm_sf2_sw_get_phy_flags(struct dsa_switch * ds,int port)588 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
589 {
590 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
591
592 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
593 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
594 * the REG_PHY_REVISION register layout is.
595 */
596
597 return priv->hw_params.gphy_rev;
598 }
599
bcm_sf2_sw_validate(struct dsa_switch * ds,int port,unsigned long * supported,struct phylink_link_state * state)600 static void bcm_sf2_sw_validate(struct dsa_switch *ds, int port,
601 unsigned long *supported,
602 struct phylink_link_state *state)
603 {
604 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
605 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
606
607 if (!phy_interface_mode_is_rgmii(state->interface) &&
608 state->interface != PHY_INTERFACE_MODE_MII &&
609 state->interface != PHY_INTERFACE_MODE_REVMII &&
610 state->interface != PHY_INTERFACE_MODE_GMII &&
611 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
612 state->interface != PHY_INTERFACE_MODE_MOCA) {
613 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
614 if (port != core_readl(priv, CORE_IMP0_PRT_ID))
615 dev_err(ds->dev,
616 "Unsupported interface: %d for port %d\n",
617 state->interface, port);
618 return;
619 }
620
621 /* Allow all the expected bits */
622 phylink_set(mask, Autoneg);
623 phylink_set_port_modes(mask);
624 phylink_set(mask, Pause);
625 phylink_set(mask, Asym_Pause);
626
627 /* With the exclusion of MII and Reverse MII, we support Gigabit,
628 * including Half duplex
629 */
630 if (state->interface != PHY_INTERFACE_MODE_MII &&
631 state->interface != PHY_INTERFACE_MODE_REVMII) {
632 phylink_set(mask, 1000baseT_Full);
633 phylink_set(mask, 1000baseT_Half);
634 }
635
636 phylink_set(mask, 10baseT_Half);
637 phylink_set(mask, 10baseT_Full);
638 phylink_set(mask, 100baseT_Half);
639 phylink_set(mask, 100baseT_Full);
640
641 bitmap_and(supported, supported, mask,
642 __ETHTOOL_LINK_MODE_MASK_NBITS);
643 bitmap_and(state->advertising, state->advertising, mask,
644 __ETHTOOL_LINK_MODE_MASK_NBITS);
645 }
646
bcm_sf2_sw_mac_config(struct dsa_switch * ds,int port,unsigned int mode,const struct phylink_link_state * state)647 static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port,
648 unsigned int mode,
649 const struct phylink_link_state *state)
650 {
651 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
652 u32 id_mode_dis = 0, port_mode;
653 u32 reg;
654
655 if (port == core_readl(priv, CORE_IMP0_PRT_ID))
656 return;
657
658 switch (state->interface) {
659 case PHY_INTERFACE_MODE_RGMII:
660 id_mode_dis = 1;
661 fallthrough;
662 case PHY_INTERFACE_MODE_RGMII_TXID:
663 port_mode = EXT_GPHY;
664 break;
665 case PHY_INTERFACE_MODE_MII:
666 port_mode = EXT_EPHY;
667 break;
668 case PHY_INTERFACE_MODE_REVMII:
669 port_mode = EXT_REVMII;
670 break;
671 default:
672 /* Nothing required for all other PHYs: internal and MoCA */
673 return;
674 }
675
676 /* Clear id_mode_dis bit, and the existing port mode, let
677 * RGMII_MODE_EN bet set by mac_link_{up,down}
678 */
679 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
680 reg &= ~ID_MODE_DIS;
681 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
682
683 reg |= port_mode;
684 if (id_mode_dis)
685 reg |= ID_MODE_DIS;
686
687 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
688 }
689
bcm_sf2_sw_mac_link_set(struct dsa_switch * ds,int port,phy_interface_t interface,bool link)690 static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port,
691 phy_interface_t interface, bool link)
692 {
693 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
694 u32 reg;
695
696 if (!phy_interface_mode_is_rgmii(interface) &&
697 interface != PHY_INTERFACE_MODE_MII &&
698 interface != PHY_INTERFACE_MODE_REVMII)
699 return;
700
701 /* If the link is down, just disable the interface to conserve power */
702 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
703 if (link)
704 reg |= RGMII_MODE_EN;
705 else
706 reg &= ~RGMII_MODE_EN;
707 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
708 }
709
bcm_sf2_sw_mac_link_down(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)710 static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port,
711 unsigned int mode,
712 phy_interface_t interface)
713 {
714 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
715 u32 reg, offset;
716
717 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) {
718 if (priv->type == BCM7445_DEVICE_ID)
719 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
720 else
721 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
722
723 reg = core_readl(priv, offset);
724 reg &= ~LINK_STS;
725 core_writel(priv, reg, offset);
726 }
727
728 bcm_sf2_sw_mac_link_set(ds, port, interface, false);
729 }
730
bcm_sf2_sw_mac_link_up(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface,struct phy_device * phydev,int speed,int duplex,bool tx_pause,bool rx_pause)731 static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port,
732 unsigned int mode,
733 phy_interface_t interface,
734 struct phy_device *phydev,
735 int speed, int duplex,
736 bool tx_pause, bool rx_pause)
737 {
738 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
739 struct ethtool_eee *p = &priv->dev->ports[port].eee;
740 u32 reg, offset;
741
742 bcm_sf2_sw_mac_link_set(ds, port, interface, true);
743
744 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) {
745 if (priv->type == BCM7445_DEVICE_ID)
746 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
747 else
748 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
749
750 if (interface == PHY_INTERFACE_MODE_RGMII ||
751 interface == PHY_INTERFACE_MODE_RGMII_TXID ||
752 interface == PHY_INTERFACE_MODE_MII ||
753 interface == PHY_INTERFACE_MODE_REVMII) {
754 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
755 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
756
757 if (tx_pause)
758 reg |= TX_PAUSE_EN;
759 if (rx_pause)
760 reg |= RX_PAUSE_EN;
761
762 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
763 }
764
765 reg = SW_OVERRIDE | LINK_STS;
766 switch (speed) {
767 case SPEED_1000:
768 reg |= SPDSTS_1000 << SPEED_SHIFT;
769 break;
770 case SPEED_100:
771 reg |= SPDSTS_100 << SPEED_SHIFT;
772 break;
773 }
774
775 if (duplex == DUPLEX_FULL)
776 reg |= DUPLX_MODE;
777
778 core_writel(priv, reg, offset);
779 }
780
781 if (mode == MLO_AN_PHY && phydev)
782 p->eee_enabled = b53_eee_init(ds, port, phydev);
783 }
784
bcm_sf2_sw_fixed_state(struct dsa_switch * ds,int port,struct phylink_link_state * status)785 static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port,
786 struct phylink_link_state *status)
787 {
788 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
789
790 status->link = false;
791
792 /* MoCA port is special as we do not get link status from CORE_LNKSTS,
793 * which means that we need to force the link at the port override
794 * level to get the data to flow. We do use what the interrupt handler
795 * did determine before.
796 *
797 * For the other ports, we just force the link status, since this is
798 * a fixed PHY device.
799 */
800 if (port == priv->moca_port) {
801 status->link = priv->port_sts[port].link;
802 /* For MoCA interfaces, also force a link down notification
803 * since some version of the user-space daemon (mocad) use
804 * cmd->autoneg to force the link, which messes up the PHY
805 * state machine and make it go in PHY_FORCING state instead.
806 */
807 if (!status->link)
808 netif_carrier_off(dsa_to_port(ds, port)->slave);
809 status->duplex = DUPLEX_FULL;
810 } else {
811 status->link = true;
812 }
813 }
814
bcm_sf2_enable_acb(struct dsa_switch * ds)815 static void bcm_sf2_enable_acb(struct dsa_switch *ds)
816 {
817 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
818 u32 reg;
819
820 /* Enable ACB globally */
821 reg = acb_readl(priv, ACB_CONTROL);
822 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
823 acb_writel(priv, reg, ACB_CONTROL);
824 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
825 reg |= ACB_EN | ACB_ALGORITHM;
826 acb_writel(priv, reg, ACB_CONTROL);
827 }
828
bcm_sf2_sw_suspend(struct dsa_switch * ds)829 static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
830 {
831 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
832 unsigned int port;
833
834 bcm_sf2_intr_disable(priv);
835
836 /* Disable all ports physically present including the IMP
837 * port, the other ones have already been disabled during
838 * bcm_sf2_sw_setup
839 */
840 for (port = 0; port < ds->num_ports; port++) {
841 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port))
842 bcm_sf2_port_disable(ds, port);
843 }
844
845 if (!priv->wol_ports_mask)
846 clk_disable_unprepare(priv->clk);
847
848 return 0;
849 }
850
bcm_sf2_sw_resume(struct dsa_switch * ds)851 static int bcm_sf2_sw_resume(struct dsa_switch *ds)
852 {
853 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
854 int ret;
855
856 if (!priv->wol_ports_mask)
857 clk_prepare_enable(priv->clk);
858
859 ret = bcm_sf2_sw_rst(priv);
860 if (ret) {
861 pr_err("%s: failed to software reset switch\n", __func__);
862 return ret;
863 }
864
865 ret = bcm_sf2_cfp_resume(ds);
866 if (ret)
867 return ret;
868
869 if (priv->hw_params.num_gphy == 1)
870 bcm_sf2_gphy_enable_set(ds, true);
871
872 ds->ops->setup(ds);
873
874 return 0;
875 }
876
bcm_sf2_sw_get_wol(struct dsa_switch * ds,int port,struct ethtool_wolinfo * wol)877 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
878 struct ethtool_wolinfo *wol)
879 {
880 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master;
881 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
882 struct ethtool_wolinfo pwol = { };
883
884 /* Get the parent device WoL settings */
885 if (p->ethtool_ops->get_wol)
886 p->ethtool_ops->get_wol(p, &pwol);
887
888 /* Advertise the parent device supported settings */
889 wol->supported = pwol.supported;
890 memset(&wol->sopass, 0, sizeof(wol->sopass));
891
892 if (pwol.wolopts & WAKE_MAGICSECURE)
893 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
894
895 if (priv->wol_ports_mask & (1 << port))
896 wol->wolopts = pwol.wolopts;
897 else
898 wol->wolopts = 0;
899 }
900
bcm_sf2_sw_set_wol(struct dsa_switch * ds,int port,struct ethtool_wolinfo * wol)901 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
902 struct ethtool_wolinfo *wol)
903 {
904 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master;
905 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
906 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
907 struct ethtool_wolinfo pwol = { };
908
909 if (p->ethtool_ops->get_wol)
910 p->ethtool_ops->get_wol(p, &pwol);
911 if (wol->wolopts & ~pwol.supported)
912 return -EINVAL;
913
914 if (wol->wolopts)
915 priv->wol_ports_mask |= (1 << port);
916 else
917 priv->wol_ports_mask &= ~(1 << port);
918
919 /* If we have at least one port enabled, make sure the CPU port
920 * is also enabled. If the CPU port is the last one enabled, we disable
921 * it since this configuration does not make sense.
922 */
923 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
924 priv->wol_ports_mask |= (1 << cpu_port);
925 else
926 priv->wol_ports_mask &= ~(1 << cpu_port);
927
928 return p->ethtool_ops->set_wol(p, wol);
929 }
930
bcm_sf2_sw_setup(struct dsa_switch * ds)931 static int bcm_sf2_sw_setup(struct dsa_switch *ds)
932 {
933 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
934 unsigned int port;
935
936 /* Enable all valid ports and disable those unused */
937 for (port = 0; port < priv->hw_params.num_ports; port++) {
938 /* IMP port receives special treatment */
939 if (dsa_is_user_port(ds, port))
940 bcm_sf2_port_setup(ds, port, NULL);
941 else if (dsa_is_cpu_port(ds, port))
942 bcm_sf2_imp_setup(ds, port);
943 else
944 bcm_sf2_port_disable(ds, port);
945 }
946
947 b53_configure_vlan(ds);
948 bcm_sf2_enable_acb(ds);
949
950 return b53_setup_devlink_resources(ds);
951 }
952
bcm_sf2_sw_teardown(struct dsa_switch * ds)953 static void bcm_sf2_sw_teardown(struct dsa_switch *ds)
954 {
955 dsa_devlink_resources_unregister(ds);
956 }
957
958 /* The SWITCH_CORE register space is managed by b53 but operates on a page +
959 * register basis so we need to translate that into an address that the
960 * bus-glue understands.
961 */
962 #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2)
963
bcm_sf2_core_read8(struct b53_device * dev,u8 page,u8 reg,u8 * val)964 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg,
965 u8 *val)
966 {
967 struct bcm_sf2_priv *priv = dev->priv;
968
969 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
970
971 return 0;
972 }
973
bcm_sf2_core_read16(struct b53_device * dev,u8 page,u8 reg,u16 * val)974 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg,
975 u16 *val)
976 {
977 struct bcm_sf2_priv *priv = dev->priv;
978
979 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
980
981 return 0;
982 }
983
bcm_sf2_core_read32(struct b53_device * dev,u8 page,u8 reg,u32 * val)984 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg,
985 u32 *val)
986 {
987 struct bcm_sf2_priv *priv = dev->priv;
988
989 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
990
991 return 0;
992 }
993
bcm_sf2_core_read64(struct b53_device * dev,u8 page,u8 reg,u64 * val)994 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg,
995 u64 *val)
996 {
997 struct bcm_sf2_priv *priv = dev->priv;
998
999 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg));
1000
1001 return 0;
1002 }
1003
bcm_sf2_core_write8(struct b53_device * dev,u8 page,u8 reg,u8 value)1004 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg,
1005 u8 value)
1006 {
1007 struct bcm_sf2_priv *priv = dev->priv;
1008
1009 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1010
1011 return 0;
1012 }
1013
bcm_sf2_core_write16(struct b53_device * dev,u8 page,u8 reg,u16 value)1014 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg,
1015 u16 value)
1016 {
1017 struct bcm_sf2_priv *priv = dev->priv;
1018
1019 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1020
1021 return 0;
1022 }
1023
bcm_sf2_core_write32(struct b53_device * dev,u8 page,u8 reg,u32 value)1024 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg,
1025 u32 value)
1026 {
1027 struct bcm_sf2_priv *priv = dev->priv;
1028
1029 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1030
1031 return 0;
1032 }
1033
bcm_sf2_core_write64(struct b53_device * dev,u8 page,u8 reg,u64 value)1034 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg,
1035 u64 value)
1036 {
1037 struct bcm_sf2_priv *priv = dev->priv;
1038
1039 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1040
1041 return 0;
1042 }
1043
1044 static const struct b53_io_ops bcm_sf2_io_ops = {
1045 .read8 = bcm_sf2_core_read8,
1046 .read16 = bcm_sf2_core_read16,
1047 .read32 = bcm_sf2_core_read32,
1048 .read48 = bcm_sf2_core_read64,
1049 .read64 = bcm_sf2_core_read64,
1050 .write8 = bcm_sf2_core_write8,
1051 .write16 = bcm_sf2_core_write16,
1052 .write32 = bcm_sf2_core_write32,
1053 .write48 = bcm_sf2_core_write64,
1054 .write64 = bcm_sf2_core_write64,
1055 };
1056
bcm_sf2_sw_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * data)1057 static void bcm_sf2_sw_get_strings(struct dsa_switch *ds, int port,
1058 u32 stringset, uint8_t *data)
1059 {
1060 int cnt = b53_get_sset_count(ds, port, stringset);
1061
1062 b53_get_strings(ds, port, stringset, data);
1063 bcm_sf2_cfp_get_strings(ds, port, stringset,
1064 data + cnt * ETH_GSTRING_LEN);
1065 }
1066
bcm_sf2_sw_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * data)1067 static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds, int port,
1068 uint64_t *data)
1069 {
1070 int cnt = b53_get_sset_count(ds, port, ETH_SS_STATS);
1071
1072 b53_get_ethtool_stats(ds, port, data);
1073 bcm_sf2_cfp_get_ethtool_stats(ds, port, data + cnt);
1074 }
1075
bcm_sf2_sw_get_sset_count(struct dsa_switch * ds,int port,int sset)1076 static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds, int port,
1077 int sset)
1078 {
1079 int cnt = b53_get_sset_count(ds, port, sset);
1080
1081 if (cnt < 0)
1082 return cnt;
1083
1084 cnt += bcm_sf2_cfp_get_sset_count(ds, port, sset);
1085
1086 return cnt;
1087 }
1088
1089 static const struct dsa_switch_ops bcm_sf2_ops = {
1090 .get_tag_protocol = b53_get_tag_protocol,
1091 .setup = bcm_sf2_sw_setup,
1092 .teardown = bcm_sf2_sw_teardown,
1093 .get_strings = bcm_sf2_sw_get_strings,
1094 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats,
1095 .get_sset_count = bcm_sf2_sw_get_sset_count,
1096 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats,
1097 .get_phy_flags = bcm_sf2_sw_get_phy_flags,
1098 .phylink_validate = bcm_sf2_sw_validate,
1099 .phylink_mac_config = bcm_sf2_sw_mac_config,
1100 .phylink_mac_link_down = bcm_sf2_sw_mac_link_down,
1101 .phylink_mac_link_up = bcm_sf2_sw_mac_link_up,
1102 .phylink_fixed_state = bcm_sf2_sw_fixed_state,
1103 .suspend = bcm_sf2_sw_suspend,
1104 .resume = bcm_sf2_sw_resume,
1105 .get_wol = bcm_sf2_sw_get_wol,
1106 .set_wol = bcm_sf2_sw_set_wol,
1107 .port_enable = bcm_sf2_port_setup,
1108 .port_disable = bcm_sf2_port_disable,
1109 .get_mac_eee = b53_get_mac_eee,
1110 .set_mac_eee = b53_set_mac_eee,
1111 .port_bridge_join = b53_br_join,
1112 .port_bridge_leave = b53_br_leave,
1113 .port_stp_state_set = b53_br_set_stp_state,
1114 .port_fast_age = b53_br_fast_age,
1115 .port_vlan_filtering = b53_vlan_filtering,
1116 .port_vlan_prepare = b53_vlan_prepare,
1117 .port_vlan_add = b53_vlan_add,
1118 .port_vlan_del = b53_vlan_del,
1119 .port_fdb_dump = b53_fdb_dump,
1120 .port_fdb_add = b53_fdb_add,
1121 .port_fdb_del = b53_fdb_del,
1122 .get_rxnfc = bcm_sf2_get_rxnfc,
1123 .set_rxnfc = bcm_sf2_set_rxnfc,
1124 .port_mirror_add = b53_mirror_add,
1125 .port_mirror_del = b53_mirror_del,
1126 .port_mdb_prepare = b53_mdb_prepare,
1127 .port_mdb_add = b53_mdb_add,
1128 .port_mdb_del = b53_mdb_del,
1129 };
1130
1131 struct bcm_sf2_of_data {
1132 u32 type;
1133 const u16 *reg_offsets;
1134 unsigned int core_reg_align;
1135 unsigned int num_cfp_rules;
1136 };
1137
1138 /* Register offsets for the SWITCH_REG_* block */
1139 static const u16 bcm_sf2_7445_reg_offsets[] = {
1140 [REG_SWITCH_CNTRL] = 0x00,
1141 [REG_SWITCH_STATUS] = 0x04,
1142 [REG_DIR_DATA_WRITE] = 0x08,
1143 [REG_DIR_DATA_READ] = 0x0C,
1144 [REG_SWITCH_REVISION] = 0x18,
1145 [REG_PHY_REVISION] = 0x1C,
1146 [REG_SPHY_CNTRL] = 0x2C,
1147 [REG_RGMII_0_CNTRL] = 0x34,
1148 [REG_RGMII_1_CNTRL] = 0x40,
1149 [REG_RGMII_2_CNTRL] = 0x4c,
1150 [REG_LED_0_CNTRL] = 0x90,
1151 [REG_LED_1_CNTRL] = 0x94,
1152 [REG_LED_2_CNTRL] = 0x98,
1153 };
1154
1155 static const struct bcm_sf2_of_data bcm_sf2_7445_data = {
1156 .type = BCM7445_DEVICE_ID,
1157 .core_reg_align = 0,
1158 .reg_offsets = bcm_sf2_7445_reg_offsets,
1159 .num_cfp_rules = 256,
1160 };
1161
1162 static const u16 bcm_sf2_7278_reg_offsets[] = {
1163 [REG_SWITCH_CNTRL] = 0x00,
1164 [REG_SWITCH_STATUS] = 0x04,
1165 [REG_DIR_DATA_WRITE] = 0x08,
1166 [REG_DIR_DATA_READ] = 0x0c,
1167 [REG_SWITCH_REVISION] = 0x10,
1168 [REG_PHY_REVISION] = 0x14,
1169 [REG_SPHY_CNTRL] = 0x24,
1170 [REG_RGMII_0_CNTRL] = 0xe0,
1171 [REG_RGMII_1_CNTRL] = 0xec,
1172 [REG_RGMII_2_CNTRL] = 0xf8,
1173 [REG_LED_0_CNTRL] = 0x40,
1174 [REG_LED_1_CNTRL] = 0x4c,
1175 [REG_LED_2_CNTRL] = 0x58,
1176 };
1177
1178 static const struct bcm_sf2_of_data bcm_sf2_7278_data = {
1179 .type = BCM7278_DEVICE_ID,
1180 .core_reg_align = 1,
1181 .reg_offsets = bcm_sf2_7278_reg_offsets,
1182 .num_cfp_rules = 128,
1183 };
1184
1185 static const struct of_device_id bcm_sf2_of_match[] = {
1186 { .compatible = "brcm,bcm7445-switch-v4.0",
1187 .data = &bcm_sf2_7445_data
1188 },
1189 { .compatible = "brcm,bcm7278-switch-v4.0",
1190 .data = &bcm_sf2_7278_data
1191 },
1192 { .compatible = "brcm,bcm7278-switch-v4.8",
1193 .data = &bcm_sf2_7278_data
1194 },
1195 { /* sentinel */ },
1196 };
1197 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);
1198
bcm_sf2_sw_probe(struct platform_device * pdev)1199 static int bcm_sf2_sw_probe(struct platform_device *pdev)
1200 {
1201 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
1202 struct device_node *dn = pdev->dev.of_node;
1203 const struct of_device_id *of_id = NULL;
1204 const struct bcm_sf2_of_data *data;
1205 struct b53_platform_data *pdata;
1206 struct dsa_switch_ops *ops;
1207 struct device_node *ports;
1208 struct bcm_sf2_priv *priv;
1209 struct b53_device *dev;
1210 struct dsa_switch *ds;
1211 void __iomem **base;
1212 unsigned int i;
1213 u32 reg, rev;
1214 int ret;
1215
1216 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1217 if (!priv)
1218 return -ENOMEM;
1219
1220 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL);
1221 if (!ops)
1222 return -ENOMEM;
1223
1224 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv);
1225 if (!dev)
1226 return -ENOMEM;
1227
1228 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1229 if (!pdata)
1230 return -ENOMEM;
1231
1232 of_id = of_match_node(bcm_sf2_of_match, dn);
1233 if (!of_id || !of_id->data)
1234 return -EINVAL;
1235
1236 data = of_id->data;
1237
1238 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */
1239 priv->type = data->type;
1240 priv->reg_offsets = data->reg_offsets;
1241 priv->core_reg_align = data->core_reg_align;
1242 priv->num_cfp_rules = data->num_cfp_rules;
1243
1244 priv->rcdev = devm_reset_control_get_optional_exclusive(&pdev->dev,
1245 "switch");
1246 if (PTR_ERR(priv->rcdev) == -EPROBE_DEFER)
1247 return PTR_ERR(priv->rcdev);
1248
1249 /* Auto-detection using standard registers will not work, so
1250 * provide an indication of what kind of device we are for
1251 * b53_common to work with
1252 */
1253 pdata->chip_id = priv->type;
1254 dev->pdata = pdata;
1255
1256 priv->dev = dev;
1257 ds = dev->ds;
1258 ds->ops = &bcm_sf2_ops;
1259
1260 /* Advertise the 8 egress queues */
1261 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES;
1262
1263 dev_set_drvdata(&pdev->dev, priv);
1264
1265 spin_lock_init(&priv->indir_lock);
1266 mutex_init(&priv->cfp.lock);
1267 INIT_LIST_HEAD(&priv->cfp.rules_list);
1268
1269 /* CFP rule #0 cannot be used for specific classifications, flag it as
1270 * permanently used
1271 */
1272 set_bit(0, priv->cfp.used);
1273 set_bit(0, priv->cfp.unique);
1274
1275 /* Balance of_node_put() done by of_find_node_by_name() */
1276 of_node_get(dn);
1277 ports = of_find_node_by_name(dn, "ports");
1278 if (ports) {
1279 bcm_sf2_identify_ports(priv, ports);
1280 of_node_put(ports);
1281 }
1282
1283 priv->irq0 = irq_of_parse_and_map(dn, 0);
1284 priv->irq1 = irq_of_parse_and_map(dn, 1);
1285
1286 base = &priv->core;
1287 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
1288 *base = devm_platform_ioremap_resource(pdev, i);
1289 if (IS_ERR(*base)) {
1290 pr_err("unable to find register: %s\n", reg_names[i]);
1291 return PTR_ERR(*base);
1292 }
1293 base++;
1294 }
1295
1296 priv->clk = devm_clk_get_optional(&pdev->dev, "sw_switch");
1297 if (IS_ERR(priv->clk))
1298 return PTR_ERR(priv->clk);
1299
1300 clk_prepare_enable(priv->clk);
1301
1302 priv->clk_mdiv = devm_clk_get_optional(&pdev->dev, "sw_switch_mdiv");
1303 if (IS_ERR(priv->clk_mdiv)) {
1304 ret = PTR_ERR(priv->clk_mdiv);
1305 goto out_clk;
1306 }
1307
1308 clk_prepare_enable(priv->clk_mdiv);
1309
1310 ret = bcm_sf2_sw_rst(priv);
1311 if (ret) {
1312 pr_err("unable to software reset switch: %d\n", ret);
1313 goto out_clk_mdiv;
1314 }
1315
1316 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1317
1318 ret = bcm_sf2_mdio_register(ds);
1319 if (ret) {
1320 pr_err("failed to register MDIO bus\n");
1321 goto out_clk_mdiv;
1322 }
1323
1324 bcm_sf2_gphy_enable_set(priv->dev->ds, false);
1325
1326 ret = bcm_sf2_cfp_rst(priv);
1327 if (ret) {
1328 pr_err("failed to reset CFP\n");
1329 goto out_mdio;
1330 }
1331
1332 /* Disable all interrupts and request them */
1333 bcm_sf2_intr_disable(priv);
1334
1335 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0,
1336 "switch_0", ds);
1337 if (ret < 0) {
1338 pr_err("failed to request switch_0 IRQ\n");
1339 goto out_mdio;
1340 }
1341
1342 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0,
1343 "switch_1", ds);
1344 if (ret < 0) {
1345 pr_err("failed to request switch_1 IRQ\n");
1346 goto out_mdio;
1347 }
1348
1349 /* Reset the MIB counters */
1350 reg = core_readl(priv, CORE_GMNCFGCFG);
1351 reg |= RST_MIB_CNT;
1352 core_writel(priv, reg, CORE_GMNCFGCFG);
1353 reg &= ~RST_MIB_CNT;
1354 core_writel(priv, reg, CORE_GMNCFGCFG);
1355
1356 /* Get the maximum number of ports for this switch */
1357 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
1358 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
1359 priv->hw_params.num_ports = DSA_MAX_PORTS;
1360
1361 /* Assume a single GPHY setup if we can't read that property */
1362 if (of_property_read_u32(dn, "brcm,num-gphy",
1363 &priv->hw_params.num_gphy))
1364 priv->hw_params.num_gphy = 1;
1365
1366 rev = reg_readl(priv, REG_SWITCH_REVISION);
1367 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
1368 SWITCH_TOP_REV_MASK;
1369 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
1370
1371 rev = reg_readl(priv, REG_PHY_REVISION);
1372 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
1373
1374 ret = b53_switch_register(dev);
1375 if (ret)
1376 goto out_mdio;
1377
1378 dev_info(&pdev->dev,
1379 "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n",
1380 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
1381 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
1382 priv->irq0, priv->irq1);
1383
1384 return 0;
1385
1386 out_mdio:
1387 bcm_sf2_mdio_unregister(priv);
1388 out_clk_mdiv:
1389 clk_disable_unprepare(priv->clk_mdiv);
1390 out_clk:
1391 clk_disable_unprepare(priv->clk);
1392 return ret;
1393 }
1394
bcm_sf2_sw_remove(struct platform_device * pdev)1395 static int bcm_sf2_sw_remove(struct platform_device *pdev)
1396 {
1397 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1398
1399 priv->wol_ports_mask = 0;
1400 /* Disable interrupts */
1401 bcm_sf2_intr_disable(priv);
1402 dsa_unregister_switch(priv->dev->ds);
1403 bcm_sf2_cfp_exit(priv->dev->ds);
1404 bcm_sf2_mdio_unregister(priv);
1405 clk_disable_unprepare(priv->clk_mdiv);
1406 clk_disable_unprepare(priv->clk);
1407 if (priv->type == BCM7278_DEVICE_ID && !IS_ERR(priv->rcdev))
1408 reset_control_assert(priv->rcdev);
1409
1410 return 0;
1411 }
1412
bcm_sf2_sw_shutdown(struct platform_device * pdev)1413 static void bcm_sf2_sw_shutdown(struct platform_device *pdev)
1414 {
1415 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1416
1417 /* For a kernel about to be kexec'd we want to keep the GPHY on for a
1418 * successful MDIO bus scan to occur. If we did turn off the GPHY
1419 * before (e.g: port_disable), this will also power it back on.
1420 *
1421 * Do not rely on kexec_in_progress, just power the PHY on.
1422 */
1423 if (priv->hw_params.num_gphy == 1)
1424 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1425 }
1426
1427 #ifdef CONFIG_PM_SLEEP
bcm_sf2_suspend(struct device * dev)1428 static int bcm_sf2_suspend(struct device *dev)
1429 {
1430 struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
1431
1432 return dsa_switch_suspend(priv->dev->ds);
1433 }
1434
bcm_sf2_resume(struct device * dev)1435 static int bcm_sf2_resume(struct device *dev)
1436 {
1437 struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
1438
1439 return dsa_switch_resume(priv->dev->ds);
1440 }
1441 #endif /* CONFIG_PM_SLEEP */
1442
1443 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops,
1444 bcm_sf2_suspend, bcm_sf2_resume);
1445
1446
1447 static struct platform_driver bcm_sf2_driver = {
1448 .probe = bcm_sf2_sw_probe,
1449 .remove = bcm_sf2_sw_remove,
1450 .shutdown = bcm_sf2_sw_shutdown,
1451 .driver = {
1452 .name = "brcm-sf2",
1453 .of_match_table = bcm_sf2_of_match,
1454 .pm = &bcm_sf2_pm_ops,
1455 },
1456 };
1457 module_platform_driver(bcm_sf2_driver);
1458
1459 MODULE_AUTHOR("Broadcom Corporation");
1460 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1461 MODULE_LICENSE("GPL");
1462 MODULE_ALIAS("platform:brcm-sf2");
1463