1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3  * core.c - DesignWare HS OTG Controller common routines
5  * Copyright (C) 2004-2013 Synopsys, Inc.
16  * 3. The names of the above-listed copyright holders may not be used
48 #include <linux/dma-mapping.h>
61  * dwc2_backup_global_registers() - Backup global controller registers.
71 	dev_dbg(hsotg->dev, "%s\n", __func__);  in dwc2_backup_global_registers()
74 	gr = &hsotg->gr_backup;  in dwc2_backup_global_registers()
76 	gr->gotgctl = dwc2_readl(hsotg, GOTGCTL);  in dwc2_backup_global_registers()
77 	gr->gintmsk = dwc2_readl(hsotg, GINTMSK);  in dwc2_backup_global_registers()
78 	gr->gahbcfg = dwc2_readl(hsotg, GAHBCFG);  in dwc2_backup_global_registers()
79 	gr->gusbcfg = dwc2_readl(hsotg, GUSBCFG);  in dwc2_backup_global_registers()
80 	gr->grxfsiz = dwc2_readl(hsotg, GRXFSIZ);  in dwc2_backup_global_registers()
81 	gr->gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);  in dwc2_backup_global_registers()
82 	gr->gdfifocfg = dwc2_readl(hsotg, GDFIFOCFG);  in dwc2_backup_global_registers()
83 	gr->pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1);  in dwc2_backup_global_registers()
84 	gr->glpmcfg = dwc2_readl(hsotg, GLPMCFG);  in dwc2_backup_global_registers()
85 	gr->gi2cctl = dwc2_readl(hsotg, GI2CCTL);  in dwc2_backup_global_registers()
86 	gr->pcgcctl = dwc2_readl(hsotg, PCGCTL);  in dwc2_backup_global_registers()
88 	gr->valid = true;  in dwc2_backup_global_registers()
93  * dwc2_restore_global_registers() - Restore controller global registers.
103 	dev_dbg(hsotg->dev, "%s\n", __func__);  in dwc2_restore_global_registers()
106 	gr = &hsotg->gr_backup;  in dwc2_restore_global_registers()
107 	if (!gr->valid) {  in dwc2_restore_global_registers()
108 		dev_err(hsotg->dev, "%s: no global registers to restore\n",  in dwc2_restore_global_registers()
110 		return -EINVAL;  in dwc2_restore_global_registers()
112 	gr->valid = false;  in dwc2_restore_global_registers()
115 	dwc2_writel(hsotg, gr->gotgctl, GOTGCTL);  in dwc2_restore_global_registers()
116 	dwc2_writel(hsotg, gr->gintmsk, GINTMSK);  in dwc2_restore_global_registers()
117 	dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);  in dwc2_restore_global_registers()
118 	dwc2_writel(hsotg, gr->gahbcfg, GAHBCFG);  in dwc2_restore_global_registers()
119 	dwc2_writel(hsotg, gr->grxfsiz, GRXFSIZ);  in dwc2_restore_global_registers()
120 	dwc2_writel(hsotg, gr->gnptxfsiz, GNPTXFSIZ);  in dwc2_restore_global_registers()
121 	dwc2_writel(hsotg, gr->gdfifocfg, GDFIFOCFG);  in dwc2_restore_global_registers()
122 	dwc2_writel(hsotg, gr->pcgcctl1, PCGCCTL1);  in dwc2_restore_global_registers()
123 	dwc2_writel(hsotg, gr->glpmcfg, GLPMCFG);  in dwc2_restore_global_registers()
124 	dwc2_writel(hsotg, gr->pcgcctl, PCGCTL);  in dwc2_restore_global_registers()
125 	dwc2_writel(hsotg, gr->gi2cctl, GI2CCTL);  in dwc2_restore_global_registers()
131  * dwc2_exit_partial_power_down() - Exit controller from Partial Power Down.
141 	if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_PARTIAL)  in dwc2_exit_partial_power_down()
142 		return -ENOTSUPP;  in dwc2_exit_partial_power_down()
160 			dev_err(hsotg->dev, "%s: failed to restore registers\n",  in dwc2_exit_partial_power_down()
167 				dev_err(hsotg->dev, "%s: failed to restore host registers\n",  in dwc2_exit_partial_power_down()
174 				dev_err(hsotg->dev, "%s: failed to restore device registers\n",  in dwc2_exit_partial_power_down()
185  * dwc2_enter_partial_power_down() - Put controller in Partial Power Down.
194 	if (!hsotg->params.power_down)  in dwc2_enter_partial_power_down()
195 		return -ENOTSUPP;  in dwc2_enter_partial_power_down()
200 		dev_err(hsotg->dev, "%s: failed to backup global registers\n",  in dwc2_enter_partial_power_down()
208 			dev_err(hsotg->dev, "%s: failed to backup host registers\n",  in dwc2_enter_partial_power_down()
215 			dev_err(hsotg->dev, "%s: failed to backup device registers\n",  in dwc2_enter_partial_power_down()
245  * dwc2_restore_essential_regs() - Restore essiential regs of core.
248  * @rmode: Restore mode, enabled in case of remote-wakeup.
259 	gr = &hsotg->gr_backup;  in dwc2_restore_essential_regs()
260 	dr = &hsotg->dr_backup;  in dwc2_restore_essential_regs()
261 	hr = &hsotg->hr_backup;  in dwc2_restore_essential_regs()
263 	dev_dbg(hsotg->dev, "%s: restoring essential regs\n", __func__);  in dwc2_restore_essential_regs()
266 	pcgcctl = (gr->pcgcctl & 0xffffc000);  in dwc2_restore_essential_regs()
278 	dwc2_writel(hsotg, gr->gahbcfg | GAHBCFG_GLBL_INTR_EN, GAHBCFG);  in dwc2_restore_essential_regs()
287 	dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);  in dwc2_restore_essential_regs()
290 		dwc2_writel(hsotg, hr->hcfg, HCFG);  in dwc2_restore_essential_regs()
300 		dwc2_writel(hsotg, dr->dcfg, DCFG);  in dwc2_restore_essential_regs()
313  * dwc2_hib_restore_common() - Common part of restore routine.
316  * @rem_wakeup: Remote-wakeup, enabled in case of remote-wakeup.
324 	/* Switch-on voltage to the core */  in dwc2_hib_restore_common()
372 		dev_dbg(hsotg->dev,  in dwc2_hib_restore_common()
376 		dev_dbg(hsotg->dev, "restore done  generated here\n");  in dwc2_hib_restore_common()
381  * dwc2_wait_for_mode() - Waits for the controller mode.
392 	dev_vdbg(hsotg->dev, "Waiting for %s mode\n",  in dwc2_wait_for_mode()
401 			dev_vdbg(hsotg->dev, "%s mode set\n",  in dwc2_wait_for_mode()
410 			dev_warn(hsotg->dev, "%s: Couldn't set %s mode\n",  in dwc2_wait_for_mode()
420  * dwc2_iddig_filter_enabled() - Returns true if the IDDIG debounce
454  * dwc2_enter_hibernation() - Common function to enter hibernation.
463 	if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_HIBERNATION)  in dwc2_enter_hibernation()
464 		return -ENOTSUPP;  in dwc2_enter_hibernation()
473  * dwc2_exit_hibernation() - Common function to exit from hibernation.
476  * @rem_wakeup: Remote-wakeup, enabled in case of remote-wakeup.
493  * resets all the internal state machines of the core.
500 	dev_vdbg(hsotg->dev, "%s()\n", __func__);  in dwc2_core_reset()
503 	 * If the current mode is host, either due to the force mode  in dwc2_core_reset()
527 	if ((hsotg->hw_params.snpsid & DWC2_CORE_REV_MASK) <  in dwc2_core_reset()
531 			dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL_CSFTRST\n",  in dwc2_core_reset()
533 			return -EBUSY;  in dwc2_core_reset()
538 			dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL_CSFTRST_DONE\n",  in dwc2_core_reset()
540 			return -EBUSY;  in dwc2_core_reset()
550 		dev_warn(hsotg->dev, "%s: HANG! AHB Idle timeout GRSTCTL GRSTCTL_AHBIDLE\n",  in dwc2_core_reset()
552 		return -EBUSY;  in dwc2_core_reset()
562  * dwc2_force_mode() - Force the mode of the controller.
566  * 1) If the dr_mode is set to either HOST or PERIPHERAL we force the
572  * device mode. We may need to force the mode if the current mode does
575  * In either case it only makes sense to force the mode if the
578  * Checks are done in this function to determine whether doing a force
581  * If a force is done, it requires a IDDIG debounce filter delay if
594 	dev_dbg(hsotg->dev, "Forcing mode to %s\n", host ? "host" : "device");  in dwc2_force_mode()
597 	 * Force mode has no effect if the hardware is not OTG.  in dwc2_force_mode()
604 	 * need to ever force the mode to the opposite mode.  in dwc2_force_mode()
606 	if (WARN_ON(host && hsotg->dr_mode == USB_DR_MODE_PERIPHERAL))  in dwc2_force_mode()
609 	if (WARN_ON(!host && hsotg->dr_mode == USB_DR_MODE_HOST))  in dwc2_force_mode()
626  * dwc2_clear_force_mode() - Clears the force mode bits.
631  * the force mode. We only need to call this once during probe if
643 	dev_dbg(hsotg->dev, "Clearing force mode bits\n");  in dwc2_clear_force_mode()
655  * Sets or clears force mode based on the dr_mode parameter.
659 	switch (hsotg->dr_mode) {  in dwc2_force_dr_mode()
663 		 * platforms on their host-only dwc2.  in dwc2_force_dr_mode()
676 		dev_warn(hsotg->dev, "%s() Invalid dr_mode=%d\n",  in dwc2_force_dr_mode()
677 			 __func__, hsotg->dr_mode);  in dwc2_force_dr_mode()
683  * dwc2_enable_acg - enable active clock gating feature
687 	if (hsotg->params.acg_enable) {  in dwc2_enable_acg()
690 		dev_dbg(hsotg->dev, "Enabling Active Clock Gating\n");  in dwc2_enable_acg()
697  * dwc2_dump_host_registers() - Prints the host registers
710 	dev_dbg(hsotg->dev, "Host Global Registers\n");  in dwc2_dump_host_registers()
711 	addr = hsotg->regs + HCFG;  in dwc2_dump_host_registers()
712 	dev_dbg(hsotg->dev, "HCFG	 @0x%08lX : 0x%08X\n",  in dwc2_dump_host_registers()
714 	addr = hsotg->regs + HFIR;  in dwc2_dump_host_registers()
715 	dev_dbg(hsotg->dev, "HFIR	 @0x%08lX : 0x%08X\n",  in dwc2_dump_host_registers()
717 	addr = hsotg->regs + HFNUM;  in dwc2_dump_host_registers()
718 	dev_dbg(hsotg->dev, "HFNUM	 @0x%08lX : 0x%08X\n",  in dwc2_dump_host_registers()
720 	addr = hsotg->regs + HPTXSTS;  in dwc2_dump_host_registers()
721 	dev_dbg(hsotg->dev, "HPTXSTS	 @0x%08lX : 0x%08X\n",  in dwc2_dump_host_registers()
723 	addr = hsotg->regs + HAINT;  in dwc2_dump_host_registers()
724 	dev_dbg(hsotg->dev, "HAINT	 @0x%08lX : 0x%08X\n",  in dwc2_dump_host_registers()
726 	addr = hsotg->regs + HAINTMSK;  in dwc2_dump_host_registers()
727 	dev_dbg(hsotg->dev, "HAINTMSK	 @0x%08lX : 0x%08X\n",  in dwc2_dump_host_registers()
729 	if (hsotg->params.dma_desc_enable) {  in dwc2_dump_host_registers()
730 		addr = hsotg->regs + HFLBADDR;  in dwc2_dump_host_registers()
731 		dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n",  in dwc2_dump_host_registers()
735 	addr = hsotg->regs + HPRT0;  in dwc2_dump_host_registers()
736 	dev_dbg(hsotg->dev, "HPRT0	 @0x%08lX : 0x%08X\n",  in dwc2_dump_host_registers()
739 	for (i = 0; i < hsotg->params.host_channels; i++) {  in dwc2_dump_host_registers()
740 		dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i);  in dwc2_dump_host_registers()
741 		addr = hsotg->regs + HCCHAR(i);  in dwc2_dump_host_registers()
742 		dev_dbg(hsotg->dev, "HCCHAR	 @0x%08lX : 0x%08X\n",  in dwc2_dump_host_registers()
744 		addr = hsotg->regs + HCSPLT(i);  in dwc2_dump_host_registers()
745 		dev_dbg(hsotg->dev, "HCSPLT	 @0x%08lX : 0x%08X\n",  in dwc2_dump_host_registers()
747 		addr = hsotg->regs + HCINT(i);  in dwc2_dump_host_registers()
748 		dev_dbg(hsotg->dev, "HCINT	 @0x%08lX : 0x%08X\n",  in dwc2_dump_host_registers()
750 		addr = hsotg->regs + HCINTMSK(i);  in dwc2_dump_host_registers()
751 		dev_dbg(hsotg->dev, "HCINTMSK	 @0x%08lX : 0x%08X\n",  in dwc2_dump_host_registers()
753 		addr = hsotg->regs + HCTSIZ(i);  in dwc2_dump_host_registers()
754 		dev_dbg(hsotg->dev, "HCTSIZ	 @0x%08lX : 0x%08X\n",  in dwc2_dump_host_registers()
756 		addr = hsotg->regs + HCDMA(i);  in dwc2_dump_host_registers()
757 		dev_dbg(hsotg->dev, "HCDMA	 @0x%08lX : 0x%08X\n",  in dwc2_dump_host_registers()
759 		if (hsotg->params.dma_desc_enable) {  in dwc2_dump_host_registers()
760 			addr = hsotg->regs + HCDMAB(i);  in dwc2_dump_host_registers()
761 			dev_dbg(hsotg->dev, "HCDMAB	 @0x%08lX : 0x%08X\n",  in dwc2_dump_host_registers()
770  * dwc2_dump_global_registers() - Prints the core global registers
782 	dev_dbg(hsotg->dev, "Core Global Registers\n");  in dwc2_dump_global_registers()
783 	addr = hsotg->regs + GOTGCTL;  in dwc2_dump_global_registers()
784 	dev_dbg(hsotg->dev, "GOTGCTL	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
786 	addr = hsotg->regs + GOTGINT;  in dwc2_dump_global_registers()
787 	dev_dbg(hsotg->dev, "GOTGINT	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
789 	addr = hsotg->regs + GAHBCFG;  in dwc2_dump_global_registers()
790 	dev_dbg(hsotg->dev, "GAHBCFG	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
792 	addr = hsotg->regs + GUSBCFG;  in dwc2_dump_global_registers()
793 	dev_dbg(hsotg->dev, "GUSBCFG	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
795 	addr = hsotg->regs + GRSTCTL;  in dwc2_dump_global_registers()
796 	dev_dbg(hsotg->dev, "GRSTCTL	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
798 	addr = hsotg->regs + GINTSTS;  in dwc2_dump_global_registers()
799 	dev_dbg(hsotg->dev, "GINTSTS	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
801 	addr = hsotg->regs + GINTMSK;  in dwc2_dump_global_registers()
802 	dev_dbg(hsotg->dev, "GINTMSK	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
804 	addr = hsotg->regs + GRXSTSR;  in dwc2_dump_global_registers()
805 	dev_dbg(hsotg->dev, "GRXSTSR	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
807 	addr = hsotg->regs + GRXFSIZ;  in dwc2_dump_global_registers()
808 	dev_dbg(hsotg->dev, "GRXFSIZ	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
810 	addr = hsotg->regs + GNPTXFSIZ;  in dwc2_dump_global_registers()
811 	dev_dbg(hsotg->dev, "GNPTXFSIZ	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
813 	addr = hsotg->regs + GNPTXSTS;  in dwc2_dump_global_registers()
814 	dev_dbg(hsotg->dev, "GNPTXSTS	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
816 	addr = hsotg->regs + GI2CCTL;  in dwc2_dump_global_registers()
817 	dev_dbg(hsotg->dev, "GI2CCTL	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
819 	addr = hsotg->regs + GPVNDCTL;  in dwc2_dump_global_registers()
820 	dev_dbg(hsotg->dev, "GPVNDCTL	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
822 	addr = hsotg->regs + GGPIO;  in dwc2_dump_global_registers()
823 	dev_dbg(hsotg->dev, "GGPIO	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
825 	addr = hsotg->regs + GUID;  in dwc2_dump_global_registers()
826 	dev_dbg(hsotg->dev, "GUID	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
828 	addr = hsotg->regs + GSNPSID;  in dwc2_dump_global_registers()
829 	dev_dbg(hsotg->dev, "GSNPSID	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
831 	addr = hsotg->regs + GHWCFG1;  in dwc2_dump_global_registers()
832 	dev_dbg(hsotg->dev, "GHWCFG1	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
834 	addr = hsotg->regs + GHWCFG2;  in dwc2_dump_global_registers()
835 	dev_dbg(hsotg->dev, "GHWCFG2	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
837 	addr = hsotg->regs + GHWCFG3;  in dwc2_dump_global_registers()
838 	dev_dbg(hsotg->dev, "GHWCFG3	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
840 	addr = hsotg->regs + GHWCFG4;  in dwc2_dump_global_registers()
841 	dev_dbg(hsotg->dev, "GHWCFG4	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
843 	addr = hsotg->regs + GLPMCFG;  in dwc2_dump_global_registers()
844 	dev_dbg(hsotg->dev, "GLPMCFG	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
846 	addr = hsotg->regs + GPWRDN;  in dwc2_dump_global_registers()
847 	dev_dbg(hsotg->dev, "GPWRDN	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
849 	addr = hsotg->regs + GDFIFOCFG;  in dwc2_dump_global_registers()
850 	dev_dbg(hsotg->dev, "GDFIFOCFG	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
852 	addr = hsotg->regs + HPTXFSIZ;  in dwc2_dump_global_registers()
853 	dev_dbg(hsotg->dev, "HPTXFSIZ	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
856 	addr = hsotg->regs + PCGCTL;  in dwc2_dump_global_registers()
857 	dev_dbg(hsotg->dev, "PCGCTL	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
863  * dwc2_flush_tx_fifo() - Flushes a Tx FIFO
872 	dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num);  in dwc2_flush_tx_fifo()
876 		dev_warn(hsotg->dev, "%s:  HANG! AHB Idle GRSCTL\n",  in dwc2_flush_tx_fifo()
884 		dev_warn(hsotg->dev, "%s:  HANG! timeout GRSTCTL GRSTCTL_TXFFLSH\n",  in dwc2_flush_tx_fifo()
887 	/* Wait for at least 3 PHY Clocks */  in dwc2_flush_tx_fifo()
892  * dwc2_flush_rx_fifo() - Flushes the Rx FIFO
900 	dev_vdbg(hsotg->dev, "%s()\n", __func__);  in dwc2_flush_rx_fifo()
904 		dev_warn(hsotg->dev, "%s:  HANG! AHB Idle GRSCTL\n",  in dwc2_flush_rx_fifo()
912 		dev_warn(hsotg->dev, "%s: HANG! timeout GRSTCTL GRSTCTL_RXFFLSH\n",  in dwc2_flush_rx_fifo()
915 	/* Wait for at least 3 PHY Clocks */  in dwc2_flush_rx_fifo()
928  * dwc2_enable_global_interrupts() - Enables the controller's Global
942  * dwc2_disable_global_interrupts() - Disables the controller's Global
974 /* Returns true if the controller is host-only. */
983 /* Returns true if the controller is device-only. */
993  * dwc2_hsotg_wait_bit_set - Waits for bit to be set.
999  * Return: 0 if bit/bits are set or -ETIMEDOUT in case of timeout.
1012 	return -ETIMEDOUT;  in dwc2_hsotg_wait_bit_set()
1016  * dwc2_hsotg_wait_bit_clear - Waits for bit to be clear.
1022  * Return: 0 if bit/bits are set or -ETIMEDOUT in case of timeout.
1035 	return -ETIMEDOUT;  in dwc2_hsotg_wait_bit_clear()
1040  * PHY type
1046 	if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&  in dwc2_init_fs_ls_pclk_sel()
1047 	     hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&  in dwc2_init_fs_ls_pclk_sel()
1048 	     hsotg->params.ulpi_fs_ls) ||  in dwc2_init_fs_ls_pclk_sel()
1049 	    hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {  in dwc2_init_fs_ls_pclk_sel()
1050 		/* Full speed PHY */  in dwc2_init_fs_ls_pclk_sel()
1053 		/* High speed PHY running at full speed or high speed */  in dwc2_init_fs_ls_pclk_sel()
1057 	dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);  in dwc2_init_fs_ls_pclk_sel()
1074 		dev_dbg(hsotg->dev, "FS PHY selected\n");  in dwc2_fs_phy_init()
1081 			/* Reset after a PHY select */  in dwc2_fs_phy_init()
1085 				dev_err(hsotg->dev,  in dwc2_fs_phy_init()
1091 		if (hsotg->params.activate_stm_fs_transceiver) {  in dwc2_fs_phy_init()
1094 				dev_dbg(hsotg->dev, "Activating transceiver\n");  in dwc2_fs_phy_init()
1113 	if (hsotg->params.i2c_enable) {  in dwc2_fs_phy_init()
1114 		dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");  in dwc2_fs_phy_init()
1146 	 * HS PHY parameters. These parameters are preserved during soft reset  in dwc2_hs_phy_init()
1150 	switch (hsotg->params.phy_type) {  in dwc2_hs_phy_init()
1153 		dev_dbg(hsotg->dev, "HS ULPI PHY selected\n");  in dwc2_hs_phy_init()
1156 		if (hsotg->params.phy_ulpi_ddr)  in dwc2_hs_phy_init()
1160 		if (hsotg->params.oc_disable)  in dwc2_hs_phy_init()
1166 		dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n");  in dwc2_hs_phy_init()
1168 		if (hsotg->params.phy_utmi_width == 16)  in dwc2_hs_phy_init()
1174 			if (hsotg->params.phy_utmi_width == 16)  in dwc2_hs_phy_init()
1181 		dev_err(hsotg->dev, "FS PHY selected at HS!\n");  in dwc2_hs_phy_init()
1188 		/* Reset after setting the PHY parameters */  in dwc2_hs_phy_init()
1191 			dev_err(hsotg->dev,  in dwc2_hs_phy_init()
1205 	if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||  in dwc2_phy_init()
1206 	     hsotg->params.speed == DWC2_SPEED_PARAM_LOW) &&  in dwc2_phy_init()
1207 	    hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {  in dwc2_phy_init()
1208 		/* If FS/LS mode with FS/LS PHY */  in dwc2_phy_init()
1213 		/* High speed PHY */  in dwc2_phy_init()
1219 	if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&  in dwc2_phy_init()
1220 	    hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&  in dwc2_phy_init()
1221 	    hsotg->params.ulpi_fs_ls) {  in dwc2_phy_init()
1222 		dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");  in dwc2_phy_init()