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/qemu/docs/system/devices/
H A Dkeyboard.rst4 ----------------
10 US keyboard layout.
12 With the escc.chnA-sunkbd-layout driver property it is possible to select
15 -global escc.chnA-sunkbd-layout=de
17 Depending on type of keyboard, the keyboard can have 6 or 5 dip-switches to
24 -global escc.chnA-sunkbd-layout=0x2b
26 -global escc.chnA-sunkbd-layout=43
28 -global escc.chnA-sunkbd-layout=sv
30 The above 3 examples all select a swedish keyboard layout. Table 3-15 at
31 https://docs.oracle.com/cd/E19683-01/806-6642/new-43/index.html explains which
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H A Digb.rst1 .. SPDX-License-Identifier: GPL-2.0-or-later
5 ---
10 This implementation is expected to be useful to test SR-IOV networking without
20 .. code-block:: shell
22 network.sh -6mta
35 However, you may also need to perform additional steps to activate SR-IOV
55 .. code-block:: shell
57 meson test qtest-x86_64/qos-test
65 pyvenv/bin/meson test --suite thorough func-x86_64-netdev_ethtool
70 …https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/82576eb-gigabit-ethernet-c…
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/qemu/pc-bios/keymaps/
H A Dmeson.build2 'ar': '-l ara',
3 'bepo': '-l fr -v dvorak',
4 'cz': '-l cz',
5 'da': '-l dk',
6 'de': '-l de -v nodeadkeys',
7 'de-ch': '-l ch',
8 'en-gb': '-l gb',
9 'en-us': '-l us',
10 'es': '-l es',
11 'et': '-l et',
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/qemu/docs/system/riscv/
H A Dmicrochip-icicle-kit.rst1 Microchip PolarFire SoC Icicle Kit (``microchip-icicle-kit``)
5 SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA.
8 https://www.microchip.com/en-us/products/fpgas-and-plds/system-on-chip-fpgas/polarfire-soc-fpgas
11 https://www.microchip.com/en-us/development-tool/mpfs-icicle-kit-es
14 -----------------
16 The ``microchip-icicle-kit`` machine supports the following devices:
21 * Platform-Level Interrupt Controller (PLIC)
22 * L2 Loosely Integrated Memory (L2-LIM)
34 ------------
36 The ``microchip-icicle-kit`` machine provides some options to run a firmware
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H A Dmicroblaze-v-generic.rst1 Microblaze-V generic board (``amd-microblaze-v-generic``)
3 The AMD MicroBlaze™ V processor is a soft-core RISC-V processor IP for AMD
4 adaptive SoCs and FPGAs. The MicroBlaze™ V processor is based on the 32-bit (or
5 64-bit) RISC-V instruction set architecture (ISA) and contains interfaces
10 https://docs.amd.com/r/en-US/ug1629-microblaze-v-user-guide/MicroBlaze-V-Architecture
14 - timer
15 - uartlite
16 - uart16550
17 - emaclite
18 - timer2
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/qemu/docs/devel/
H A Dcode-of-conduct.rst12 a harassment-free experience for everyone, regardless of level of
17 * Be respectful. Not all of us will agree all the time. Disagreements, both
53 conduct, please read the :ref:`conflict-resolution` document for
57 -------
60 <http://web.archive.org/web/20210429132536/https://docs.fedoraproject.org/en-US/project/code-of-con…
62 <https://www.contributor-covenant.org/version/1/3/0/code-of-conduct/>`__.
/qemu/contrib/plugins/
H A Dwin32_linker.c5 * https://learn.microsoft.com/en-us/cpp/build/reference/error-handling-and-notification
6 * It gets called when a delay-loaded DLL encounters various errors.
11 * See the COPYING.LIB file in the top-level directory.
25 if (strcmp(pdli->szDll, "qemu.exe") == 0) { in dll_failure_hook()
/qemu/docs/system/arm/
H A Dxlnx-zynq.rst1 Xilinx Zynq board (``xilinx-zynq-a9``)
4 integrate a feature-rich dual or single-core Arm Cortex-A9 MPCore based
8 https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Zynq-7000-SoC-Technical-Reference-Manual
10 QEMU xilinx-zynq-a9 board supports following devices:
11 - A9 MPCORE
12 - cortex-a9
13 - GIC v1
14 - Generic timer
15 - wdt
16 - OCM 256KB
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/qemu/hw/timer/
H A Dsse-counter.c14 * the Arm SSE-123 Example Subsystem Technical Reference Manual:
17 * The system counter is a non-stop 64-bit up-counter. It provides
21 * 88-bit precision (64.24 fixed point), with a programmable scale factor.
34 #include "hw/timer/sse-counter.h"
38 #include "hw/qdev-clock.h"
43 FIELD(CNTCR, EN, 0, 1)
50 * Although CNTCR defines interrupt-related bits, the counter doesn't
106 notifier_list_notify(&s->notifier_list, NULL); in sse_counter_notify_users()
111 return (s->cntcr & R_CNTCR_EN_MASK) != 0; in sse_counter_enabled()
120 tick -= s->ticks_then; in sse_counter_tick_to_time()
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H A Dsse-timer.c14 * the Arm SSE-123 Example Subsystem Technical Reference Manual:
17 * The timer is based around a simple 64-bit incrementing counter
19 * Counter - CompareValue >= 0.
20 * The CompareValue is guest-writable, via CNTP_CVAL_HI/LO.
22 * TimerValue = CompareValue[31:0] - Counter[31:0]
24 * This part is similar to the generic timer in an Arm A-class CPU.
26 * The timer also has a separate auto-increment timer. When this
30 * Counter - AutoIncrValue >= 0
33 * When the auto-increment timer is enabled, interrupt generation
41 #include "hw/timer/sse-timer.h"
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/qemu/include/hw/misc/
H A Dxlnx-versal-pmc-iou-slcr.h34 * https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf
37 * https://docs.xilinx.com/r/en-US/am012-versal-register-reference/PMC_IOP_SLCR-Module
44 * + Named GPIO output "sd-emmc-sel[0]": Enables 0: SD mode or 1: eMMC mode on
46 * + Named GPIO output "sd-emmc-sel[1]": Enables 0: SD mode or 1: eMMC mode on
48 * + Named GPIO output "qspi-ospi-mux-sel": Selects 0: QSPI linear region or 1:
50 * + Named GPIO output "ospi-mux-sel": Selects 0: OSPI Indirect access mode or
60 #define TYPE_XILINX_VERSAL_PMC_IOU_SLCR "xlnx.versal-pmc-iou-slcr"
/qemu/include/hw/ssi/
H A Dxlnx-versal-ospi.h34 * https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf
37 * https://docs.xilinx.com/r/en-US/am012-versal-register-reference/OSPI-Module
45 * + Named GPIO input "ospi-mux-sel": 0: enables indirect access mode
47 * + Property "dac-with-indac": Allow both direct accesses and indirect
49 * + Property "indac-write-disabled": Disable indirect access writes.
60 #define TYPE_XILINX_VERSAL_OSPI "xlnx.versal-ospi"
/qemu/docs/devel/migration/
H A Dqpl-compression.rst4 The Intel Query Processing Library (Intel ``QPL``) is an open-source library to
8 The ``QPL`` compression relies on Intel In-Memory Analytics Accelerator(``IAA``)
21 +----------------+ +------------------+
22 | MultiFD Thread | |accel-config tool |
23 +-------+--------+ +--------+---------+
27 +-------+--------+ | Setup IAA
29 +-------+---+----+ |
31 | +-------------+-------+
33 | Devices +-----+-----+
35 | +-----+-----+
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/qemu/hw/net/
H A Digb_core.h5 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/82576eg-gbe-datasheet.pdf
7 * Copyright (c) 2020-2023 Red Hat, Inc.
/qemu/tests/bench/
H A Datomic64-bench.c5 * See the COPYING file in the top-level directory.
9 #include "qemu/host-utils.h"
32 " -d = duration in seconds\n"
33 " -n = number of threads\n"
34 " -r = range (will be rounded up to pow2)";
43 * From: https://en.wikipedia.org/wiki/Xorshift
44 * This is faster than rand_r(), and gives us a wider range (RAND_MAX is only
67 info->r = xorshift64star(info->r); in thread_func()
68 index = info->r & (range - 1); in thread_func()
70 info->accesses++; in thread_func()
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H A Datomic_add-bench.c3 #include "qemu/host-utils.h"
28 " -n = number of threads\n"
29 " -m = use mutexes instead of atomic increments\n"
30 " -p = enable sync profiler\n"
31 " -d = duration in seconds\n"
32 " -r = range (will be rounded up to pow2)";
41 * From: https://en.wikipedia.org/wiki/Xorshift
42 * This is faster than rand_r(), and gives us a wider range (RAND_MAX is only
65 info->r = xorshift64star(info->r); in thread_func()
66 index = info->r & (range - 1); in thread_func()
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/qemu/block/
H A Dvhdx.h2 * Block driver for Hyper-V VHDX Images
11 * https://www.microsoft.com/en-us/download/details.aspx?id=34750
14 * See the COPYING.LIB file in the top-level directory.
32 * |----------|---------------|------------|--------------|--------------------|
47 * A note on the use of MS-GUID fields. For more details on the GUID,
48 * please see: https://en.wikipedia.org/wiki/Globally_unique_identifier.
51 * bytes are data1-data4. It makes no mention of what algorithm should be used
58 /* ---- HEADER SECTION STRUCTURES ---- */
66 uint16_t creator[256]; /* optional; utf-16 string to identify
72 /* the guid is a 16 byte unique ID - the definition for this used by
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H A Dvhdx-endian.c2 * Block driver for Hyper-V VHDX Images
11 * https://www.microsoft.com/en-us/download/details.aspx?id=34750
14 * See the COPYING.LIB file in the top-level directory.
24 * All the VHDX formats on disk are little endian - the following
37 h->signature = le32_to_cpu(h->signature); in vhdx_header_le_import()
38 h->checksum = le32_to_cpu(h->checksum); in vhdx_header_le_import()
39 h->sequence_number = le64_to_cpu(h->sequence_number); in vhdx_header_le_import()
41 leguid_to_cpus(&h->file_write_guid); in vhdx_header_le_import()
42 leguid_to_cpus(&h->data_write_guid); in vhdx_header_le_import()
43 leguid_to_cpus(&h->log_guid); in vhdx_header_le_import()
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/qemu/qga/
H A Dcommands-win32.c2 * QEMU Guest Agent win32-specific command implementations
11 * See the COPYING file in the top-level directory.
32 #include "guest-agent-core.h"
33 #include "vss-win32.h"
34 #include "qga-qapi-commands.h"
38 #include "qemu/host-utils.h"
40 #include "commands-common.h"
62 #pragma GCC diagnostic ignored "-Wredundant-decls"
82 (365 * (1970 - 1601) + \
83 (1970 - 1601) / 4 - 3))
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H A Dservice-win32.c11 * See the COPYING file in the top-level directory.
15 #include "qga/service-win32.h"
38 * <http://msdn.microsoft.com/en-us/library/windows/desktop/17w5ykft%28v=vs.85%29.aspx>.
54 /* The meaning depends on the first non-backslash character coming in win_escape_arg()
66 --backslash_count; in win_escape_arg()
78 --backslash_count; in win_escape_arg()
90 --backslash_count; in win_escape_arg()
95 return buffer->str; in win_escape_arg()
117 g_string_append_printf(cmdline, "%s -d", in ga_install_service()
121 g_string_append_printf(cmdline, " -p %s", win_escape_arg(path, esc)); in ga_install_service()
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H A Dcommands.c2 * QEMU Guest Agent common/cross-platform command implementations
10 * See the COPYING file in the top-level directory.
15 #include "guest-agent-core.h"
16 #include "qga-qapi-commands.h"
20 #include "commands-common.h"
22 /* Maximum captured guest-exec out_data/err_data - 16MB */
24 /* Allocation and I/O buffer for reading guest-exec out_data/err_data - 4KB */
27 * Maximum file size to read - 48MB
59 slog("guest-ping called"); in qmp_guest_ping()
68 cmd_info->name = g_strdup(qmp_command_name(cmd)); in qmp_command_info()
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H A Dmeson.build17 http://www.microsoft.com/en-us/download/details.aspx?id=23490
18 On POSIX-systems, MinGW should provide headers in >=10.0 releases.
20 $ scripts/extract-vsssdk-headers setup.exe
22 Then run configure with: --extra-cxxflags="-isystem /path/to/vss/inc/win2003"''') \
32 'qga-qapi-commands.c',
33 'qga-qapi-commands.h',
34 'qga-qapi-emit-events.c',
35 'qga-qapi-emit-events.h',
36 'qga-qapi-events.c',
37 'qga-qapi-events.h',
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/qemu/docs/system/i386/
H A Dtdx.rst5 Virtual Machine Extensions (VMX) and Multi-Key Total Memory Encryption (MKTME)
12 -------------
29 device and it actually works as RAM. "-bios" option is chosen to load TDVF.
32 command line to specify and load TDVF is ``-bios OVMF.fd``
35 ---------------------
37 Unlike non-TDX VM, the CPU features (enumerated by CPU or MSR) of a TD are not
43 - Attributes:
44 - PKS (bit 30) controls whether Supervisor Protection Keys is exposed to TD,
46 - PERFMON (bit 63) controls whether PMU is exposed to TD.
48 - XSAVE related features (XFAM):
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/qemu/include/hw/i386/
H A Dtopology.h28 * This file implements the APIC-ID-based CPU topology enumeration logic,
31 * http://software.intel.com/en-us/articles/intel-64-architecture-processor-topology-enumeration/
42 #include "qapi/qapi-types-machine-common.h"
46 * APIC IDs can be 32-bit, but beware: APIC IDs > 255 require x2APIC support
71 count -= 1; in apicid_bitwidth_for_count()
72 return count ? 32 - clz32(count) : 0; in apicid_bitwidth_for_count()
78 return apicid_bitwidth_for_count(topo_info->threads_per_core); in apicid_smt_width()
84 return apicid_bitwidth_for_count(topo_info->cores_per_module); in apicid_core_width()
90 return apicid_bitwidth_for_count(topo_info->modules_per_die); in apicid_module_width()
96 return apicid_bitwidth_for_count(topo_info->dies_per_pkg); in apicid_die_width()
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/qemu/hw/intc/
H A Dxilinx_intc.c6 * https://docs.amd.com/v/u/en-US/xps_intc
33 #include "hw/qdev-properties.h"
34 #include "hw/qdev-properties-system.h"
49 #define TYPE_XILINX_INTC "xlnx.xps-intc"
61 /* Configuration reg chosen at synthesis-time. QEMU populates
62 the bits at board-setup. */
76 if (p->regs[R_MER] & 2) { in update_irq()
77 p->regs[R_ISR] |= p->irq_pin_state & ~p->c_kind_of_intr; in update_irq()
81 p->regs[R_IPR] = p->regs[R_ISR] & p->regs[R_IER]; in update_irq()
85 if (p->regs[R_IPR] & (1U << i)) { in update_irq()
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