Lines Matching +full:en +full:- +full:us

6  * https://docs.amd.com/v/u/en-US/xps_intc
33 #include "hw/qdev-properties.h"
34 #include "hw/qdev-properties-system.h"
49 #define TYPE_XILINX_INTC "xlnx.xps-intc"
61 /* Configuration reg chosen at synthesis-time. QEMU populates
62 the bits at board-setup. */
76 if (p->regs[R_MER] & 2) { in update_irq()
77 p->regs[R_ISR] |= p->irq_pin_state & ~p->c_kind_of_intr; in update_irq()
81 p->regs[R_IPR] = p->regs[R_ISR] & p->regs[R_IER]; in update_irq()
85 if (p->regs[R_IPR] & (1U << i)) { in update_irq()
92 p->regs[R_IVR] = i; in update_irq()
93 qemu_set_irq(p->parent_irq, (p->regs[R_MER] & 1) && p->regs[R_IPR]); in update_irq()
105 if (addr < ARRAY_SIZE(p->regs)) in pic_read()
106 r = p->regs[addr]; in pic_read()
125 p->regs[R_ISR] &= ~value; /* ACK. */ in pic_write()
128 p->regs[R_IER] |= value; /* Atomic set ie. */ in pic_write()
131 p->regs[R_IER] &= ~value; /* Atomic clear ie. */ in pic_write()
134 p->regs[R_MER] = value & 0x3; in pic_write()
137 if ((p->regs[R_MER] & 2)) { in pic_write()
142 if (addr < ARRAY_SIZE(p->regs)) in pic_write()
143 p->regs[addr] = value; in pic_write()
162 * although some bits may be unused and is accessed on a 4-byte
178 if (p->c_kind_of_intr & (1 << irq) && p->regs[R_MER] & 2) { in irq_handler()
179 p->regs[R_ISR] |= (level << irq); in irq_handler()
182 p->irq_pin_state &= ~(1 << irq); in irq_handler()
183 p->irq_pin_state |= level << irq; in irq_handler()
192 sysbus_init_irq(SYS_BUS_DEVICE(obj), &p->parent_irq); in xilinx_intc_init()
193 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &p->mmio); in xilinx_intc_init()
200 if (p->model_endianness == ENDIAN_MODE_UNSPECIFIED) { in xilinx_intc_realize()
206 memory_region_init_io(&p->mmio, OBJECT(dev), in xilinx_intc_realize()
207 &pic_ops[p->model_endianness == ENDIAN_MODE_BIG], in xilinx_intc_realize()
208 p, "xlnx.xps-intc", in xilinx_intc_realize()
214 DEFINE_PROP_UINT32("kind-of-intr", XpsIntc, c_kind_of_intr, 0),
221 dc->realize = xilinx_intc_realize; in xilinx_intc_class_init()