Searched +full:dma +full:- +full:controller (Results 1 – 25 of 151) sorted by relevance
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6 * SPDX-License-Identifier: GPL-2.0-or-later21 /* Capabilities for SD controller: no DMA, high-speed, default clocks etc. */31 memory_region_init(&s->peri_low_mr, obj, "bcm2838-peripherals", in bcm2838_peripherals_init()32 bc->peri_low_size); in bcm2838_peripherals_init()33 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->peri_low_mr); in bcm2838_peripherals_init()35 /* Extended Mass Media Controller 2 */ in bcm2838_peripherals_init()36 object_initialize_child(obj, "emmc2", &s->emmc2, TYPE_SYSBUS_SDHCI); in bcm2838_peripherals_init()39 object_initialize_child(obj, "gpio", &s->gpio, TYPE_BCM2838_GPIO); in bcm2838_peripherals_init()41 object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhci", in bcm2838_peripherals_init()42 OBJECT(&s_base->sdhci.sdbus)); in bcm2838_peripherals_init()[all …]
6 * SPDX-License-Identifier: GPL-2.0-or-later44 qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); in bcm2838_gic_set_irq()51 object_initialize_child(obj, "peripherals", &s->peripherals, in bcm2838_init()53 object_property_add_alias(obj, "board-rev", OBJECT(&s->peripherals), in bcm2838_init()54 "board-rev"); in bcm2838_init()55 object_property_add_alias(obj, "vcram-size", OBJECT(&s->peripherals), in bcm2838_init()56 "vcram-size"); in bcm2838_init()57 object_property_add_alias(obj, "vcram-base", OBJECT(&s->peripherals), in bcm2838_init()58 "vcram-base"); in bcm2838_init()59 object_property_add_alias(obj, "command-line", OBJECT(&s->peripherals), in bcm2838_init()[all …]
9 * See the COPYING file in the top-level directory.23 /* Capabilities for SD controller: no DMA, high-speed, default clocks etc. */27 * According to Linux driver & DTS, dma channels 0--10 have separate IRQ,28 * while channels 11--14 share one IRQ:44 memory_region_add_subregion_overlap(&ps->peri_mr, ofs, in create_unimp()45 sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0), -1000); in create_unimp()54 object_initialize_child(obj, "rng", &s->rng, TYPE_BCM2835_RNG); in bcm2835_peripherals_init()57 object_initialize_child(obj, "thermal", &s->thermal, TYPE_BCM2835_THERMAL); in bcm2835_peripherals_init()60 object_initialize_child(obj, "gpio", &s->gpio, TYPE_BCM2835_GPIO); in bcm2835_peripherals_init()62 object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhci", in bcm2835_peripherals_init()[all …]
2 * Allwinner (sun4i and above) SD Host Controller emulation32 /** Generic Allwinner SD Host Controller (abstract) */33 #define TYPE_AW_SDHOST "allwinner-sdhost"36 #define TYPE_AW_SDHOST_SUN4I TYPE_AW_SDHOST "-sun4i"39 #define TYPE_AW_SDHOST_SUN5I TYPE_AW_SDHOST "-sun5i"41 /** Allwinner sun50i-a64 */42 #define TYPE_AW_SDHOST_SUN50I_A64 TYPE_AW_SDHOST "-sun50i-a64"44 /** Allwinner sun50i-a64 emmc */45 #define TYPE_AW_SDHOST_SUN50I_A64_EMMC TYPE_AW_SDHOST "-sun50i-a64-emmc"59 * Allwinner SD Host Controller object instance state.[all …]
6 Copyright (c) 2014-2015 Jiri Slaby20 ---------------------22 ``-device edu[,dma_mask=mask]``23 ``dma_mask`` makes the virtual device work with DMA addresses with the given29 ---------39 --------------46 - ``RR`` -- major version47 - ``rr`` -- minor version78 0x80 (RW) : DMA source address79 Where to perform the DMA from.[all …]
2 * ASPEED AST2400 SMC Controller (SPI Flash Only)31 #include "qemu/error-report.h"37 #include "hw/qdev-properties.h"80 (!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_ADDR_BYTE0_DISABLE_SHIFT + (i)))))82 (!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_DATA_BYTE0_DISABLE_SHIFT + (i)))))115 #define SEG_START_SHIFT 16 /* address bit [A29-A23] */135 /* DMA DRAM Side Address High Part (AST2700) */138 /* DMA Control/Status Register */151 /* DMA Flash Side Address */154 /* DMA DRAM Side Address */[all …]
2 * ARM Aspeed I2C controller27 #include "qemu/error-report.h"31 #include "hw/qdev-properties.h"40 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); in aspeed_i2c_bus_raise_interrupt()43 uint32_t intr_ctrl_mask = bus->regs[intr_ctrl_reg] | in aspeed_i2c_bus_raise_interrupt()50 ARRAY_FIELD_EX32(bus->regs, I2CM_INTR_STS, PKT_CMD_DONE) ? in aspeed_i2c_bus_raise_interrupt()52 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, TX_NAK) ? in aspeed_i2c_bus_raise_interrupt()54 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, TX_ACK) ? in aspeed_i2c_bus_raise_interrupt()56 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, RX_DONE) ? in aspeed_i2c_bus_raise_interrupt()58 ARRAY_FIELD_EX32(bus->regs, I2CD_INTR_STS, SLAVE_ADDR_RX_MATCH) ? in aspeed_i2c_bus_raise_interrupt()[all …]
... (dma-alloc) ppc-dma-map-in ['] ppc-dma-map-in ...
2 * QTest testcase for BCM283x DMA engine (on Raspberry Pi 3)3 * and its interrupts coming to Interrupt Controller.7 * SPDX-License-Identifier: GPL-2.0-or-later11 #include "libqtest-single.h"19 /* DMA engine registers: */28 /* DMA Transfer Info fields: */33 /* Interrupt controller registers: */85 /* Check that interrupt status is set both in DMA and IC controllers: */ in bcm2835_dma_test_interrupt()101 /* DMA engines 0--10 have separate IRQ lines, 11--14 - only one: */ in bcm2835_dma_test_interrupts()112 qtest_add_func("/bcm2835/dma/test_interrupts", in main()[all …]
2 * Allwinner (sun4i and above) SD Host Controller emulation26 #include "system/dma.h"27 #include "hw/qdev-properties.h"29 #include "hw/sd/allwinner-sdhost.h"34 #define TYPE_AW_SDHOST_BUS "allwinner-sdhost-bus"64 REG_SD_DMAC = 0x80, /* Internal DMA Controller Control */66 REG_SD_IDST = 0x88, /* Internal DMA Controller Status */67 REG_SD_IDIE = 0x8C, /* Internal DMA Controller IRQ Enable */80 REG_SD_SAMP_DL = 0x144, /* Sample Delay Control (sun50i-a64) */166 /* Data transfer descriptor for DMA */[all …]
2 * DMA helper functions14 #include "system/address-spaces.h"27 * or less have to treat these as 64-bit always to cover all (or at49 * This is called before DMA read and write operations in dma_barrier()64 * transfer, the DMA context, etc... in dma_barrier()69 /* Checks that the given range of addresses is valid for DMA. This is111 * dma_memory_rw: Read from or write to an address space from DMA controller.134 * dma_memory_read: Read from an address space from DMA controller.155 * dma_memory_write: Write to address space from DMA controller.176 * dma_memory_set: Fill memory with a constant byte from DMA controller.[all …]
26 * The controller is used in Sun4m systems in a slightly different27 * way. There are changes in DOR register and DMA is not available.33 #include "qemu/error-report.h"38 #include "hw/qdev-properties.h"39 #include "hw/qdev-properties-system.h"42 #include "system/block-backend.h"47 #include "qemu/main-loop.h"51 #include "fdc-internal.h"62 uint32_t dma; member72 FDCtrl *s = &isa->state; in fdctrl_external_reset_isa()[all …]
33 #include "fdc-internal.h"36 #define TYPE_SYSBUS_FDC "base-sysbus-fdc"89 FDCtrl *s = &sys->state; in fdctrl_external_reset_sysbus()105 dev = qdev_new("sysbus-fdc"); in fdctrl_init_sysbus()112 fdctrl_init_drives(&sys->state.bus, fds); in fdctrl_init_sysbus()121 dev = qdev_new("sun-fdtwo"); in sun4m_fdctrl_init()128 fdctrl_init_drives(&sys->state.bus, fds); in sun4m_fdctrl_init()137 FDCtrl *fdctrl = &sys->state; in sysbus_fdc_common_instance_init()140 * DMA is not currently supported for sysbus floppy controllers. in sysbus_fdc_common_instance_init()142 * to have a QOM link property 'dma-controller' which the board in sysbus_fdc_common_instance_init()[all …]
26 * The controller is used in Sun4m systems in a slightly different27 * way. There are changes in DOR register and DMA is not available.33 #include "qemu/error-report.h"38 #include "hw/qdev-properties.h"39 #include "hw/qdev-properties-system.h"42 #include "system/block-backend.h"46 #include "qemu/main-loop.h"50 #include "fdc-internal.h"74 #define TYPE_FLOPPY_BUS "floppy-bus"88 bus->fdc = fdc; in floppy_bus_create()[all …]
1 = How to convert to -device & friends =7 -device parameter bus.10 where this address can be configured, devices provide a bus-specific16 SCSI scsi-id %u19 virtio-serial-bus nr %u20 ccid-bus slot %u23 Example: device i440FX-pcihost is on the root bus, and provides a PCI24 bus named pci.0. To put a FOO device into its slot 4, use -device25 FOO,bus=/i440FX-pcihost/pci.0,addr=4. The abbreviated form bus=pci.032 In the general case, the guest device is connected to a controller[all …]
8 ARM1176JZF-S core, 512 MiB of RAM10 Cortex-A7 (4 cores), 1 GiB of RAM12 Cortex-A53 (4 cores), 512 MiB of RAM14 Cortex-A53 (4 cores), 1 GiB of RAM16 Cortex-A72 (4 cores), 2 GiB of RAM19 -------------------21 * ARM1176JZF-S, Cortex-A7, Cortex-A53 or Cortex-A72 CPU22 * Interrupt controller23 * DMA controller24 * Clock and reset controller (CPRMAN)[all …]
1 STMicroelectronics STM32 boards (``netduino2``, ``netduinoplus2``, ``olimex-stm32-h405``, ``stm32vl…4 The `STM32`_ chips are a family of 32-bit ARM-based microcontroller by7 .. _STM32: https://www.st.com/en/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus.html9 The STM32F1 series is based on ARM Cortex-M3 core. The following machines are12 - ``stm32vldiscovery`` STM32VLDISCOVERY board with STM32F100RBT6 microcontroller14 The STM32F2 series is based on ARM Cortex-M3 core. The following machines are17 - ``netduino2`` Netduino 2 board with STM32F205RFT6 microcontroller19 The STM32F4 series is based on ARM Cortex-M4F core, as well as the STM32L420 ultra-low-power series. The STM32F4 series is pin-to-pin compatible with STM32F2 series.21 The following machines are based on this ARM Cortex-M4F chip :[all …]
2 * On-chip DMA controller framework.21 #include "qemu/error-report.h"27 memcpy(ch->paddr[0], ch->paddr[1], ch->bytes); in transfer_mem2mem()28 ch->paddr[0] += ch->bytes; in transfer_mem2mem()29 ch->paddr[1] += ch->bytes; in transfer_mem2mem()34 ch->io_fn[1](ch->io_opaque[1], ch->paddr[0], ch->bytes); in transfer_mem2fifo()35 ch->paddr[0] += ch->bytes; in transfer_mem2fifo()40 ch->io_fn[0](ch->io_opaque[0], ch->paddr[1], ch->bytes); in transfer_fifo2mem()41 ch->paddr[1] += ch->bytes; in transfer_fifo2mem()45 * DMA peripherals forbid this kind of transfers and even when they don't,[all …]
2 * QEMU Intel 82374 emulation (Enhanced DMA controller)29 #include "hw/qdev-properties.h"31 #include "hw/dma/i8257.h"129 error_setg(errp, "DMA already initialized on ISA bus"); in i82374_realize()134 portio_list_init(&s->port_list, OBJECT(s), i82374_portio_list, s, in i82374_realize()136 portio_list_add(&s->port_list, isa_address_space_io(&s->parent_obj), in i82374_realize()137 s->iobase); in i82374_realize()139 memset(s->commands, 0, sizeof(s->commands)); in i82374_realize()150 dc->realize = i82374_realize; in i82374_class_init()151 dc->vmsd = &vmstate_i82374; in i82374_class_init()[all …]
2 * On-chip DMA controller framework.45 struct soc_dma_s *dma; member53 /* This should be set by dma->setup_fn(). */55 /* Initialised by the DMA module, call soc_dma_ch_update after writing. */66 /* Set and used by the DMA module. */71 /* Following fields are set by the SoC DMA module and can be used79 /* Set by soc_dma_init() for use by the DMA module. */83 /* Call to activate or stop a DMA channel. */87 * ch->type[0...1],88 * ch->vaddr[0...1],[all …]
5 * arch/arm/mach-{bcm2708,bcm2709}/include/mach/platform.h25 * https://github.com/hermanhermitage/videocoreiv/wiki/MMIO-Register-map34 /* Registered machine type (matches RPi Foundation bootloader and U-Boot) */37 #define TYPE_RASPI_BASE_MACHINE MACHINE_TYPE_NAME("raspi-base")69 #define INTE_OFFSET 0x2000 /* VC Interrupt controller */73 #define MPHI_OFFSET 0x6000 /* Message-based Parallel Host Intf. */74 #define DMA_OFFSET 0x7000 /* DMA controller, channels 0-14 */79 #define ARMCTRL_IC_OFFSET (ARM_OFFSET + 0x200) /* Interrupt controller */123 #define USB_OTG_OFFSET 0x980000 /* DTC_OTG USB controller */126 #define L2CC_OFFSET 0xe01000 /* Level 2 Cache controller */[all …]
5 * Copyright (c) 2024 Mark Cave-Ayland15 #include "exec/cpu-interrupt.h"19 #include "hw/m68k/next-cube.h"28 #include "hw/qdev-properties.h"30 #include "qemu/error-report.h"48 #define TYPE_NEXT_RTC "next-rtc"66 #define TYPE_NEXT_SCSI "next-scsi"69 /* NeXT SCSI Controller */82 #define TYPE_NEXT_PC "next-pc"85 /* NeXT Peripheral Controller */[all …]
4 * Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>11 /dts-v1/;14 #address-cells = <2>;15 #size-cells = <1>;18 dcr-parent = <&{/cpus/cpu@0}>;28 #address-cells = <1>;29 #size-cells = <0>;35 clock-frequency = <0>; /* Filled in by U-Boot */36 timebase-frequency = <0>; /* Filled in by U-Boot */37 i-cache-line-size = <32>;[all …]
2 * GUSEMU32 - API4 * Copyright (C) 2000-2007 Tibor "TS" Schütz31 …uint8_t *gusdatapos; /* (gusdataend-gusdata) bytes used for storing emulated GF1/mixer register st…40 /* NMI is defined as hwirq=-1 (not supported (yet?)) */45 void GUS_irqclear( GUSEmuState *state, int hwirq); /* used by gus_write() only - can be left empty…46 void GUS_dmarequest(GUSEmuState *state); /* used by gus_write() only - can be left empty…59 /* DMA data transfer function */62 /* Called back by GUS_start_DMA as soon as the emulated DMA controller is ready for a transfer to o…63 /* (might be immediately if the DMA controller was programmed first) */65 /* do not forget to update DMA states after the call, including the DREQ and TC flags */[all …]
2 * ASPEED AST2400 I2C Controller18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.30 #define TYPE_ASPEED_2400_I2C TYPE_ASPEED_I2C "-ast2400"31 #define TYPE_ASPEED_2500_I2C TYPE_ASPEED_I2C "-ast2500"32 #define TYPE_ASPEED_2600_I2C TYPE_ASPEED_I2C "-ast2600"33 #define TYPE_ASPEED_1030_I2C TYPE_ASPEED_I2C "-ast1030"34 #define TYPE_ASPEED_2700_I2C TYPE_ASPEED_I2C "-ast2700"101 SHARED_FIELD(SMBUS_ALERT, 12, 1) /* Bus [0-3] only */152 REG32(I2CD_DMA_ADDR, 0x24) /* DMA Buffer Address */153 REG32(I2CD_DMA_LEN, 0x28) /* DMA Transfer Length < 4KB */[all …]