Lines Matching +full:dma +full:- +full:controller
2 * ASPEED AST2400 SMC Controller (SPI Flash Only)
31 #include "qemu/error-report.h"
37 #include "hw/qdev-properties.h"
80 (!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_ADDR_BYTE0_DISABLE_SHIFT + (i)))))
82 (!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_DATA_BYTE0_DISABLE_SHIFT + (i)))))
115 #define SEG_START_SHIFT 16 /* address bit [A29-A23] */
135 /* DMA DRAM Side Address High Part (AST2700) */
138 /* DMA Control/Status Register */
151 /* DMA Flash Side Address */
154 /* DMA DRAM Side Address */
157 /* DMA Length Register */
166 /* SPI controller registers and bits (AST2400) */
177 * DMA DRAM addresses should be 4 bytes aligned and the valid address
178 * range is 0x40000000 - 0x5FFFFFFF (AST2400)
179 * 0x80000000 - 0xBFFFFFFF (AST2500)
181 * DMA flash addresses should be 4 bytes aligned and the valid address
182 * range is 0x20000000 - 0x2FFFFFFF.
184 * DMA length is from 4 bytes to 32MB (AST2500)
188 * DMA length is from 1 byte to 32MB (AST2600, AST10x0 and AST2700)
192 #define DMA_DRAM_ADDR(asc, val) ((val) & (asc)->dma_dram_mask)
194 #define DMA_FLASH_ADDR(asc, val) ((val) & (asc)->dma_flash_mask)
205 * controller. These can be changed when board is initialized with the
218 return !!(asc->features & ASPEED_SMC_FEATURE_DMA); in aspeed_smc_has_dma()
223 return !!(asc->features & ASPEED_SMC_FEATURE_WDT_CONTROL); in aspeed_smc_has_wdt_control()
228 return !!(asc->features & ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH); in aspeed_smc_has_dma64()
242 for (i = 0; i < asc->cs_num_max; i++) { in aspeed_smc_flash_overlap()
247 asc->reg_to_segment(s, s->regs[R_SEG_ADDR0 + i], &seg); in aspeed_smc_flash_overlap()
249 if (new->addr + new->size > seg.addr && in aspeed_smc_flash_overlap()
250 new->addr < seg.addr + seg.size) { in aspeed_smc_flash_overlap()
252 HWADDR_PRIx" - 0x%"HWADDR_PRIx" ] overlaps with " in aspeed_smc_flash_overlap()
253 "CS%d [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]", in aspeed_smc_flash_overlap()
254 cs, new->addr, new->addr + new->size, in aspeed_smc_flash_overlap()
266 AspeedSMCFlash *fl = &s->flashes[cs]; in aspeed_smc_flash_set_segment_region()
269 asc->reg_to_segment(s, regval, &seg); in aspeed_smc_flash_set_segment_region()
272 memory_region_set_size(&fl->mmio, seg.size); in aspeed_smc_flash_set_segment_region()
273 memory_region_set_address(&fl->mmio, seg.addr - asc->flash_window_base); in aspeed_smc_flash_set_segment_region()
274 memory_region_set_enabled(&fl->mmio, !!seg.size); in aspeed_smc_flash_set_segment_region()
277 if (asc->segment_addr_mask) { in aspeed_smc_flash_set_segment_region()
278 regval &= asc->segment_addr_mask; in aspeed_smc_flash_set_segment_region()
281 s->regs[R_SEG_ADDR0 + cs] = regval; in aspeed_smc_flash_set_segment_region()
290 asc->reg_to_segment(s, new, &seg); in aspeed_smc_flash_set_segment()
294 /* The start address of CS0 is read-only */ in aspeed_smc_flash_set_segment()
295 if (cs == 0 && seg.addr != asc->flash_window_base) { in aspeed_smc_flash_set_segment()
298 seg.addr = asc->flash_window_base; in aspeed_smc_flash_set_segment()
299 new = asc->segment_to_reg(s, &seg); in aspeed_smc_flash_set_segment()
304 * read-only. in aspeed_smc_flash_set_segment()
306 if ((asc->segments == aspeed_2500_spi1_segments || in aspeed_smc_flash_set_segment()
307 asc->segments == aspeed_2500_spi2_segments) && in aspeed_smc_flash_set_segment()
308 cs == asc->cs_num_max && in aspeed_smc_flash_set_segment()
309 seg.addr + seg.size != asc->segments[cs].addr + in aspeed_smc_flash_set_segment()
310 asc->segments[cs].size) { in aspeed_smc_flash_set_segment()
313 seg.size = asc->segments[cs].addr + asc->segments[cs].size - in aspeed_smc_flash_set_segment()
315 new = asc->segment_to_reg(s, &seg); in aspeed_smc_flash_set_segment()
320 (seg.addr + seg.size <= asc->flash_window_base || in aspeed_smc_flash_set_segment()
321 seg.addr > asc->flash_window_base + asc->flash_window_size)) { in aspeed_smc_flash_set_segment()
323 "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]", in aspeed_smc_flash_set_segment()
331 "aligned : [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]", in aspeed_smc_flash_set_segment()
368 const AspeedSMCState *s = fl->controller; in aspeed_smc_flash_mode()
370 return s->regs[s->r_ctrl0 + fl->cs] & CTRL_CMD_MODE_MASK; in aspeed_smc_flash_mode()
375 const AspeedSMCState *s = fl->controller; in aspeed_smc_is_writable()
377 return s->regs[s->r_conf] & (1 << (s->conf_enable_w0 + fl->cs)); in aspeed_smc_is_writable()
382 const AspeedSMCState *s = fl->controller; in aspeed_smc_flash_cmd()
383 int cmd = (s->regs[s->r_ctrl0 + fl->cs] >> CTRL_CMD_SHIFT) & CTRL_CMD_MASK; in aspeed_smc_flash_cmd()
405 const AspeedSMCState *s = fl->controller; in aspeed_smc_flash_addr_width()
406 AspeedSMCClass *asc = fl->asc; in aspeed_smc_flash_addr_width()
408 if (asc->addr_width) { in aspeed_smc_flash_addr_width()
409 return asc->addr_width(s); in aspeed_smc_flash_addr_width()
411 return s->regs[s->r_ce_ctrl] & (1 << (CTRL_EXTENDED0 + fl->cs)) ? 4 : 3; in aspeed_smc_flash_addr_width()
417 AspeedSMCState *s = fl->controller; in aspeed_smc_flash_do_select()
419 trace_aspeed_smc_flash_select(fl->cs, unselect ? "un" : ""); in aspeed_smc_flash_do_select()
420 s->unselect = unselect; in aspeed_smc_flash_do_select()
421 qemu_set_irq(s->cs_lines[fl->cs], unselect); in aspeed_smc_flash_do_select()
437 const AspeedSMCState *s = fl->controller; in aspeed_smc_check_segment_addr()
438 AspeedSMCClass *asc = fl->asc; in aspeed_smc_check_segment_addr()
441 asc->reg_to_segment(s, s->regs[R_SEG_ADDR0 + fl->cs], &seg); in aspeed_smc_check_segment_addr()
444 "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]", in aspeed_smc_check_segment_addr()
445 addr, fl->cs, seg.addr, seg.addr + seg.size); in aspeed_smc_check_segment_addr()
454 const AspeedSMCState *s = fl->controller; in aspeed_smc_flash_dummies()
455 uint32_t r_ctrl0 = s->regs[s->r_ctrl0 + fl->cs]; in aspeed_smc_flash_dummies()
469 const AspeedSMCState *s = fl->controller; in aspeed_smc_flash_setup()
476 ssi_transfer(s->spi, cmd); in aspeed_smc_flash_setup()
477 while (i--) { in aspeed_smc_flash_setup()
479 ssi_transfer(s->spi, (addr >> (i * 8)) & 0xff); in aspeed_smc_flash_setup()
485 * be configured to some non-zero value in fast read mode and in aspeed_smc_flash_setup()
491 ssi_transfer(fl->controller->spi, s->regs[R_DUMMY_DATA] & 0xff); in aspeed_smc_flash_setup()
499 AspeedSMCState *s = fl->controller; in aspeed_smc_flash_read()
506 ret |= (uint64_t) ssi_transfer(s->spi, 0x0) << (8 * i); in aspeed_smc_flash_read()
515 ret |= (uint64_t) ssi_transfer(s->spi, 0x0) << (8 * i); in aspeed_smc_flash_read()
524 trace_aspeed_smc_flash_read(fl->cs, addr, size, ret, in aspeed_smc_flash_read()
571 return -1; in aspeed_smc_num_dummies()
578 AspeedSMCState *s = fl->controller; in aspeed_smc_do_snoop()
581 trace_aspeed_smc_do_snoop(fl->cs, s->snoop_index, s->snoop_dummies, in aspeed_smc_do_snoop()
584 if (s->snoop_index == SNOOP_OFF) { in aspeed_smc_do_snoop()
587 } else if (s->snoop_index == SNOOP_START) { in aspeed_smc_do_snoop()
596 s->snoop_index = SNOOP_OFF; in aspeed_smc_do_snoop()
600 s->snoop_dummies = ndummies * 8; in aspeed_smc_do_snoop()
602 } else if (s->snoop_index >= addr_width + 1) { in aspeed_smc_do_snoop()
605 for (; s->snoop_dummies; s->snoop_dummies--) { in aspeed_smc_do_snoop()
606 ssi_transfer(s->spi, s->regs[R_DUMMY_DATA] & 0xff); in aspeed_smc_do_snoop()
610 if (!s->snoop_dummies) { in aspeed_smc_do_snoop()
611 s->snoop_index = SNOOP_OFF; in aspeed_smc_do_snoop()
613 s->snoop_index += size; in aspeed_smc_do_snoop()
623 s->snoop_index += size; in aspeed_smc_do_snoop()
631 AspeedSMCState *s = fl->controller; in aspeed_smc_flash_write()
634 trace_aspeed_smc_flash_write(fl->cs, addr, size, data, in aspeed_smc_flash_write()
649 ssi_transfer(s->spi, (data >> (8 * i)) & 0xff); in aspeed_smc_flash_write()
657 ssi_transfer(s->spi, (data >> (8 * i)) & 0xff); in aspeed_smc_flash_write()
679 AspeedSMCState *s = fl->controller; in aspeed_smc_flash_update_ctrl()
684 old_mode = s->regs[s->r_ctrl0 + fl->cs] & CTRL_CMD_MODE_MASK; in aspeed_smc_flash_update_ctrl()
693 if (!(s->regs[s->r_ctrl0 + fl->cs] & CTRL_CE_STOP_ACTIVE) && in aspeed_smc_flash_update_ctrl()
703 s->regs[s->r_ctrl0 + fl->cs] = value; in aspeed_smc_flash_update_ctrl()
705 if (unselect != s->unselect) { in aspeed_smc_flash_update_ctrl()
706 s->snoop_index = unselect ? SNOOP_OFF : SNOOP_START; in aspeed_smc_flash_update_ctrl()
717 if (asc->resets) { in aspeed_smc_reset()
718 memcpy(s->regs, asc->resets, sizeof s->regs); in aspeed_smc_reset()
720 memset(s->regs, 0, sizeof s->regs); in aspeed_smc_reset()
723 for (i = 0; i < asc->cs_num_max; i++) { in aspeed_smc_reset()
724 DeviceState *dev = ssi_get_cs(s->spi, i); in aspeed_smc_reset()
730 BUS(s->spi)->name, i, object_get_typename(o)); in aspeed_smc_reset()
740 for (i = 0; i < asc->cs_num_max; ++i) { in aspeed_smc_reset()
741 s->regs[s->r_ctrl0 + i] |= CTRL_CE_STOP_ACTIVE; in aspeed_smc_reset()
742 qemu_set_irq(s->cs_lines[i], true); in aspeed_smc_reset()
745 s->unselect = true; in aspeed_smc_reset()
748 for (i = 0; i < asc->cs_num_max; ++i) { in aspeed_smc_reset()
750 asc->segment_to_reg(s, &asc->segments[i])); in aspeed_smc_reset()
753 s->snoop_index = SNOOP_OFF; in aspeed_smc_reset()
754 s->snoop_dummies = 0; in aspeed_smc_reset()
764 if (addr == s->r_conf || in aspeed_smc_read()
765 (addr >= s->r_timings && in aspeed_smc_read()
766 addr < s->r_timings + asc->nregs_timings) || in aspeed_smc_read()
767 addr == s->r_ce_ctrl || in aspeed_smc_read()
780 addr < R_SEG_ADDR0 + asc->cs_num_max) || in aspeed_smc_read()
781 (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + asc->cs_num_max)) { in aspeed_smc_read()
783 trace_aspeed_smc_read(addr << 2, size, s->regs[addr]); in aspeed_smc_read()
785 return s->regs[addr]; in aspeed_smc_read()
789 return -1; in aspeed_smc_read()
813 * Register are set using bit[11:4] of the DMA Control Register.
818 (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MASK; in aspeed_smc_dma_calibration()
820 (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK; in aspeed_smc_dma_calibration()
822 uint32_t hclk_shift = (hclk_div - 1) << 2; in aspeed_smc_dma_calibration()
827 * the SPI bus and only HCLK/1 - HCLK/5 can have tunable delays in aspeed_smc_dma_calibration()
830 s->regs[s->r_timings] &= ~(0xf << hclk_shift); in aspeed_smc_dma_calibration()
831 s->regs[s->r_timings] |= delay << hclk_shift; in aspeed_smc_dma_calibration()
835 * TODO: compute the CS from the DMA address and the segment in aspeed_smc_dma_calibration()
841 s->regs[s->r_ctrl0 + cs] &= in aspeed_smc_dma_calibration()
843 s->regs[s->r_ctrl0 + cs] |= CE_CTRL_CLOCK_FREQ(hclk_div); in aspeed_smc_dma_calibration()
847 * Emulate read errors in the DMA Checksum Register for high
855 (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MASK; in aspeed_smc_inject_read_failure()
857 (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK; in aspeed_smc_inject_read_failure()
860 * Typical values of a palmetto-bmc machine. in aspeed_smc_inject_read_failure()
869 case 1: /* (> 100MHz) is above the max freq of the controller */ in aspeed_smc_inject_read_failure()
878 return s->regs[R_DMA_DRAM_ADDR] | in aspeed_smc_dma_dram_addr()
879 ((uint64_t) s->regs[R_DMA_DRAM_ADDR_HIGH] << 32); in aspeed_smc_dma_dram_addr()
886 return QEMU_ALIGN_UP(s->regs[R_DMA_LEN] + asc->dma_start_length, 4); in aspeed_smc_dma_len()
899 if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) { in aspeed_smc_dma_checksum()
900 aspeed_smc_error("invalid direction for DMA checksum"); in aspeed_smc_dma_checksum()
904 if (s->regs[R_DMA_CTRL] & DMA_CTRL_CALIB) { in aspeed_smc_dma_checksum()
911 data = address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR], in aspeed_smc_dma_checksum()
915 s->regs[R_DMA_FLASH_ADDR]); in aspeed_smc_dma_checksum()
918 trace_aspeed_smc_dma_checksum(s->regs[R_DMA_FLASH_ADDR], data); in aspeed_smc_dma_checksum()
921 * When the DMA is on-going, the DMA registers are updated in aspeed_smc_dma_checksum()
924 s->regs[R_DMA_CHECKSUM] += data; in aspeed_smc_dma_checksum()
925 s->regs[R_DMA_FLASH_ADDR] += 4; in aspeed_smc_dma_checksum()
926 dma_len -= 4; in aspeed_smc_dma_checksum()
927 s->regs[R_DMA_LEN] = dma_len; in aspeed_smc_dma_checksum()
930 if (s->inject_failure && aspeed_smc_inject_read_failure(s)) { in aspeed_smc_dma_checksum()
931 s->regs[R_DMA_CHECKSUM] = 0xbadc0de; in aspeed_smc_dma_checksum()
949 dma_dram_offset = dma_dram_addr - s->dram_base; in aspeed_smc_dma_rw()
954 trace_aspeed_smc_dma_rw(s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE ? in aspeed_smc_dma_rw()
956 s->regs[R_DMA_FLASH_ADDR], in aspeed_smc_dma_rw()
960 if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) { in aspeed_smc_dma_rw()
961 data = address_space_ldl_le(&s->dram_as, dma_dram_offset, in aspeed_smc_dma_rw()
969 address_space_stl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR], in aspeed_smc_dma_rw()
973 s->regs[R_DMA_FLASH_ADDR]); in aspeed_smc_dma_rw()
977 data = address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR], in aspeed_smc_dma_rw()
981 s->regs[R_DMA_FLASH_ADDR]); in aspeed_smc_dma_rw()
985 address_space_stl_le(&s->dram_as, dma_dram_offset, in aspeed_smc_dma_rw()
995 * When the DMA is on-going, the DMA registers are updated in aspeed_smc_dma_rw()
1001 s->regs[R_DMA_DRAM_ADDR_HIGH] = dma_dram_addr >> 32; in aspeed_smc_dma_rw()
1002 s->regs[R_DMA_DRAM_ADDR] = dma_dram_addr & 0xffffffff; in aspeed_smc_dma_rw()
1003 s->regs[R_DMA_FLASH_ADDR] += 4; in aspeed_smc_dma_rw()
1004 dma_len -= 4; in aspeed_smc_dma_rw()
1005 s->regs[R_DMA_LEN] = dma_len; in aspeed_smc_dma_rw()
1006 s->regs[R_DMA_CHECKSUM] += data; in aspeed_smc_dma_rw()
1013 * When the DMA is disabled, INTR_CTRL_DMA_STATUS=0 means the in aspeed_smc_dma_stop()
1016 s->regs[R_INTR_CTRL] &= ~INTR_CTRL_DMA_STATUS; in aspeed_smc_dma_stop()
1017 s->regs[R_DMA_CHECKSUM] = 0; in aspeed_smc_dma_stop()
1020 * Lower the DMA irq in any case. The IRQ control register could in aspeed_smc_dma_stop()
1021 * have been cleared before disabling the DMA. in aspeed_smc_dma_stop()
1023 qemu_irq_lower(s->irq); in aspeed_smc_dma_stop()
1027 * When INTR_CTRL_DMA_STATUS=1, the DMA has completed and a new DMA
1032 return s->regs[R_DMA_CTRL] & DMA_CTRL_ENABLE && in aspeed_smc_dma_in_progress()
1033 !(s->regs[R_INTR_CTRL] & INTR_CTRL_DMA_STATUS); in aspeed_smc_dma_in_progress()
1038 s->regs[R_INTR_CTRL] |= INTR_CTRL_DMA_STATUS; in aspeed_smc_dma_done()
1039 if (s->regs[R_INTR_CTRL] & INTR_CTRL_DMA_EN) { in aspeed_smc_dma_done()
1040 qemu_irq_raise(s->irq); in aspeed_smc_dma_done()
1047 s->regs[R_DMA_CTRL] = dma_ctrl; in aspeed_smc_dma_ctrl()
1054 aspeed_smc_error("DMA in progress !"); in aspeed_smc_dma_ctrl()
1058 s->regs[R_DMA_CTRL] = dma_ctrl; in aspeed_smc_dma_ctrl()
1060 if (s->regs[R_DMA_CTRL] & DMA_CTRL_CKSUM) { in aspeed_smc_dma_ctrl()
1073 if (!(asc->features & ASPEED_SMC_FEATURE_DMA_GRANT)) { in aspeed_smc_dma_granted()
1077 if (!(s->regs[R_DMA_CTRL] & DMA_CTRL_GRANT)) { in aspeed_smc_dma_granted()
1078 aspeed_smc_error("DMA not granted"); in aspeed_smc_dma_granted()
1087 /* Preserve DMA bits */ in aspeed_2600_smc_dma_ctrl()
1088 dma_ctrl |= s->regs[R_DMA_CTRL] & (DMA_CTRL_REQUEST | DMA_CTRL_GRANT); in aspeed_2600_smc_dma_ctrl()
1092 s->regs[R_DMA_CTRL] |= (DMA_CTRL_REQUEST | DMA_CTRL_GRANT); in aspeed_2600_smc_dma_ctrl()
1098 s->regs[R_DMA_CTRL] &= ~(DMA_CTRL_REQUEST | DMA_CTRL_GRANT); in aspeed_2600_smc_dma_ctrl()
1103 aspeed_smc_error("DMA not granted"); in aspeed_2600_smc_dma_ctrl()
1108 s->regs[R_DMA_CTRL] &= ~(DMA_CTRL_REQUEST | DMA_CTRL_GRANT); in aspeed_2600_smc_dma_ctrl()
1122 if (addr == s->r_conf || in aspeed_smc_write()
1123 (addr >= s->r_timings && in aspeed_smc_write()
1124 addr < s->r_timings + asc->nregs_timings) || in aspeed_smc_write()
1125 addr == s->r_ce_ctrl) { in aspeed_smc_write()
1126 s->regs[addr] = value; in aspeed_smc_write()
1127 } else if (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + asc->cs_num_max) { in aspeed_smc_write()
1128 int cs = addr - s->r_ctrl0; in aspeed_smc_write()
1129 aspeed_smc_flash_update_ctrl(&s->flashes[cs], value); in aspeed_smc_write()
1131 addr < R_SEG_ADDR0 + asc->cs_num_max) { in aspeed_smc_write()
1132 int cs = addr - R_SEG_ADDR0; in aspeed_smc_write()
1134 if (value != s->regs[R_SEG_ADDR0 + cs]) { in aspeed_smc_write()
1138 s->regs[addr] = value & 0xff; in aspeed_smc_write()
1140 s->regs[addr] = value & 0xff; in aspeed_smc_write()
1142 s->regs[addr] = value & FMC_WDT2_CTRL_EN; in aspeed_smc_write()
1144 s->regs[addr] = value; in aspeed_smc_write()
1146 asc->dma_ctrl(s, value); in aspeed_smc_write()
1149 s->regs[addr] = DMA_DRAM_ADDR(asc, value); in aspeed_smc_write()
1152 s->regs[addr] = DMA_FLASH_ADDR(asc, value); in aspeed_smc_write()
1155 s->regs[addr] = DMA_LENGTH(value); in aspeed_smc_write()
1158 s->regs[addr] = DMA_DRAM_ADDR_HIGH(value); in aspeed_smc_write()
1178 for (i = 0; i < asc->cs_num_max; i++) { in aspeed_smc_instance_init()
1179 object_initialize_child(obj, "flash[*]", &s->flashes[i], in aspeed_smc_instance_init()
1189 if (!s->dram_mr) { in aspeed_smc_dma_setup()
1194 address_space_init(&s->flash_as, &s->mmio_flash, in aspeed_smc_dma_setup()
1195 TYPE_ASPEED_SMC ".dma-flash"); in aspeed_smc_dma_setup()
1196 address_space_init(&s->dram_as, s->dram_mr, in aspeed_smc_dma_setup()
1197 TYPE_ASPEED_SMC ".dma-dram"); in aspeed_smc_dma_setup()
1209 s->r_conf = asc->r_conf; in aspeed_smc_realize()
1210 s->r_ce_ctrl = asc->r_ce_ctrl; in aspeed_smc_realize()
1211 s->r_ctrl0 = asc->r_ctrl0; in aspeed_smc_realize()
1212 s->r_timings = asc->r_timings; in aspeed_smc_realize()
1213 s->conf_enable_w0 = asc->conf_enable_w0; in aspeed_smc_realize()
1215 /* DMA irq. Keep it first for the initialization in the SoC */ in aspeed_smc_realize()
1216 sysbus_init_irq(sbd, &s->irq); in aspeed_smc_realize()
1218 s->spi = ssi_create_bus(dev, NULL); in aspeed_smc_realize()
1221 s->cs_lines = g_new0(qemu_irq, asc->cs_num_max); in aspeed_smc_realize()
1222 qdev_init_gpio_out_named(DEVICE(s), s->cs_lines, "cs", asc->cs_num_max); in aspeed_smc_realize()
1224 /* The memory region for the controller registers */ in aspeed_smc_realize()
1225 memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_smc_ops, s, in aspeed_smc_realize()
1226 TYPE_ASPEED_SMC, asc->nregs * 4); in aspeed_smc_realize()
1227 sysbus_init_mmio(sbd, &s->mmio); in aspeed_smc_realize()
1232 * address depends on the SoC model and controller type. in aspeed_smc_realize()
1234 memory_region_init(&s->mmio_flash_container, OBJECT(s), in aspeed_smc_realize()
1236 asc->flash_window_size); in aspeed_smc_realize()
1237 sysbus_init_mmio(sbd, &s->mmio_flash_container); in aspeed_smc_realize()
1239 memory_region_init_io(&s->mmio_flash, OBJECT(s), in aspeed_smc_realize()
1242 asc->flash_window_size); in aspeed_smc_realize()
1243 memory_region_add_subregion(&s->mmio_flash_container, 0x0, in aspeed_smc_realize()
1244 &s->mmio_flash); in aspeed_smc_realize()
1249 * window of the controller but, there is not necessarily a flash in aspeed_smc_realize()
1253 for (i = 0; i < asc->cs_num_max; ++i) { in aspeed_smc_realize()
1254 AspeedSMCFlash *fl = &s->flashes[i]; in aspeed_smc_realize()
1256 if (!object_property_set_link(OBJECT(fl), "controller", OBJECT(s), in aspeed_smc_realize()
1267 memory_region_add_subregion(&s->mmio_flash, offset, &fl->mmio); in aspeed_smc_realize()
1268 offset += asc->segments[i].size; in aspeed_smc_realize()
1271 /* DMA support */ in aspeed_smc_realize()
1291 DEFINE_PROP_BOOL("inject-failure", AspeedSMCState, inject_failure, false),
1292 DEFINE_PROP_UINT64("dram-base", AspeedSMCState, dram_base, 0),
1301 dc->realize = aspeed_smc_realize; in aspeed_smc_class_init()
1304 dc->vmsd = &vmstate_aspeed_smc; in aspeed_smc_class_init()
1320 g_autofree char *name = g_strdup_printf(TYPE_ASPEED_SMC_FLASH ".%d", s->cs); in aspeed_smc_flash_realize()
1322 if (!s->controller) { in aspeed_smc_flash_realize()
1323 error_setg(errp, TYPE_ASPEED_SMC_FLASH ": 'controller' link not set"); in aspeed_smc_flash_realize()
1327 s->asc = ASPEED_SMC_GET_CLASS(s->controller); in aspeed_smc_flash_realize()
1333 memory_region_init_io(&s->mmio, OBJECT(s), s->asc->reg_ops, in aspeed_smc_flash_realize()
1334 s, name, s->asc->segments[s->cs].size); in aspeed_smc_flash_realize()
1335 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); in aspeed_smc_flash_realize()
1340 DEFINE_PROP_LINK("controller", AspeedSMCFlash, controller, TYPE_ASPEED_SMC,
1348 dc->desc = "Aspeed SMC Flash device region"; in aspeed_smc_flash_class_init()
1349 dc->realize = aspeed_smc_flash_realize; in aspeed_smc_flash_class_init()
1363 * absolute addresses which should be part of the overall controller
1370 reg |= ((seg->addr >> 23) & SEG_START_MASK) << SEG_START_SHIFT; in aspeed_smc_segment_to_reg()
1371 reg |= (((seg->addr + seg->size) >> 23) & SEG_END_MASK) << SEG_END_SHIFT; in aspeed_smc_segment_to_reg()
1378 seg->addr = ((reg >> SEG_START_SHIFT) & SEG_START_MASK) << 23; in aspeed_smc_reg_to_segment()
1379 seg->size = (((reg >> SEG_END_SHIFT) & SEG_END_MASK) << 23) - seg->addr; in aspeed_smc_reg_to_segment()
1391 dc->desc = "Aspeed 2400 SMC Controller"; in aspeed_2400_smc_class_init()
1392 asc->r_conf = R_CONF; in aspeed_2400_smc_class_init()
1393 asc->r_ce_ctrl = R_CE_CTRL; in aspeed_2400_smc_class_init()
1394 asc->r_ctrl0 = R_CTRL0; in aspeed_2400_smc_class_init()
1395 asc->r_timings = R_TIMINGS; in aspeed_2400_smc_class_init()
1396 asc->nregs_timings = 1; in aspeed_2400_smc_class_init()
1397 asc->conf_enable_w0 = CONF_ENABLE_W0; in aspeed_2400_smc_class_init()
1398 asc->cs_num_max = 1; in aspeed_2400_smc_class_init()
1399 asc->segments = aspeed_2400_smc_segments; in aspeed_2400_smc_class_init()
1400 asc->flash_window_base = 0x10000000; in aspeed_2400_smc_class_init()
1401 asc->flash_window_size = 0x6000000; in aspeed_2400_smc_class_init()
1402 asc->features = 0x0; in aspeed_2400_smc_class_init()
1403 asc->nregs = ASPEED_SMC_R_SMC_MAX; in aspeed_2400_smc_class_init()
1404 asc->segment_to_reg = aspeed_smc_segment_to_reg; in aspeed_2400_smc_class_init()
1405 asc->reg_to_segment = aspeed_smc_reg_to_segment; in aspeed_2400_smc_class_init()
1406 asc->dma_ctrl = aspeed_smc_dma_ctrl; in aspeed_2400_smc_class_init()
1407 asc->reg_ops = &aspeed_smc_flash_ops; in aspeed_2400_smc_class_init()
1411 .name = "aspeed.smc-ast2400",
1437 dc->desc = "Aspeed 2400 FMC Controller"; in aspeed_2400_fmc_class_init()
1438 asc->r_conf = R_CONF; in aspeed_2400_fmc_class_init()
1439 asc->r_ce_ctrl = R_CE_CTRL; in aspeed_2400_fmc_class_init()
1440 asc->r_ctrl0 = R_CTRL0; in aspeed_2400_fmc_class_init()
1441 asc->r_timings = R_TIMINGS; in aspeed_2400_fmc_class_init()
1442 asc->nregs_timings = 1; in aspeed_2400_fmc_class_init()
1443 asc->conf_enable_w0 = CONF_ENABLE_W0; in aspeed_2400_fmc_class_init()
1444 asc->cs_num_max = 5; in aspeed_2400_fmc_class_init()
1445 asc->segments = aspeed_2400_fmc_segments; in aspeed_2400_fmc_class_init()
1446 asc->segment_addr_mask = 0xffff0000; in aspeed_2400_fmc_class_init()
1447 asc->resets = aspeed_2400_fmc_resets; in aspeed_2400_fmc_class_init()
1448 asc->flash_window_base = 0x20000000; in aspeed_2400_fmc_class_init()
1449 asc->flash_window_size = 0x10000000; in aspeed_2400_fmc_class_init()
1450 asc->features = ASPEED_SMC_FEATURE_DMA; in aspeed_2400_fmc_class_init()
1451 asc->dma_flash_mask = 0x0FFFFFFC; in aspeed_2400_fmc_class_init()
1452 asc->dma_dram_mask = 0x1FFFFFFC; in aspeed_2400_fmc_class_init()
1453 asc->dma_start_length = 4; in aspeed_2400_fmc_class_init()
1454 asc->nregs = ASPEED_SMC_R_MAX; in aspeed_2400_fmc_class_init()
1455 asc->segment_to_reg = aspeed_smc_segment_to_reg; in aspeed_2400_fmc_class_init()
1456 asc->reg_to_segment = aspeed_smc_reg_to_segment; in aspeed_2400_fmc_class_init()
1457 asc->dma_ctrl = aspeed_smc_dma_ctrl; in aspeed_2400_fmc_class_init()
1458 asc->reg_ops = &aspeed_smc_flash_ops; in aspeed_2400_fmc_class_init()
1462 .name = "aspeed.fmc-ast2400",
1473 return s->regs[R_SPI_CTRL0] & CTRL_AST2400_SPI_4BYTE ? 4 : 3; in aspeed_2400_spi1_addr_width()
1481 dc->desc = "Aspeed 2400 SPI1 Controller"; in aspeed_2400_spi1_class_init()
1482 asc->r_conf = R_SPI_CONF; in aspeed_2400_spi1_class_init()
1483 asc->r_ce_ctrl = 0xff; in aspeed_2400_spi1_class_init()
1484 asc->r_ctrl0 = R_SPI_CTRL0; in aspeed_2400_spi1_class_init()
1485 asc->r_timings = R_SPI_TIMINGS; in aspeed_2400_spi1_class_init()
1486 asc->nregs_timings = 1; in aspeed_2400_spi1_class_init()
1487 asc->conf_enable_w0 = SPI_CONF_ENABLE_W0; in aspeed_2400_spi1_class_init()
1488 asc->cs_num_max = 1; in aspeed_2400_spi1_class_init()
1489 asc->segments = aspeed_2400_spi1_segments; in aspeed_2400_spi1_class_init()
1490 asc->flash_window_base = 0x30000000; in aspeed_2400_spi1_class_init()
1491 asc->flash_window_size = 0x10000000; in aspeed_2400_spi1_class_init()
1492 asc->features = 0x0; in aspeed_2400_spi1_class_init()
1493 asc->nregs = ASPEED_SMC_R_SPI_MAX; in aspeed_2400_spi1_class_init()
1494 asc->segment_to_reg = aspeed_smc_segment_to_reg; in aspeed_2400_spi1_class_init()
1495 asc->reg_to_segment = aspeed_smc_reg_to_segment; in aspeed_2400_spi1_class_init()
1496 asc->dma_ctrl = aspeed_smc_dma_ctrl; in aspeed_2400_spi1_class_init()
1497 asc->addr_width = aspeed_2400_spi1_addr_width; in aspeed_2400_spi1_class_init()
1498 asc->reg_ops = &aspeed_smc_flash_ops; in aspeed_2400_spi1_class_init()
1502 .name = "aspeed.spi1-ast2400",
1523 dc->desc = "Aspeed 2500 FMC Controller"; in aspeed_2500_fmc_class_init()
1524 asc->r_conf = R_CONF; in aspeed_2500_fmc_class_init()
1525 asc->r_ce_ctrl = R_CE_CTRL; in aspeed_2500_fmc_class_init()
1526 asc->r_ctrl0 = R_CTRL0; in aspeed_2500_fmc_class_init()
1527 asc->r_timings = R_TIMINGS; in aspeed_2500_fmc_class_init()
1528 asc->nregs_timings = 1; in aspeed_2500_fmc_class_init()
1529 asc->conf_enable_w0 = CONF_ENABLE_W0; in aspeed_2500_fmc_class_init()
1530 asc->cs_num_max = 3; in aspeed_2500_fmc_class_init()
1531 asc->segments = aspeed_2500_fmc_segments; in aspeed_2500_fmc_class_init()
1532 asc->segment_addr_mask = 0xffff0000; in aspeed_2500_fmc_class_init()
1533 asc->resets = aspeed_2500_fmc_resets; in aspeed_2500_fmc_class_init()
1534 asc->flash_window_base = 0x20000000; in aspeed_2500_fmc_class_init()
1535 asc->flash_window_size = 0x10000000; in aspeed_2500_fmc_class_init()
1536 asc->features = ASPEED_SMC_FEATURE_DMA; in aspeed_2500_fmc_class_init()
1537 asc->dma_flash_mask = 0x0FFFFFFC; in aspeed_2500_fmc_class_init()
1538 asc->dma_dram_mask = 0x3FFFFFFC; in aspeed_2500_fmc_class_init()
1539 asc->dma_start_length = 4; in aspeed_2500_fmc_class_init()
1540 asc->nregs = ASPEED_SMC_R_MAX; in aspeed_2500_fmc_class_init()
1541 asc->segment_to_reg = aspeed_smc_segment_to_reg; in aspeed_2500_fmc_class_init()
1542 asc->reg_to_segment = aspeed_smc_reg_to_segment; in aspeed_2500_fmc_class_init()
1543 asc->dma_ctrl = aspeed_smc_dma_ctrl; in aspeed_2500_fmc_class_init()
1544 asc->reg_ops = &aspeed_smc_flash_ops; in aspeed_2500_fmc_class_init()
1548 .name = "aspeed.fmc-ast2500",
1563 dc->desc = "Aspeed 2500 SPI1 Controller"; in aspeed_2500_spi1_class_init()
1564 asc->r_conf = R_CONF; in aspeed_2500_spi1_class_init()
1565 asc->r_ce_ctrl = R_CE_CTRL; in aspeed_2500_spi1_class_init()
1566 asc->r_ctrl0 = R_CTRL0; in aspeed_2500_spi1_class_init()
1567 asc->r_timings = R_TIMINGS; in aspeed_2500_spi1_class_init()
1568 asc->nregs_timings = 1; in aspeed_2500_spi1_class_init()
1569 asc->conf_enable_w0 = CONF_ENABLE_W0; in aspeed_2500_spi1_class_init()
1570 asc->cs_num_max = 2; in aspeed_2500_spi1_class_init()
1571 asc->segments = aspeed_2500_spi1_segments; in aspeed_2500_spi1_class_init()
1572 asc->segment_addr_mask = 0xffff0000; in aspeed_2500_spi1_class_init()
1573 asc->flash_window_base = 0x30000000; in aspeed_2500_spi1_class_init()
1574 asc->flash_window_size = 0x8000000; in aspeed_2500_spi1_class_init()
1575 asc->features = 0x0; in aspeed_2500_spi1_class_init()
1576 asc->nregs = ASPEED_SMC_R_MAX; in aspeed_2500_spi1_class_init()
1577 asc->segment_to_reg = aspeed_smc_segment_to_reg; in aspeed_2500_spi1_class_init()
1578 asc->reg_to_segment = aspeed_smc_reg_to_segment; in aspeed_2500_spi1_class_init()
1579 asc->dma_ctrl = aspeed_smc_dma_ctrl; in aspeed_2500_spi1_class_init()
1580 asc->reg_ops = &aspeed_smc_flash_ops; in aspeed_2500_spi1_class_init()
1584 .name = "aspeed.spi1-ast2500",
1599 dc->desc = "Aspeed 2500 SPI2 Controller"; in aspeed_2500_spi2_class_init()
1600 asc->r_conf = R_CONF; in aspeed_2500_spi2_class_init()
1601 asc->r_ce_ctrl = R_CE_CTRL; in aspeed_2500_spi2_class_init()
1602 asc->r_ctrl0 = R_CTRL0; in aspeed_2500_spi2_class_init()
1603 asc->r_timings = R_TIMINGS; in aspeed_2500_spi2_class_init()
1604 asc->nregs_timings = 1; in aspeed_2500_spi2_class_init()
1605 asc->conf_enable_w0 = CONF_ENABLE_W0; in aspeed_2500_spi2_class_init()
1606 asc->cs_num_max = 2; in aspeed_2500_spi2_class_init()
1607 asc->segments = aspeed_2500_spi2_segments; in aspeed_2500_spi2_class_init()
1608 asc->segment_addr_mask = 0xffff0000; in aspeed_2500_spi2_class_init()
1609 asc->flash_window_base = 0x38000000; in aspeed_2500_spi2_class_init()
1610 asc->flash_window_size = 0x8000000; in aspeed_2500_spi2_class_init()
1611 asc->features = 0x0; in aspeed_2500_spi2_class_init()
1612 asc->nregs = ASPEED_SMC_R_MAX; in aspeed_2500_spi2_class_init()
1613 asc->segment_to_reg = aspeed_smc_segment_to_reg; in aspeed_2500_spi2_class_init()
1614 asc->reg_to_segment = aspeed_smc_reg_to_segment; in aspeed_2500_spi2_class_init()
1615 asc->dma_ctrl = aspeed_smc_dma_ctrl; in aspeed_2500_spi2_class_init()
1616 asc->reg_ops = &aspeed_smc_flash_ops; in aspeed_2500_spi2_class_init()
1620 .name = "aspeed.spi2-ast2500",
1628 * controller window. The previous SoC AST2400 and AST2500 used
1640 if (!seg->size) { in aspeed_2600_smc_segment_to_reg()
1644 reg |= (seg->addr & AST2600_SEG_ADDR_MASK) >> 16; /* start offset */ in aspeed_2600_smc_segment_to_reg()
1645 reg |= (seg->addr + seg->size - 1) & AST2600_SEG_ADDR_MASK; /* end offset */ in aspeed_2600_smc_segment_to_reg()
1657 seg->addr = asc->flash_window_base + start_offset; in aspeed_2600_smc_reg_to_segment()
1658 seg->size = end_offset + MiB - start_offset; in aspeed_2600_smc_reg_to_segment()
1660 seg->addr = asc->flash_window_base; in aspeed_2600_smc_reg_to_segment()
1661 seg->size = 0; in aspeed_2600_smc_reg_to_segment()
1673 { 128 * MiB, 128 * MiB }, /* default is disabled but needed for -kernel */
1682 dc->desc = "Aspeed 2600 FMC Controller"; in aspeed_2600_fmc_class_init()
1683 asc->r_conf = R_CONF; in aspeed_2600_fmc_class_init()
1684 asc->r_ce_ctrl = R_CE_CTRL; in aspeed_2600_fmc_class_init()
1685 asc->r_ctrl0 = R_CTRL0; in aspeed_2600_fmc_class_init()
1686 asc->r_timings = R_TIMINGS; in aspeed_2600_fmc_class_init()
1687 asc->nregs_timings = 1; in aspeed_2600_fmc_class_init()
1688 asc->conf_enable_w0 = CONF_ENABLE_W0; in aspeed_2600_fmc_class_init()
1689 asc->cs_num_max = 3; in aspeed_2600_fmc_class_init()
1690 asc->segments = aspeed_2600_fmc_segments; in aspeed_2600_fmc_class_init()
1691 asc->segment_addr_mask = 0x0ff00ff0; in aspeed_2600_fmc_class_init()
1692 asc->resets = aspeed_2600_fmc_resets; in aspeed_2600_fmc_class_init()
1693 asc->flash_window_base = 0x20000000; in aspeed_2600_fmc_class_init()
1694 asc->flash_window_size = 0x10000000; in aspeed_2600_fmc_class_init()
1695 asc->features = ASPEED_SMC_FEATURE_DMA | in aspeed_2600_fmc_class_init()
1697 asc->dma_flash_mask = 0x0FFFFFFC; in aspeed_2600_fmc_class_init()
1698 asc->dma_dram_mask = 0x3FFFFFFC; in aspeed_2600_fmc_class_init()
1699 asc->dma_start_length = 1; in aspeed_2600_fmc_class_init()
1700 asc->nregs = ASPEED_SMC_R_MAX; in aspeed_2600_fmc_class_init()
1701 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg; in aspeed_2600_fmc_class_init()
1702 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment; in aspeed_2600_fmc_class_init()
1703 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; in aspeed_2600_fmc_class_init()
1704 asc->reg_ops = &aspeed_smc_flash_ops; in aspeed_2600_fmc_class_init()
1708 .name = "aspeed.fmc-ast2600",
1723 dc->desc = "Aspeed 2600 SPI1 Controller"; in aspeed_2600_spi1_class_init()
1724 asc->r_conf = R_CONF; in aspeed_2600_spi1_class_init()
1725 asc->r_ce_ctrl = R_CE_CTRL; in aspeed_2600_spi1_class_init()
1726 asc->r_ctrl0 = R_CTRL0; in aspeed_2600_spi1_class_init()
1727 asc->r_timings = R_TIMINGS; in aspeed_2600_spi1_class_init()
1728 asc->nregs_timings = 2; in aspeed_2600_spi1_class_init()
1729 asc->conf_enable_w0 = CONF_ENABLE_W0; in aspeed_2600_spi1_class_init()
1730 asc->cs_num_max = 2; in aspeed_2600_spi1_class_init()
1731 asc->segments = aspeed_2600_spi1_segments; in aspeed_2600_spi1_class_init()
1732 asc->segment_addr_mask = 0x0ff00ff0; in aspeed_2600_spi1_class_init()
1733 asc->flash_window_base = 0x30000000; in aspeed_2600_spi1_class_init()
1734 asc->flash_window_size = 0x10000000; in aspeed_2600_spi1_class_init()
1735 asc->features = ASPEED_SMC_FEATURE_DMA | in aspeed_2600_spi1_class_init()
1737 asc->dma_flash_mask = 0x0FFFFFFC; in aspeed_2600_spi1_class_init()
1738 asc->dma_dram_mask = 0x3FFFFFFC; in aspeed_2600_spi1_class_init()
1739 asc->dma_start_length = 1; in aspeed_2600_spi1_class_init()
1740 asc->nregs = ASPEED_SMC_R_MAX; in aspeed_2600_spi1_class_init()
1741 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg; in aspeed_2600_spi1_class_init()
1742 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment; in aspeed_2600_spi1_class_init()
1743 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; in aspeed_2600_spi1_class_init()
1744 asc->reg_ops = &aspeed_smc_flash_ops; in aspeed_2600_spi1_class_init()
1748 .name = "aspeed.spi1-ast2600",
1764 dc->desc = "Aspeed 2600 SPI2 Controller"; in aspeed_2600_spi2_class_init()
1765 asc->r_conf = R_CONF; in aspeed_2600_spi2_class_init()
1766 asc->r_ce_ctrl = R_CE_CTRL; in aspeed_2600_spi2_class_init()
1767 asc->r_ctrl0 = R_CTRL0; in aspeed_2600_spi2_class_init()
1768 asc->r_timings = R_TIMINGS; in aspeed_2600_spi2_class_init()
1769 asc->nregs_timings = 3; in aspeed_2600_spi2_class_init()
1770 asc->conf_enable_w0 = CONF_ENABLE_W0; in aspeed_2600_spi2_class_init()
1771 asc->cs_num_max = 3; in aspeed_2600_spi2_class_init()
1772 asc->segments = aspeed_2600_spi2_segments; in aspeed_2600_spi2_class_init()
1773 asc->segment_addr_mask = 0x0ff00ff0; in aspeed_2600_spi2_class_init()
1774 asc->flash_window_base = 0x50000000; in aspeed_2600_spi2_class_init()
1775 asc->flash_window_size = 0x10000000; in aspeed_2600_spi2_class_init()
1776 asc->features = ASPEED_SMC_FEATURE_DMA | in aspeed_2600_spi2_class_init()
1778 asc->dma_flash_mask = 0x0FFFFFFC; in aspeed_2600_spi2_class_init()
1779 asc->dma_dram_mask = 0x3FFFFFFC; in aspeed_2600_spi2_class_init()
1780 asc->dma_start_length = 1; in aspeed_2600_spi2_class_init()
1781 asc->nregs = ASPEED_SMC_R_MAX; in aspeed_2600_spi2_class_init()
1782 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg; in aspeed_2600_spi2_class_init()
1783 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment; in aspeed_2600_spi2_class_init()
1784 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; in aspeed_2600_spi2_class_init()
1785 asc->reg_ops = &aspeed_smc_flash_ops; in aspeed_2600_spi2_class_init()
1789 .name = "aspeed.spi2-ast2600",
1806 if (!seg->size) { in aspeed_1030_smc_segment_to_reg()
1810 reg |= (seg->addr & AST1030_SEG_ADDR_MASK) >> 16; /* start offset */ in aspeed_1030_smc_segment_to_reg()
1811 reg |= (seg->addr + seg->size - 1) & AST1030_SEG_ADDR_MASK; /* end offset */ in aspeed_1030_smc_segment_to_reg()
1823 seg->addr = asc->flash_window_base + start_offset; in aspeed_1030_smc_reg_to_segment()
1824 seg->size = end_offset + (512 * KiB) - start_offset; in aspeed_1030_smc_reg_to_segment()
1826 seg->addr = asc->flash_window_base; in aspeed_1030_smc_reg_to_segment()
1827 seg->size = 0; in aspeed_1030_smc_reg_to_segment()
1838 { 128 * MiB, 128 * MiB }, /* default is disabled but needed for -kernel */
1847 dc->desc = "Aspeed 1030 FMC Controller"; in aspeed_1030_fmc_class_init()
1848 asc->r_conf = R_CONF; in aspeed_1030_fmc_class_init()
1849 asc->r_ce_ctrl = R_CE_CTRL; in aspeed_1030_fmc_class_init()
1850 asc->r_ctrl0 = R_CTRL0; in aspeed_1030_fmc_class_init()
1851 asc->r_timings = R_TIMINGS; in aspeed_1030_fmc_class_init()
1852 asc->nregs_timings = 2; in aspeed_1030_fmc_class_init()
1853 asc->conf_enable_w0 = CONF_ENABLE_W0; in aspeed_1030_fmc_class_init()
1854 asc->cs_num_max = 2; in aspeed_1030_fmc_class_init()
1855 asc->segments = aspeed_1030_fmc_segments; in aspeed_1030_fmc_class_init()
1856 asc->segment_addr_mask = 0x0ff80ff8; in aspeed_1030_fmc_class_init()
1857 asc->resets = aspeed_1030_fmc_resets; in aspeed_1030_fmc_class_init()
1858 asc->flash_window_base = 0x80000000; in aspeed_1030_fmc_class_init()
1859 asc->flash_window_size = 0x10000000; in aspeed_1030_fmc_class_init()
1860 asc->features = ASPEED_SMC_FEATURE_DMA; in aspeed_1030_fmc_class_init()
1861 asc->dma_flash_mask = 0x0FFFFFFC; in aspeed_1030_fmc_class_init()
1862 asc->dma_dram_mask = 0x000BFFFC; in aspeed_1030_fmc_class_init()
1863 asc->dma_start_length = 1; in aspeed_1030_fmc_class_init()
1864 asc->nregs = ASPEED_SMC_R_MAX; in aspeed_1030_fmc_class_init()
1865 asc->segment_to_reg = aspeed_1030_smc_segment_to_reg; in aspeed_1030_fmc_class_init()
1866 asc->reg_to_segment = aspeed_1030_smc_reg_to_segment; in aspeed_1030_fmc_class_init()
1867 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; in aspeed_1030_fmc_class_init()
1868 asc->reg_ops = &aspeed_smc_flash_ops; in aspeed_1030_fmc_class_init()
1872 .name = "aspeed.fmc-ast1030",
1887 dc->desc = "Aspeed 1030 SPI1 Controller"; in aspeed_1030_spi1_class_init()
1888 asc->r_conf = R_CONF; in aspeed_1030_spi1_class_init()
1889 asc->r_ce_ctrl = R_CE_CTRL; in aspeed_1030_spi1_class_init()
1890 asc->r_ctrl0 = R_CTRL0; in aspeed_1030_spi1_class_init()
1891 asc->r_timings = R_TIMINGS; in aspeed_1030_spi1_class_init()
1892 asc->nregs_timings = 2; in aspeed_1030_spi1_class_init()
1893 asc->conf_enable_w0 = CONF_ENABLE_W0; in aspeed_1030_spi1_class_init()
1894 asc->cs_num_max = 2; in aspeed_1030_spi1_class_init()
1895 asc->segments = aspeed_1030_spi1_segments; in aspeed_1030_spi1_class_init()
1896 asc->segment_addr_mask = 0x0ff00ff0; in aspeed_1030_spi1_class_init()
1897 asc->flash_window_base = 0x90000000; in aspeed_1030_spi1_class_init()
1898 asc->flash_window_size = 0x10000000; in aspeed_1030_spi1_class_init()
1899 asc->features = ASPEED_SMC_FEATURE_DMA; in aspeed_1030_spi1_class_init()
1900 asc->dma_flash_mask = 0x0FFFFFFC; in aspeed_1030_spi1_class_init()
1901 asc->dma_dram_mask = 0x000BFFFC; in aspeed_1030_spi1_class_init()
1902 asc->dma_start_length = 1; in aspeed_1030_spi1_class_init()
1903 asc->nregs = ASPEED_SMC_R_MAX; in aspeed_1030_spi1_class_init()
1904 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg; in aspeed_1030_spi1_class_init()
1905 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment; in aspeed_1030_spi1_class_init()
1906 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; in aspeed_1030_spi1_class_init()
1907 asc->reg_ops = &aspeed_smc_flash_ops; in aspeed_1030_spi1_class_init()
1911 .name = "aspeed.spi1-ast1030",
1925 dc->desc = "Aspeed 1030 SPI2 Controller"; in aspeed_1030_spi2_class_init()
1926 asc->r_conf = R_CONF; in aspeed_1030_spi2_class_init()
1927 asc->r_ce_ctrl = R_CE_CTRL; in aspeed_1030_spi2_class_init()
1928 asc->r_ctrl0 = R_CTRL0; in aspeed_1030_spi2_class_init()
1929 asc->r_timings = R_TIMINGS; in aspeed_1030_spi2_class_init()
1930 asc->nregs_timings = 2; in aspeed_1030_spi2_class_init()
1931 asc->conf_enable_w0 = CONF_ENABLE_W0; in aspeed_1030_spi2_class_init()
1932 asc->cs_num_max = 2; in aspeed_1030_spi2_class_init()
1933 asc->segments = aspeed_1030_spi2_segments; in aspeed_1030_spi2_class_init()
1934 asc->segment_addr_mask = 0x0ff00ff0; in aspeed_1030_spi2_class_init()
1935 asc->flash_window_base = 0xb0000000; in aspeed_1030_spi2_class_init()
1936 asc->flash_window_size = 0x10000000; in aspeed_1030_spi2_class_init()
1937 asc->features = ASPEED_SMC_FEATURE_DMA; in aspeed_1030_spi2_class_init()
1938 asc->dma_flash_mask = 0x0FFFFFFC; in aspeed_1030_spi2_class_init()
1939 asc->dma_dram_mask = 0x000BFFFC; in aspeed_1030_spi2_class_init()
1940 asc->dma_start_length = 1; in aspeed_1030_spi2_class_init()
1941 asc->nregs = ASPEED_SMC_R_MAX; in aspeed_1030_spi2_class_init()
1942 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg; in aspeed_1030_spi2_class_init()
1943 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment; in aspeed_1030_spi2_class_init()
1944 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; in aspeed_1030_spi2_class_init()
1945 asc->reg_ops = &aspeed_smc_flash_ops; in aspeed_1030_spi2_class_init()
1949 .name = "aspeed.spi2-ast1030",
1966 if (!seg->size) { in aspeed_2700_smc_segment_to_reg()
1970 reg |= (seg->addr & AST2700_SEG_ADDR_MASK) >> 16; /* start offset */ in aspeed_2700_smc_segment_to_reg()
1971 reg |= (seg->addr + seg->size - 1) & AST2700_SEG_ADDR_MASK; /* end offset */ in aspeed_2700_smc_segment_to_reg()
1983 seg->addr = asc->flash_window_base + start_offset; in aspeed_2700_smc_reg_to_segment()
1984 seg->size = end_offset + (64 * KiB) - start_offset; in aspeed_2700_smc_reg_to_segment()
1986 seg->addr = asc->flash_window_base; in aspeed_2700_smc_reg_to_segment()
1987 seg->size = 0; in aspeed_2700_smc_reg_to_segment()
2020 { 128 * MiB, 128 * MiB }, /* default is disabled but needed for -kernel */
2021 { 256 * MiB, 128 * MiB }, /* default is disabled but needed for -kernel */
2030 dc->desc = "Aspeed 2700 FMC Controller"; in aspeed_2700_fmc_class_init()
2031 asc->r_conf = R_CONF; in aspeed_2700_fmc_class_init()
2032 asc->r_ce_ctrl = R_CE_CTRL; in aspeed_2700_fmc_class_init()
2033 asc->r_ctrl0 = R_CTRL0; in aspeed_2700_fmc_class_init()
2034 asc->r_timings = R_TIMINGS; in aspeed_2700_fmc_class_init()
2035 asc->nregs_timings = 3; in aspeed_2700_fmc_class_init()
2036 asc->conf_enable_w0 = CONF_ENABLE_W0; in aspeed_2700_fmc_class_init()
2037 asc->cs_num_max = 3; in aspeed_2700_fmc_class_init()
2038 asc->segments = aspeed_2700_fmc_segments; in aspeed_2700_fmc_class_init()
2039 asc->segment_addr_mask = 0xffffffff; in aspeed_2700_fmc_class_init()
2040 asc->resets = aspeed_2700_fmc_resets; in aspeed_2700_fmc_class_init()
2041 asc->flash_window_base = 0x100000000; in aspeed_2700_fmc_class_init()
2042 asc->flash_window_size = 1 * GiB; in aspeed_2700_fmc_class_init()
2043 asc->features = ASPEED_SMC_FEATURE_DMA | in aspeed_2700_fmc_class_init()
2045 asc->dma_flash_mask = 0x2FFFFFFC; in aspeed_2700_fmc_class_init()
2046 asc->dma_dram_mask = 0xFFFFFFFC; in aspeed_2700_fmc_class_init()
2047 asc->dma_start_length = 1; in aspeed_2700_fmc_class_init()
2048 asc->nregs = ASPEED_SMC_R_MAX; in aspeed_2700_fmc_class_init()
2049 asc->segment_to_reg = aspeed_2700_smc_segment_to_reg; in aspeed_2700_fmc_class_init()
2050 asc->reg_to_segment = aspeed_2700_smc_reg_to_segment; in aspeed_2700_fmc_class_init()
2051 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; in aspeed_2700_fmc_class_init()
2052 asc->reg_ops = &aspeed_2700_smc_flash_ops; in aspeed_2700_fmc_class_init()
2056 .name = "aspeed.fmc-ast2700",
2072 dc->desc = "Aspeed 2700 SPI0 Controller"; in aspeed_2700_spi0_class_init()
2073 asc->r_conf = R_CONF; in aspeed_2700_spi0_class_init()
2074 asc->r_ce_ctrl = R_CE_CTRL; in aspeed_2700_spi0_class_init()
2075 asc->r_ctrl0 = R_CTRL0; in aspeed_2700_spi0_class_init()
2076 asc->r_timings = R_TIMINGS; in aspeed_2700_spi0_class_init()
2077 asc->nregs_timings = 2; in aspeed_2700_spi0_class_init()
2078 asc->conf_enable_w0 = CONF_ENABLE_W0; in aspeed_2700_spi0_class_init()
2079 asc->cs_num_max = 2; in aspeed_2700_spi0_class_init()
2080 asc->segments = aspeed_2700_spi0_segments; in aspeed_2700_spi0_class_init()
2081 asc->segment_addr_mask = 0xffffffff; in aspeed_2700_spi0_class_init()
2082 asc->flash_window_base = 0x180000000; in aspeed_2700_spi0_class_init()
2083 asc->flash_window_size = 1 * GiB; in aspeed_2700_spi0_class_init()
2084 asc->features = ASPEED_SMC_FEATURE_DMA | in aspeed_2700_spi0_class_init()
2086 asc->dma_flash_mask = 0x2FFFFFFC; in aspeed_2700_spi0_class_init()
2087 asc->dma_dram_mask = 0xFFFFFFFC; in aspeed_2700_spi0_class_init()
2088 asc->dma_start_length = 1; in aspeed_2700_spi0_class_init()
2089 asc->nregs = ASPEED_SMC_R_MAX; in aspeed_2700_spi0_class_init()
2090 asc->segment_to_reg = aspeed_2700_smc_segment_to_reg; in aspeed_2700_spi0_class_init()
2091 asc->reg_to_segment = aspeed_2700_smc_reg_to_segment; in aspeed_2700_spi0_class_init()
2092 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; in aspeed_2700_spi0_class_init()
2093 asc->reg_ops = &aspeed_2700_smc_flash_ops; in aspeed_2700_spi0_class_init()
2097 .name = "aspeed.spi0-ast2700",
2112 dc->desc = "Aspeed 2700 SPI1 Controller"; in aspeed_2700_spi1_class_init()
2113 asc->r_conf = R_CONF; in aspeed_2700_spi1_class_init()
2114 asc->r_ce_ctrl = R_CE_CTRL; in aspeed_2700_spi1_class_init()
2115 asc->r_ctrl0 = R_CTRL0; in aspeed_2700_spi1_class_init()
2116 asc->r_timings = R_TIMINGS; in aspeed_2700_spi1_class_init()
2117 asc->nregs_timings = 2; in aspeed_2700_spi1_class_init()
2118 asc->conf_enable_w0 = CONF_ENABLE_W0; in aspeed_2700_spi1_class_init()
2119 asc->cs_num_max = 2; in aspeed_2700_spi1_class_init()
2120 asc->segments = aspeed_2700_spi1_segments; in aspeed_2700_spi1_class_init()
2121 asc->segment_addr_mask = 0xffffffff; in aspeed_2700_spi1_class_init()
2122 asc->flash_window_base = 0x200000000; in aspeed_2700_spi1_class_init()
2123 asc->flash_window_size = 1 * GiB; in aspeed_2700_spi1_class_init()
2124 asc->features = ASPEED_SMC_FEATURE_DMA | in aspeed_2700_spi1_class_init()
2126 asc->dma_flash_mask = 0x2FFFFFFC; in aspeed_2700_spi1_class_init()
2127 asc->dma_dram_mask = 0xFFFFFFFC; in aspeed_2700_spi1_class_init()
2128 asc->dma_start_length = 1; in aspeed_2700_spi1_class_init()
2129 asc->nregs = ASPEED_SMC_R_MAX; in aspeed_2700_spi1_class_init()
2130 asc->segment_to_reg = aspeed_2700_smc_segment_to_reg; in aspeed_2700_spi1_class_init()
2131 asc->reg_to_segment = aspeed_2700_smc_reg_to_segment; in aspeed_2700_spi1_class_init()
2132 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; in aspeed_2700_spi1_class_init()
2133 asc->reg_ops = &aspeed_2700_smc_flash_ops; in aspeed_2700_spi1_class_init()
2137 .name = "aspeed.spi1-ast2700",
2152 dc->desc = "Aspeed 2700 SPI2 Controller"; in aspeed_2700_spi2_class_init()
2153 asc->r_conf = R_CONF; in aspeed_2700_spi2_class_init()
2154 asc->r_ce_ctrl = R_CE_CTRL; in aspeed_2700_spi2_class_init()
2155 asc->r_ctrl0 = R_CTRL0; in aspeed_2700_spi2_class_init()
2156 asc->r_timings = R_TIMINGS; in aspeed_2700_spi2_class_init()
2157 asc->nregs_timings = 2; in aspeed_2700_spi2_class_init()
2158 asc->conf_enable_w0 = CONF_ENABLE_W0; in aspeed_2700_spi2_class_init()
2159 asc->cs_num_max = 2; in aspeed_2700_spi2_class_init()
2160 asc->segments = aspeed_2700_spi2_segments; in aspeed_2700_spi2_class_init()
2161 asc->segment_addr_mask = 0xffffffff; in aspeed_2700_spi2_class_init()
2162 asc->flash_window_base = 0x280000000; in aspeed_2700_spi2_class_init()
2163 asc->flash_window_size = 1 * GiB; in aspeed_2700_spi2_class_init()
2164 asc->features = ASPEED_SMC_FEATURE_DMA | in aspeed_2700_spi2_class_init()
2166 asc->dma_flash_mask = 0x0FFFFFFC; in aspeed_2700_spi2_class_init()
2167 asc->dma_dram_mask = 0xFFFFFFFC; in aspeed_2700_spi2_class_init()
2168 asc->dma_start_length = 1; in aspeed_2700_spi2_class_init()
2169 asc->nregs = ASPEED_SMC_R_MAX; in aspeed_2700_spi2_class_init()
2170 asc->segment_to_reg = aspeed_2700_smc_segment_to_reg; in aspeed_2700_spi2_class_init()
2171 asc->reg_to_segment = aspeed_2700_smc_reg_to_segment; in aspeed_2700_spi2_class_init()
2172 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; in aspeed_2700_spi2_class_init()
2173 asc->reg_ops = &aspeed_2700_smc_flash_ops; in aspeed_2700_spi2_class_init()
2177 .name = "aspeed.spi2-ast2700",