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/qemu/tests/tcg/mips/user/ase/msa/
H A Dtest_msa_run_64r6el.sh8 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_b_64r6el
9 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_h_64r6el
10 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_w_64r6el
11 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_d_64r6el
12 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_b_64r6el
13 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_h_64r6el
14 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_w_64r6el
15 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_d_64r6el
16 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pcnt_b_64r6el
17 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pcnt_h_64r6el
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H A Dtest_msa_run_32r5el.sh8 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_b_32r5el
9 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_h_32r5el
10 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_w_32r5el
11 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_d_32r5el
12 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_b_32r5el
13 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_h_32r5el
14 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_w_32r5el
15 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_d_32r5el
16 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pcnt_b_32r5el
17 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pcnt_h_32r5el
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H A Dtest_msa_run_64r6eb.sh8 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_b_64r6eb
9 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_h_64r6eb
10 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_w_64r6eb
11 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_d_64r6eb
12 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_b_64r6eb
13 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_h_64r6eb
14 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_w_64r6eb
15 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_d_64r6eb
16 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pcnt_b_64r6eb
17 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pcnt_h_64r6eb
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H A Dtest_msa_run_32r5eb.sh8 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_b_32r5eb
9 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_h_32r5eb
10 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_w_32r5eb
11 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_d_32r5eb
12 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_b_32r5eb
13 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_h_32r5eb
14 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_w_32r5eb
15 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_d_32r5eb
16 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pcnt_b_32r5eb
17 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pcnt_h_32r5eb
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/qemu/target/arm/tcg/
H A Dcpu-v7m.c12 #include "cpu.h"
13 #include "accel/tcg/cpu-ops.h"
22 ARMCPU *cpu = ARM_CPU(cs); in arm_v7m_cpu_exec_interrupt() local
23 CPUARMState *env = &cpu->env; in arm_v7m_cpu_exec_interrupt()
47 ARMCPU *cpu = ARM_CPU(obj); in cortex_m0_initfn() local
48 set_feature(&cpu->env, ARM_FEATURE_V6); in cortex_m0_initfn()
49 set_feature(&cpu->env, ARM_FEATURE_M); in cortex_m0_initfn()
51 cpu->midr = 0x410cc200; in cortex_m0_initfn()
61 cpu->isar.id_pfr0 = 0x00000030; in cortex_m0_initfn()
62 cpu->isar.id_pfr1 = 0x00000200; in cortex_m0_initfn()
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H A Dcpu32.c12 #include "cpu.h"
13 #include "accel/tcg/cpu-ops.h"
22 /* Share AArch32 -cpu max features with AArch64. */
23 void aa32_max_features(ARMCPU *cpu) in aa32_max_features() argument
28 t = cpu->isar.id_isar5; in aa32_max_features()
35 cpu->isar.id_isar5 = t; in aa32_max_features()
37 t = cpu->isar.id_isar6; in aa32_max_features()
45 cpu->isar.id_isar6 = t; in aa32_max_features()
47 t = cpu->isar.mvfr1; in aa32_max_features()
50 cpu->isar.mvfr1 = t; in aa32_max_features()
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H A Dcpu64.c23 #include "cpu.h"
29 #include "cpu-features.h"
34 ARMCPU *cpu = ARM_CPU(obj); in aarch64_a35_initfn() local
36 cpu->dtb_compatible = "arm,cortex-a35"; in aarch64_a35_initfn()
37 set_feature(&cpu->env, ARM_FEATURE_V8); in aarch64_a35_initfn()
38 set_feature(&cpu->env, ARM_FEATURE_NEON); in aarch64_a35_initfn()
39 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in aarch64_a35_initfn()
40 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in aarch64_a35_initfn()
41 set_feature(&cpu->env, ARM_FEATURE_AARCH64); in aarch64_a35_initfn()
42 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); in aarch64_a35_initfn()
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/qemu/target/i386/emulate/
H A Dx86.h198 #define x86_reg(cpu, reg) ((x86_register *) &cpu->regs[reg]) argument
200 #define RRX(cpu, reg) (x86_reg(cpu, reg)->rrx) argument
201 #define RAX(cpu) RRX(cpu, R_EAX) argument
202 #define RCX(cpu) RRX(cpu, R_ECX) argument
203 #define RDX(cpu) RRX(cpu, R_EDX) argument
204 #define RBX(cpu) RRX(cpu, R_EBX) argument
205 #define RSP(cpu) RRX(cpu, R_ESP) argument
206 #define RBP(cpu) RRX(cpu, R_EBP) argument
207 #define RSI(cpu) RRX(cpu, R_ESI) argument
208 #define RDI(cpu) RRX(cpu, R_EDI) argument
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/qemu/hw/core/
H A Dcpu-system.c2 * QEMU CPU model (system specific)
30 #include "hw/core/sysemu-cpu-ops.h"
34 bool cpu_has_work(CPUState *cpu) in cpu_has_work() argument
36 return cpu->cc->sysemu_ops->has_work(cpu); in cpu_has_work()
39 bool cpu_paging_enabled(const CPUState *cpu) in cpu_paging_enabled() argument
41 if (cpu->cc->sysemu_ops->get_paging_enabled) { in cpu_paging_enabled()
42 return cpu->cc->sysemu_ops->get_paging_enabled(cpu); in cpu_paging_enabled()
48 bool cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, in cpu_get_memory_mapping() argument
51 if (cpu->cc->sysemu_ops->get_memory_mapping) { in cpu_get_memory_mapping()
52 return cpu->cc->sysemu_ops->get_memory_mapping(cpu, list, errp); in cpu_get_memory_mapping()
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H A Dcpu-common.c2 * QEMU CPU model
23 #include "hw/core/cpu.h"
43 CPUState *cpu; in cpu_by_arch_id() local
45 CPU_FOREACH(cpu) { in cpu_by_arch_id()
46 if (cpu->cc->get_arch_id(cpu) == id) { in cpu_by_arch_id()
47 return cpu; in cpu_by_arch_id()
61 CPUState *cpu = CPU(object_new(typename)); in cpu_create() local
62 if (!qdev_realize(DEVICE(cpu), NULL, &err)) { in cpu_create()
64 object_unref(OBJECT(cpu)); in cpu_create()
67 return cpu; in cpu_create()
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/qemu/target/arm/
H A Dcpu64.c2 * QEMU AArch64 CPU
23 #include "cpu.h"
36 #include "cpu-features.h"
39 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) in arm_cpu_sve_finalize() argument
56 uint32_t vq_map = cpu->sve_vq.map; in arm_cpu_sve_finalize()
57 uint32_t vq_init = cpu->sve_vq.init; in arm_cpu_sve_finalize()
63 * CPU models specify a set of supported vector lengths which are in arm_cpu_sve_finalize()
70 cpu->sve_vq.supported = kvm_arm_sve_get_vls(cpu); in arm_cpu_sve_finalize()
71 vq_supported = cpu->sve_vq.supported; in arm_cpu_sve_finalize()
73 assert(!cpu_isar_feature(aa64_sve, cpu)); in arm_cpu_sve_finalize()
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H A Dcpu.c2 * QEMU ARM CPU
30 #include "cpu.h"
33 #include "accel/tcg/cpu-ops.h"
36 #include "cpu-features.h"
53 #include "target/arm/cpu-qom.h"
58 ARMCPU *cpu = ARM_CPU(cs); in arm_cpu_set_pc() local
59 CPUARMState *env = &cpu->env; in arm_cpu_set_pc()
72 ARMCPU *cpu = ARM_CPU(cs); in arm_cpu_get_pc() local
73 CPUARMState *env = &cpu->env; in arm_cpu_get_pc()
143 ARMCPU *cpu = ARM_CPU(cs); in arm_cpu_has_work() local
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/qemu/include/hw/core/
H A Dcpu.h2 * QEMU CPU model
44 * SECTION:cpu
45 * @section_id: QEMU-cpu
46 * @title: CPU Class
50 #define TYPE_CPU "cpu"
56 #define CPU(obj) ((CPUState *)(obj)) macro
66 DECLARE_CLASS_CHECKERS(CPUClass, CPU,
73 * @CPU_MODULE_OBJ_NAME: the CPU name in uppercase with underscore separators
75 * This macro is typically used in "cpu-qom.h" header file, and will:
77 * - create the typedefs for the CPU object and class structs
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/qemu/
H A Dcpu-common.c2 * CPU thread main loop - common bits for user and system mode emulation
22 #include "exec/cpu-common.h"
23 #include "hw/core/cpu.h"
81 void cpu_list_add(CPUState *cpu) in cpu_list_add() argument
86 if (cpu->cpu_index == UNASSIGNED_CPU_INDEX) { in cpu_list_add()
88 cpu->cpu_index = cpu_get_free_index(); in cpu_list_add()
89 assert(cpu->cpu_index != UNASSIGNED_CPU_INDEX); in cpu_list_add()
93 QTAILQ_INSERT_TAIL_RCU(&cpus_queue, cpu, node); in cpu_list_add()
97 void cpu_list_remove(CPUState *cpu) in cpu_list_remove() argument
100 if (!QTAILQ_IN_USE(cpu, node)) { in cpu_list_remove()
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/qemu/target/s390x/
H A Dcpu-system.c2 * QEMU S/390 CPU - System-only code
26 #include "cpu.h"
40 #include "hw/core/sysemu-cpu-ops.h"
44 S390CPU *cpu = S390_CPU(cs); in s390_cpu_has_work() local
47 if (s390_cpu_get_state(cpu) != S390_CPU_STATE_LOAD && in s390_cpu_has_work()
48 s390_cpu_get_state(cpu) != S390_CPU_STATE_OPERATING) { in s390_cpu_has_work()
56 return s390_cpu_has_int(cpu); in s390_cpu_has_work()
62 S390CPU *cpu = S390_CPU(s); in s390_cpu_load_normal() local
67 cpu->env.psw.mask = spsw & PSW_MASK_SHORT_CTRL; in s390_cpu_load_normal()
72 cpu->env.psw.mask ^= PSW_MASK_SHORTPSW; in s390_cpu_load_normal()
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/qemu/accel/tcg/
H A Dtcg-accel-ops-rr.c34 #include "exec/cpu-common.h"
43 CPUState *cpu; in rr_kick_vcpu_thread() local
45 CPU_FOREACH(cpu) { in rr_kick_vcpu_thread()
46 cpu_exit(cpu); in rr_kick_vcpu_thread()
55 * timer event we force a cpu->exit so the next vCPU can get
73 CPUState *cpu; in rr_kick_next_cpu() local
75 cpu = qatomic_read(&rr_current_cpu); in rr_kick_next_cpu()
76 if (cpu) { in rr_kick_next_cpu()
77 cpu_exit(cpu); in rr_kick_next_cpu()
79 /* Finish kicking this cpu before reading again. */ in rr_kick_next_cpu()
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H A Dcpu-exec.c24 #include "hw/core/cpu.h"
25 #include "accel/tcg/cpu-ops.h"
29 #include "exec/cpu-common.h"
30 #include "exec/cpu-interrupt.h"
70 static void align_clocks(SyncClocks *sc, CPUState *cpu) in align_clocks() argument
78 cpu_icount = cpu->icount_extra + cpu->neg.icount_decr.u16.low; in align_clocks()
121 static void init_delay_params(SyncClocks *sc, CPUState *cpu) in init_delay_params() argument
129 = cpu->icount_extra + cpu->neg.icount_decr.u16.low; in init_delay_params()
142 static void align_clocks(SyncClocks *sc, const CPUState *cpu) in align_clocks() argument
146 static void init_delay_params(SyncClocks *sc, const CPUState *cpu) in init_delay_params() argument
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/qemu/system/
H A Dcpus.c36 #include "exec/cpu-common.h"
45 #include "system/cpu-timers.h"
77 bool cpu_is_stopped(CPUState *cpu) in cpu_is_stopped() argument
79 return cpu->stopped || !runstate_is_running(); in cpu_is_stopped()
82 bool cpu_work_list_empty(CPUState *cpu) in cpu_work_list_empty() argument
84 return QSIMPLEQ_EMPTY_ATOMIC(&cpu->work_list); in cpu_work_list_empty()
87 bool cpu_thread_is_idle(CPUState *cpu) in cpu_thread_is_idle() argument
89 if (cpu->stop || !cpu_work_list_empty(cpu)) { in cpu_thread_is_idle()
92 if (cpu_is_stopped(cpu)) { in cpu_thread_is_idle()
95 if (!cpu->halted || cpu_has_work(cpu)) { in cpu_thread_is_idle()
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/qemu/docs/system/
H A Dcpu-models-x86.rst.inc1 Recommendations for KVM CPU model configuration on x86 hosts
5 CPU models on x86 hosts. The goals are to maximise performance, while
6 protecting guest OS against various CPU hardware flaws, and optionally
7 enabling live migration between hosts with heterogeneous CPU models.
10 Two ways to configure CPU models with QEMU / KVM
15 This passes the host CPU model features, model, stepping, exactly to
16 the guest. Note that KVM may filter out some host CPU model features
19 stable CPU is exposed to the guest across hosts. This is the
20 recommended CPU to use, provided live migration is not required.
24 QEMU comes with a number of predefined named CPU models, that
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/qemu/hw/openrisc/
H A Dcputimer.c22 #include "cpu.h"
38 void cpu_openrisc_count_set(OpenRISCCPU *cpu, uint32_t val) in cpu_openrisc_count_set() argument
45 uint32_t cpu_openrisc_count_get(OpenRISCCPU *cpu) in cpu_openrisc_count_get() argument
51 void cpu_openrisc_count_update(OpenRISCCPU *cpu) in cpu_openrisc_count_update() argument
55 if (!cpu->env.is_counting) { in cpu_openrisc_count_update()
64 void cpu_openrisc_timer_update(OpenRISCCPU *cpu) in cpu_openrisc_timer_update() argument
69 if (!cpu->env.is_counting) { in cpu_openrisc_timer_update()
73 cpu_openrisc_count_update(cpu); in cpu_openrisc_timer_update()
76 if ((cpu->env.ttmr & TTMR_TP) <= (or1k_timer->ttcr & TTMR_TP)) { in cpu_openrisc_timer_update()
78 wait += cpu->env.ttmr & TTMR_TP; in cpu_openrisc_timer_update()
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/qemu/target/riscv/tcg/
H A Dtcg-cpu.c2 * riscv TCG cpu class initialization
22 #include "tcg-cpu.h"
23 #include "cpu.h"
33 #include "accel/accel-cpu-target.h"
34 #include "accel/tcg/cpu-ops.h"
73 static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, in riscv_cpu_write_misa_bit() argument
76 CPURISCVState *env = &cpu->env; in riscv_cpu_write_misa_bit()
104 RISCVCPU *cpu = env_archcpu(env); in riscv_get_tb_cpu_state() local
109 if (cpu->cfg.ext_zve32x) { in riscv_get_tb_cpu_state()
122 uint32_t vlmax = vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul); in riscv_get_tb_cpu_state()
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/qemu/docs/specs/
H A Dacpi_cpu_hotplug.rst1 QEMU<->ACPI BIOS CPU hotplug interface
4 QEMU supports CPU hotplug via ACPI. This document
7 ACPI BIOS GPE.2 handler is dedicated for notifying OS about CPU hot-add
11 Legacy ACPI CPU hotplug interface registers
14 CPU present bitmap for:
18 - One bit per CPU. Bit position reflects corresponding CPU APIC ID. Read-only.
20 to modern CPU hotplug interface, write 0 into it to do switch.
22 QEMU sets corresponding CPU bit on hot-add event and issues SCI
23 with GPE.2 event set. CPU present map is read by ACPI BIOS GPE.2 handler
24 to notify OS about CPU hot-add events. CPU hot-remove isn't supported.
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/qemu/docs/system/arm/
H A Dcpu-features.rst1 Arm CPU Features
4 CPU features are optional features that a CPU of supporting type may
5 choose to implement or not. In QEMU, optional CPU features have
6 corresponding boolean CPU proprieties that, when enabled, indicate
8 indicate that it is not implemented. An example of an Arm CPU feature
9 is the Performance Monitoring Unit (PMU). CPU types such as the
13 a PMU, then the ``-cpu`` parameter should contain ``pmu=off`` on the QEMU
14 command line, i.e. ``-cpu cortex-a15,pmu=off``.
16 As not all CPU types support all optional CPU features, then whether or
17 not a CPU property exists depends on the CPU type. For example, CPUs
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/qemu/include/exec/
H A Dcputlb.h2 * Common CPU TLB handling
23 #include "exec/cpu-common.h"
34 void tlb_reset_dirty(CPUState *cpu, uintptr_t start, uintptr_t length);
40 * @cpu: CPU context
45 * Add an entry to @cpu tlb index @mmu_idx. All of the fields of
57 void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr,
62 * @cpu: CPU to add this TLB entry for
70 * Add an entry to this CPU's TLB (a mapping from virtual address
72 * transaction attributes. This is generally called by the target CPU
82 void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr,
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/qemu/hw/s390x/
H A Dcpu-topology.c3 * CPU Topology
14 * guest with CPU and KVM specificity will be implemented inside
23 #include "target/s390x/cpu.h"
25 #include "hw/s390x/cpu-topology.h"
36 /* will be initialized after the CPU model is realized */
43 * @cpu: s390x CPU
56 * @cpu: s390x CPU
59 * for a cpu.
61 static int s390_socket_nb(S390CPU *cpu) in s390_socket_nb() argument
63 return s390_socket_nb_from_ids(cpu->env.drawer_id, cpu->env.book_id, in s390_socket_nb()
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